Gate High Electron Mobility Transistors Research Articles

K/Ka‐Band–GaN–High‐Electron‐Mobility Transistors Technology with 700 mS mm−1 Extrinsic Transconductance

In this study, the impacts of fabrication technology and epitaxial layer design on the transconductance (gm) of radio frequency AlGaN/GaN high‐electron‐mobility transistors (HEMTs) are examined. Optimization of the SiNx passivation and AlGaN barrier design of 150 nm gate HEMTs enhances the extrinsic (at Vds = 10 V) and intrinsic (at Vds = 15 V) transconductance from ≈0.47/0.65 to ≈0.62/1.1 S mm−1. Notably, an extrinsic gm of 0.70 S mm−1 at Vds = 5 V is achieved, setting a new benchmark for the extrinsic transconductance of AlGaN/GaN HEMTs designed for the K/Ka frequency range with a breakdown voltage exceeding 100 V.

Recovery of drain-induced threshold voltage shift by positive gate bias in GaN power HEMTs with p-GaN gate

We demonstrate that exposure to positive gate bias can favor a fast recovery of the threshold voltage variation induced by off-state stress, in p-GaN gate high electron mobility transistors. Two process splits were investigated, having different Schottky barriers at the metal/p-GaN junction. Results indicate that: (a) drain stress may result in significant threshold voltage increase; (b) devices with sufficiently high gate leakage current show an immediate recovery after gate turn-on, resulting in stable operation in actual applications. The contribution of leakage current is demonstrated, based on recovery experiments at different voltages and for the same rate of hole injection from the gate.

TCAD‐enabled machine learning framework for DC and RF performance evaluation of InGaAs sub‐channel DG‐HEMTs

AbstractThis research presents a machine learning (ML)‐based model that determines the DC and RF characteristics of InGaAs sub‐channel double gate high electron mobility transistors (DG‐HEMTs) to optimize the device structure. We employ technology computer‐aided design (TCAD) simulations to analyze the DC and RF performance of InGaAs sub‐channel DG‐HEMTs, generating a range of datasets by varying the material composition, layer width, and thickness of different layers in the device structure. We then train and optimize support vector regression (SVR) models using 5‐fold cross‐validation, varying the kernel function and degree parameters, and achieve better performance with the radial basis function (RBF) kernel. The simulated results indicate that the ML model predicts physical parameters more effectively than experimental analysis, offering a compact modeling solution that requires fewer computing resources than traditional methods.

Physical insight into the abnormal VTH instability of Schottky p-GaN HEMTs under high-frequency operation

In this Letter, we investigate the threshold voltage (VTH) instability of Schottky p-GaN gate high electron mobility transistors (SP-HEMTs) under high-frequency operation by a resistive-load hard switching method. The abnormal VTH instability is observed, which is different between fully and partially depleted SP-HEMTs (FD- and PD-HEMTs). Notably, for FD-HEMT, VTH shifts positively with effective stress time. However, the VTH instability in PD-HEMT is more complex. At low VGS (e.g., 3 V) and high VGS (e.g., 6 V), VTH shifts positively with stress time consistently. Nevertheless, at intermediate VGS levels (e.g., 4 and 5 V), VTH initially shifts positively and then negatively, displaying a non-monotonous variation. Furthermore, the frequency dependence of VTH is contingent upon VGS. At low VGS, VTH exhibits a negative shift with the increase in frequency. This trend inverses when VGS exceeds 4 V. And it should be noted that the extracted VTH under high-frequency operation is lower than their quasi-static values for both transistor types. This work depicts the physical process and mechanism of the abnormal VTH instability; different from the quasi-static case, hole accumulation effects will be enhanced due to the high dV/dt, which results in a lower VTH. The distinct VTH behaviors of FD- and PD-HEMTs are closely related to the trapping effects, as well as hole accumulation and insufficiency, within the two different p-GaN gate layers.

Normally-off GaON/p-GaN gate HEMTs with selective plasma oxidation: from structural characterization, performance improvement to physical mechanism

In this letter, a p-GaN gate high-electron-mobility transistor (HEMT) with a high threshold voltage and better gate reliability was demonstrated by using selective plasma oxidation (SPO) and an additional low-temperature annealing step before gate metal is evaporated. After the SPO, a gallium oxynitride (GaON) dielectric layer was formed on the surface of p-GaN under the gate metal, and was studied by x-ray photoelectron spectroscopy (XPS), secondary ion mass spectrometry, high-resolution transmission electron microscopy and energy dispersion spectroscopy. In addition, the fabricated metal/GaON/p-GaN gate HEMT exhibited a large threshold voltage (V TH) improvement from 1.46 V to 2.47 V. Furthermore, the forward gate breakdown voltage (V GS,BD) increased from 7.55 V to 11.10 V, and the maximum forward gate operating voltage (V GS-max) significantly improved from 5.0 V to 7.80 V for a ten-year lifetime with a 63.2% failure rate. Kelvin probe force microscopy reveals that the surface potential increased after SPO, and the shift of valence band maximum obtained by XPS spectra was 0.7 eV lower than that of the p-GaN, which further improves the Schottky barrier height at the gate metal/GaON interfaces to holes, thereby improving V TH and reducing I GS of the device. As a barrier layer, GaON suppressed the injection of carrier into the depletion region under a high electric field and enhanced the reliability of the gate.

Al-rich AlGaN high electron mobility transistor gate metallization study up to 600 °C in air

Al-rich AlGaN high electron mobility transistor gate metallization study up to 600 °C in air

Monolithic fully-controlled HEMT bidirectional power switch with merged Schottky barrier diodes and p-GaN gate transistors for ultra-low turn-on voltage and high threshold voltage

A monolithic fully-controlled high electron mobility transistor (HEMT) bidirectional power switch (FC-HEMT BPS) is studied and implemented for ultra-low turn-on voltage and high threshold voltage. The alternately embedded recess Schottky barrier diodes with p-GaN gate HEMTs in the common active region is a distinctive feature of the proposed device. The FC-HEMT BPS is a sophisticated device with two independent gate controls, capable of operating in four distinct modes. Its flexibility in managing current and voltage in the first and third quadrants makes it versatile for a range of applications in power electronics. The proposed device offers notable advantages over conventional counterparts, including reduced turn-on voltage V ON-D of ∼0.4 V in diode modes and the elimination of turn-on voltage V ON-B (i.e. 0 V) in bidirectional conduction mode. These features make it a promising solution for efficient power electronics applications.

Incorporation of total ionizing dose effects into a compact model for p-GaN gate high electron mobility transistors

Total ionizing dose (TID) characteristics of p-GaN gate high electron mobility transistors (HEMTs) under different bias conditions are explored in this work. Potential mechanism accounting for the TID response of p-GaN gate HEMTs is analyzed, based on which a TID effects model is developed. The TID effects model describes the relationship among threshold voltage of p-GaN gate HEMTs, total radiation dose, and electric field inside the p-GaN cap layer. Furthermore, an approach incorporating the TID effects model into Advanced Spice Model for HEMT (ASM-HEMT) is proposed, the reliability of which is validated by the well-fitted modeled results in comparison with the measured ones. This approach makes it possible to probe into the impact of TID effects on p-GaN gate HEMTs from the perspective of circuit level, which provides a basis for the follow-up GaN-based circuit design.

Challenges and advancements in p-GaN gate based high electron mobility transistors (HEMTs) on silicon substrates

This review highlights the challenges and advancements in p-GaN gate HEMTs on silicon substrates. It also discusses several attempts to enhance device performance and explores the future developments of p-GaN gate HEMT.

Review on Main Gate Characteristics of P-Type GaN Gate High-Electron-Mobility Transistors.

As wide bandgap semiconductors, gallium nitride (GaN) lateral high-electron-mobility transistors (HEMTs) possess high breakdown voltage, low resistance and high frequency performance. PGaN gate HEMTs are promising candidates for high-voltage, high-power applications due to the normally off operation and robust gate reliability. However, the threshold and gate-breakdown voltages are relatively low compared with Si-based and SiC-based power MOSFETs. The epitaxial layers and device structures were optimized to enhance the main characteristics of pGaN HEMTs. In this work, various methods to improve threshold and gate-breakdown voltages are presented, such as the top-layer optimization of the pGaN cap, hole-concentration enhancement, the low-work-function gate electrode, and the MIS-type pGaN gate. The discussion of the main gate characteristic enhancement of p-type GaN gate HEMTs would accelerate the development of GaN power electronics to some extent.

Novel T-Shaped Gate Structure of AlGaN/GaN HEMTs on Si for RF Application

Due to the high electron saturation velocity and breakdown electric field, GaN-based high electron mobility transistors (HEMTs) have been widely used in high frequency and power application, such as telecommunication, satellite communication, and radar system [1]. Since first demonstration of AlGaN/GaN HEMTs in 1993 [2], the RF performance of these device has continuously improved by the progress on epitaxy and device scaling technology [3].The current gain cut-off frequency (fT) and the maximum oscillation frequency (fmax) from the small-signal equivalent circuit of the HEMT are derived by the following equations [4].From these equations, it can be concluded that in order to achieve high frequency operation, HEMTs should be designed with a T-shaped gate structure that simultaneously achieves low gate resistance (Rg) and low parasitic capacitance (Cgs and Cgd). However, there are complex fabrication processes to form the T-shaped gate. Typically, the T-shaped gate structure is implemented through electron beam lithography process using a tri-layer resist such as PMMA/PMGI/PMMA, which requires multiple exposures or developments. Multiple exposures can cause overlay errors that can significantly affect the T-shaped gate with smaller gate lengths [5]. Also, it is difficult to obtain an undercut structure that enables a good lift-off and guarantees a high yield due to the need for precise dose control. In addition, since the T-shaped gate has an unstable structure in which a narrow foot supports the weight of a wide head, the gate may collapse during a subsequent process.In this work, we fabricated a novel T-shaped gate using the negative e-beam resist HSQ, which offers a simple T-shaped gate fabrication process. The HSQ that was exposed to e-beam is located underneath the gate head and on both sides of the gate foot in our novel T-shaped gate design, providing a robust structure. The HSQ-assisted gate HEMTs exhibit comparable DC/RF performance compared to conventional T-shaped gate HEMTs. Acknowledgement This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MIST) (No. NRF-2021M3C13097672).

Improved frequency performance in AlGaN/GaN HEMTs on Si using hydrogen silsesquioxane-assisted gate

AlGaN/GaN HEMTs have been regarded as the most promising option for achieving high-frequency power amplifier in various applications, including wireless communication, aerospace, and radar systems. To enable their use at even higher frequency, we conducted a study to enhance the frequency characteristics of AlGaN/GaN high electron mobility transistors (HEMTs) on a silicon substrate. By employing a hydrogen silsesquioxane (HSQ)-assisted gate, AlGaN/GaN HEMT with an LG of 0.17 μm and LSD of 5 μm exhibited a VTH of 4.5 V, ID.max of 885 mA/mm, and gm.max of 253 mS/mm. The planar-gate without HSQ shows VTH of 4.4 V, ID.max of 876 mA/mm, and gm.max of 258 mS/mm. The DC characteristics are comparable to those observed in planar-gate HEMT with a conventional gate structure. Though the DC characteristics of both devices are similar, the HSQ-assisted gate HEMT exhibits a higher fT/fmax of 55/89 GHz, whereas the planar-gate HEMT yields an fT/fmax of 38/64 GHz. The 32% reduction in the total extrinsic gate capacitance (Cgs + Cgd) is the major contributor to the improved frequency performance of the HSQ-assisted gate AlGaN/GaN HEMT. The adoption of HSQ-assisted gate AlGaN/GaN HEMTs presents itself as a highly advantageous choice for achieving higher-frequency operations. © 2023 Elsevier Inc. All rights reserved.

High-performance normally off AlGaN/GaN high electron mobility transistor with p-type h-BN cap layer

Normally off AlGaN/GaN high electron mobility transistors (HEMTs) with p-type gates are attracting increasing attention due to their high safety and low power loss in the field of power switching. In this work, to solve the Mg difficult activating problem of the conventional p-GaN gate AlGaN/GaN HEMTs, we propose an advanced design for the normally off AlGaN/GaN HEMT with a p-type hexagonal boron nitride (h-BN) gate cap layer to effectively manipulate the channel transport of the device. The simulation results demonstrate that the p-hBN gate cap HEMTs yield superior performance over conventional p-GaN gate HEMTs in terms of output current and breakdown voltage, which can be attributed to the deeper potential well formation at the AlGaN/GaN interface and more accumulation of holes located at the p-hBN/AlGaN interface. Moreover, we investigate the effect of bandgap variation on device performance, taking into account that the exact bandgap of h-BN remains under debate. Herein, valuable insights into h-BN cap-gate E-mode AlGaN/GaN HEMT devices are provided, which could serve as a useful reference for the future development of robust III-nitride material power electronic devices.

Breakdown enhancement and hot electrons mitigation for p-GaN gate HEMTs by electric field modulation

In this article, an enhancement mode (E-mode) p-GaN gate AlGaN/GaN high electron mobility transistor (HEMT) with the novel strain technology (NST) has been proposed. The NST consists of GaN/AlGaN/GaN and AlN/AlGaN/GaN heterojunctions laterally from the gate to drain side. By utilizing the different polarization effect of these two heterojunctions, it laterally forms different density of two-dimensional electron gas (2DEG). Accordingly, it decreases the electric field around the gate and introduces an extra electric field peak far away from the gate edge to improve the breakdown voltage (BV) effectively. The experimental BV of the proposed NST-HEMT is increased by 52 % to 1185 V from 780 V of the conventional HEMT. Meanwhile, the output current of NST-HEMT is almost consistent with the conventional HEMT. Moreover, the NST-HEMT realizes better hot electrons mitigation than conventional HMET, and its Vth and Ron degradations are only 1.38 % and 10.72 % after 8 h stress time.

Design and performance analysis of front and back Pi 6 nm gate with high K dielectric passivated high electron mobility transistor

Advanced high electron mobility transistor (HEMT) with dual front gate, back gate with silicon nitride/aluminum oxide (Si3N4/Al2O3) as passivation layer, has been designed. The dependency on DC characteristics and radio frequency characteristics due to GaN cap layers, multi gate (FG and BG), and high K dielectric material is established. Further compared single gate (SG) passivated HEMT, double gate (DG) passivated HEMT, double gate triple (DGT) tooth passivated HEMT, high K dielectric front Pi gate (FG) and back Pi gate (BG) HEMT. It is observed that there is an increased drain current (Ion) of 5.92 (A/mm), low leakage current (Ioff) 5.54E-13 (A) of transconductance (Gm) of 3.71 (S/mm), drain conductance (Gd) of 1.769 (S/mm), Cutoff frequency (fT) of 743 GHz maximum oscillation frequency (Fmax) 765 GHz, minimum threshold voltage (V<sub>th</sub>) of -4.5 V, on resistance (Ron) of 0.40 (Ohms) at V<sub>gs</sub>=0 V. These outstanding characteristics and transistor structure of proposed HEMT and materials involved to apply for upcoming generation high-speed GHz frequency applications.

Modeling of Enhancement Mode HEMT with Π-Gate Optimization for High Power Applications

This paper presents technology computer-aided design (TCAD) modeling of an enhancement-mode aluminum gallium nitride (AlGaN)/gallium nitride (GaN) high electron mobility transistor (HEMT) with extensive π-gate optimization for high-power and radio frequency (RF) applications. Effects of the gate voltages on threshold (Vth), transconductance (gm), breakdown voltage (VBR), cutoff frequency (fT), maximum frequency of oscillation (fmax) and minimum noise figure (NFmin) are systematically investigated with different gate structures (π–Shaped p-GaN MISHEMT, π–Shaped p-GaN HEMT, π–Gate HEMT). A comparative study demonstrates that π–Gate with additional p-GaN and insulating layer makes the device effectively operate in the enhancement mode having a threshold voltage (Vth) = 1.72 V with a breakdown voltage (VBR) = 341 V, exhibiting better gate control with maximum transconductance (gm,max) of 0.321 S/mm. In addition, the proposed device architecture with an optimized gate structure maintains a balance between a positive device threshold and a high breakdown voltage and achieves a better noise immunity with the minimum noise figure of 0.64 dB while operating at 10 GHz with a cutoff frequency (fT) of 33.4 GHz, and a maximum stable operating frequency (fmax) of 82.3 GHz. Moreover, the device achieved an outstanding Vth, gm,max, VBR, fT, fmax and NFmin making it suitable for high-power, high-speed electronics, and low-noise amplifiers.

Evaluation of Trapping Behaviors in Forward Biased Schottky-Type p-GaN Gate HEMTs

In this work, we investigated the trapping behaviors in the Schottky-type p-GaN gate high-electron-mobility transistors (HEMTs) under positive gate bias using the current-transient method. By excluding the trapping effect introduced by the measurement voltages, the actual recovery curves of drain transient current under different gate filling voltages and temperatures were extracted. The impacts of electron trapping, hole injection, and electron–hole recombination on the threshold voltage instability can be effectively distinguished according to the results of drain current variations under different gate stresses. In addition, the dynamic drain leakage current was monitored to confirm the electron–hole recombination and optical pumping of trapped electrons. The properties of three electron traps can be obtained based on the time constant spectrum (TCS), and a database of the gate-trapping behaviors in the GaN-based devices was constructed. The combined results may provide a basis for a better understanding of the threshold voltage instability under positive gate stress in the p-GaN gate HEMTs.

Threshold Voltage Measurement Protocol “Triple Sense” Applied to GaN HEMTs

The threshold voltage instability in p-GaN gate high electron mobility transistors (HEMTs) has been brought into evidence in recent years. It can lead to reliability issues in switching applications, and it can be followed by other degradation mechanisms. In this paper, a Vth measurement protocol established for SiC MOSFETs is applied to GaN HEMTs: the triple sense protocol, which uses voltage bias to precondition the transistor gate. It has been experimentally verified that the proposed protocol increased the stability of the Vth measurement, even for measurements following degrading voltage bias stress on both drain and gate.

Revealing the Mechanism of the Bias Temperature Instability Effect of p-GaN Gate HEMTs by Time-Dependent Gate Breakdown Stress and Fast Sweeping Characterization.

The bias temperature instability (BTI) effect of p-GaN gate high-electron-mobility transistors (HEMTs) is a serious problem for reliability. To uncover the essential cause of this effect, in this paper, we precisely monitored the shifting process of the threshold voltage (VTH) of HEMTs under BTI stress by fast sweeping characterizations. The HEMTs without time-dependent gate breakdown (TDGB) stress featured a high VTH shift of 0.62 V. In contrast, the HEMT that underwent 424 s of TDGB stress clearly saw a limited VTH shift of 0.16 V. The mechanism is that the TDGB stress can induce a Schottky barrier lowering effect on the metal/p-GaN junction, thus boosting the hole injection from the gate metal to the p-GaN layer. This hole injection eventually improves the VTH stability by replenishing the holes lost under BTI stress. It is the first time that we experimentally proved that the BTI effect of p-GaN gate HEMTs was directly dominated by the gate Schottky barrier that impeded the hole supply to the p-GaN layer.

Investigation of the Gate Degradation Induced by Forward Gate Voltage Stress in p-GaN Gate High Electron Mobility Transistors.

In this work, we investigated the degradation of the p-GaN gate stack induced by the forward gate voltage stress in normally off AlGaN/GaN high electron mobility transistors (HEMTs) with Schottky-type p-GaN gate. The gate stack degradations of p-GaN gate HEMTs were investigated by performing the gate step voltage stress and the gate constant voltage stress measurements. In the gate step voltage stress test, the positive and negative shifts of threshold voltage (VTH) depended on the range of the gate stress voltage (VG.stress) at room temperature. However, the positive shift of VTH in the small gate stress voltage was not observed at 75 and 100 °C and the negative shift of VTH was started from a lower gate voltage at a high temperature compared to room temperature. In the gate constant voltage stress test, the gate leakage current increased with three steps in the off-state current characteristics as the degradation progressed. To investigate the detailed breakdown mechanism, we measured the two terminal currents (IGD and IGS) before and after the stress test. The difference between the gate-source current and the gate-drain current in the reverse gate bias indicated that the increase of the leakage current was attributed to the degradation between the gate and the source while the drain side was not affected.