High Electron Mobility Transistor Design Research Articles

Design and optimization of high electron mobility transistor with high-k dielectric material integration

We have developed and simulated a high electron mobility transistor (HEMT) operating in the 5 nm regime. This HEMT uses hafnium oxide (HfO2), a high-k dielectric material, to create an undoped region (UR) beneath the gate. While the gate and undoped regions share equal thickness, the channel length differs. This innovative undoped under the gate dielectric HEMT design mitigates the maximum electric field (V) within the channel area, leading to a significant increase in drain current. The utilization of a high-k dielectric in the HEMT structure results in a saturated Ion current that is 60% higher compared to conventional structures. Specifically, we use an AlGaN/GaN/SiC-based HEMT with an intrinsic section below the gate, using HfO2 as the high-k dielectric substantial, for applications requiring high power and high-frequency power amplifiers. Compare this advanced HEMT design to conventional HEMTs and you will see improved conductivity, a greater drain current (Id), a 54% increase in transconductance (Gm), and a lower on-resistance (Ron). Additionally, advancements in the electric field in the Y direction are seen. This HEMT structure exhibits superior performance compared to alternative materials analyzed. The integration of AlGaN/GaN materials in HEMTs opens up extensive opportunities in the realms of radio frequency very large-scale integration (VLSI) and power electronics.

Third generation semiconductor device research: Optimizing CMOS and HEMT designs

The third-generation semiconductor device known as High Electron Mobility Transistors (HEMT) has found extensive applications in high-frequency and high-speed electronic systems. Its widespread usage in critical technologies such as radio telescopes, satellite broadcast receivers, and cellular base stations has established HEMT as a foundational technology underpinning our information and communication society. This paper provides an in-depth exploration of these semiconductor advancements. Firstly, the paper utilizes the CMOS inverter as a representative example to elucidate the fundamental structure of Complementary Metal-Oxide-Semiconductor (CMOS) technology. Additionally, it employs Gallium Arsenide (GaAs) HEMT as an illustrative instance to expound upon the architecture of HEMT devices. Furthermore, the paper delves into the optimization of CMOS technology, focusing on topics such as Multi-Threshold CMOS and the impact of the Width/Length (W/L) ratio. These discussions shed light on ways to enhance the performance of CMOS-based components. Additionally, the paper explores strategies to optimize HEMT devices, including the introduction of carbon doping and the application of the Grey-Wolf optimization technique. These approaches are critical in achieving higher efficiency and performance in HEMT-based applications.

(Invited) Heterogeneous Integration of Ultrawide Bandgap III-Nitrides and Diamond

Industry demands for power switching, amplification and photonic applications are continually pushing the limits of semiconductor device technologies leading to increasing applied voltages and, thus, higher electric fields while simultaneously requiring reduction in the size, weight and power consumption. In addition, recent heightened interest in higher temperature (and other extreme environment) applications, while simultaneously maintaining high-voltage and high-power performance, has inexorably led to ultrawide bandgap (UWBG) semiconductor materials. This interest in UWBG materials stems from superior properties that include high material hardness, breakdown strength to withstand large electric fields and mitigation of power dissipation during device switching, deliver high current density while operating at higher junction and ambient temperature. Among these materials are boron nitride in its hexagonal and cubic phases, gallium oxide, diamond, and aluminum gallium nitride. The versatile alloys of wurtzite AlxGa1-xN have long been demonstrated across the full composition range. The variation in Eg with AlGaN composition, along with select WBG and UWBG materials, is shown in Figure 1 versus (in-plane for non-cubic) lattice constant.Premier WBG materials to date for electronics and photonics are SiC (Eg = 3.3 eV) and GaN (Eg = 3.4 eV). The latter has been successfully applied to high-power transistors and near ultraviolet photonics. In both electronics and photonics applications, the polarization fields of the wurtzite crystal structure, generally grown along (0001) direction, produce design challenges. In photonics, for example, the fields and band alignment couple to spatially separate electrically injected electrons and holes to reduce wavefunction overlap in quantum wells. In electronics, the internal fields have contributed to difficulties in the design of logic and bipolar transistor devices based on these materials. Despite this, the inherent polarization field and band offsets were successfully employed in the design of high electron-mobility transistors (HEMTs). The inherent AlGaN/GaN HEMT band offset produces a high electron concentration at the interface that spontaneously forms a two-dimensional electron gas (2DEG). Because charge flow in these devices is restricted to the 2DEG, current crowding results in intense self-heating. The local heating decreases electrical conductivity to produce a runaway scenario for elevating the Joule heating. Dissipating this heat, therefore, is the principal limiting factor in operating at power higher than 40 W/mm.The various temperature dependences of semiconductor device parameters are the principal drivers in the operation of semiconductor devices. The physics has inextricably led to UWBGs for future high temperature applications, > 300 °C, due to their lower intrinsic carrier density and thus the effects of leakage are orders of magnitudes less than Si-based devices. Furthermore, AlGaN and diamond offer superior high temperature mechanical stability due to their structural hardness and chemical inertness. Thermal management is essential for achieving higher power densities. Diamond is highly attractive for many applications due to its high hardness, transparency, chemical inertness, promising semiconductor properties, and its high thermal conductivity (κ) to 2500 W/m·K in natural material. Factors related to the consequences of self-heating in devices have motivated extensive research to improve the properties of diamond and produce better approaches to determine the thermal properties. Laboratory-grown diamond films exhibit significantly poorer κ than natural diamond and, when integrated with other electronic materials, a low thermal boundary conductance (TBC in W/m2·K) that inhibits heat transfer between materials. The former originates from the ubiquitous polycrystalline nature of chemical vapor deposition (CVD) diamond and the presence of non-diamond carbon (NDC) in the layer. The low TBC stems from fundamental barriers to phonon propagation between two materials and from practical issues of poor diamond quality in the initial growth regime. Continued research is needed to improve κ in the polycrystalline diamond and mitigate the negative impact of the initial diamond layer on TBC.The current status of hetero-integration of UWBG AlGaN and diamond will be reviewed. Particular emphasis is given to high Al content AlGaN for near-bandgap matching with diamond. Patterned diamond grown using hot-filament CVD to realize unique three-dimensional lateral device structures in a self-aligned, as-grown fabrication process is employed. Engineering the AlGaN-diamond bandgap alignment is noteworthy at the nonpolar AlGaN – diamond interface including diamond surface terminations that produce either negative or positive electron affinity. The review will focus on improvements in material properties, especially the interfaces, that are critical to both charge and heat transport for UWBG device structures. Figure 1

Design and Simulation of Enhancement-Mode Vertical Superjunction GaN HEMT with Improved Ron and Cut-Off Frequency

GaN-based vertical superjunction high electron mobility transistors (HEMT) are recent avenues for power transistors. In this work, an enhancement mode vertical superjunction GaN-HEMT with gradient doping (GDP-SJ HEMT) is proposed and analyzed. In the GDP-SJ HEMT, the n-pillar doping concentration increases in a gradient manner from top to bottom. Whereas the concentration of the p-pillar is uniform and equivalent to the doping of the middle of the n-pillar. By optimizing the device design and doping profile, the specific-on resistance (Ron,sp) of the device has been reduced from 5.0 mΩ-cm2 to 3.79 mΩ-cm2. To the best of our knowledge, the frequency performance of vertical SJ HEMT has not been documented in the literature. As a result, we also performed a frequency study. The cut-off frequency (f T) of the proposed device is 78 MHz and the maximum frequency (f MAX) is 71 MHz. The device optimization increases the f T by 89% i.e. 148 MHz and f MAX by 67% i.e. 119 MHz.

Crack-Free High-Composition (>35%) Thick-Barrier (>30 nm) AlGaN/AlN/GaN High-Electron-Mobility Transistor on Sapphire with Low Sheet Resistance (<250 Ω/□)

In this article, a high-composition (>35%) thick-barrier (>30 nm) AlGaN/AlN/GaN high-electron-mobility transistor (HEMT) structure grown on a sapphire substrate with ultra-low sheet resistivity (<250 Ω/□) is reported. The optimization of growth conditions, such as reduced deposition rate, and the thickness optimization of different epitaxial layers allowed us to deposit a crack-free high-composition and thick AlGaN barrier layer HEMT structure. A significantly high two-dimensional electron gas (2DEG) density of 1.46 × 1013 cm−2 with a room-temperature mobility of 1710 cm2/V·s was obtained via Hall measurement using the Van der Pauw method. These state-of-the-art results show great potential for high-power Ga-polar HEMT design on sapphire substrates.

Theoretical Prediction of Mobility Improvement in GaN-Based HEMTs at High Carrier Densities

In this article, we use a semiclassical low-field mobility modeling framework, which includes all relevant scattering mechanisms, to examine the dependence of electron mobility on 2-D electron gas (2DEG) density in previously characterized high Al-content AlGaN/gallium nitride (GaN) high electron mobility transistors (HEMTs) with and without an AlN spacer layer. Polar optical phonon (POP) scattering has previously been identified as the dominant scattering mechanism in GaN-based HEMTs at room temperature, so the analysis of POP scattering rates is of particular importance. We find that the POP-limited mobility in both structures decreases with increasing 2DEG density up to a critical density of around <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${10}^{{13}}$ </tex-math></inline-formula> cm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{-{2}}$ </tex-math></inline-formula> , above which we observe a significant improvement of up to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${46}\%$ </tex-math></inline-formula> , contrary to the behavior typically reported for GaN HEMT structures. The POP-limited mobility increase is explained by the interplay of ground-state energy and quasi-Fermi energy within the channel, by which intrasubband POP emission within the ground state is suppressed at high 2DEG densities. This provides a universal guideline for the design and operation of GaN-based HEMTs to achieve a minimum ON-resistance in switching applications at room temperature and above.

Physical design guidelines to minimize area-specific ON-resistance for rated ON-current and breakdown voltage of GaN power HEMTs

In this article, we report on the development of an analytical model to estimate area-specific ON-state resistance (R ds,on) of GaN-based power high electron mobility transistor (HEMT) using rated device specifications—ON-state drain current (I ON) and maximum operating drain-to-source voltage (V DSO)—as input parameters. The rated I ON and V DSO are considered as fractions k and S, of the maximum possible drain current (I DS,max) and breakdown voltage (V BR), respectively, deliverable by the power device. The developed model is utilized to obtain the optimal physical design space parameters for a comb-like power HEMT design. Due consideration has been given to the trade-off between R ds,on and area-specific R ds,on of the transistor, device processing limitations for all the physical device parameters. The developed model has been validated with experimental results of prior literature. Our calculations impose a lower-bound for the best possible R ds,on as well as the area-specific on-resistance product (R ds,on AA) that can be obtained for a given starting channel sheet resistance in the comb architecture for a desired I ON − V DSO rating.

Compositionally Graded III-N HEMTs for Improved Linearity: A Simulation Study

As is well known, a roadblock to realizing the full potential of GaN high-electron mobility transistors (HEMTs) for power amplifier applications is the peaked nature of the transconductance and the resulting power-gain roll-off exhibited by these devices. Motivated by promising work on compositionally graded HEMT designs, in this paper we explore this design solution using the numerical device simulation. Among other things, we examine the consequences of saturation velocity, grading profile, alloy scattering, and device scaling. In addition, lumped element modeling of the large-signal behavior is carried out to assess the power amplifier performance. We also compare the graded approach with another known method of linearity improvement in which the source resistance is reduced. In general, we find much to recommend in the graded-channel approach, especially for gate lengths greater than about 100 nm.

Polarization-mediated Debye-screening of surface potential fluctuations in dual-channel AlN/GaN high electron mobility transistors

A dual-channel AlN/GaN/AlN/GaN high electron mobility transistor (HEMT) architecture is proposed, simulated, and demonstrated that suppresses gate lag due to surface-originated trapped charge. Dual two-dimensional electron gas (2DEG) channels are utilized such that the top 2DEG serves as an equipotential that screens potential fluctuations resulting from surface trapped charge. The bottom channel serves as the transistor's modulated channel. Two device modeling approaches have been performed as a means to guide the device design and to elucidate the relationship between the design and performance metrics. The modeling efforts include a self-consistent Poisson-Schrodinger solution for electrostatic simulation as well as hydrodynamic three-dimensional device modeling for three-dimensional electrostatics, steady-state, and transient simulations. Experimental results validated the HEMT design whereby homo-epitaxial growth on free-standing GaN substrates and fabrication of the same-wafer dual-channel and recessed-gate AlN/GaN HEMTs have been demonstrated. Notable pulsed-gate performance has been achieved by the fabricated HEMTs through a gate lag ratio of 0.86 with minimal drain current collapse while maintaining high levels of dc and rf performance.

Analytical Model for Power Switching GaN-Based HEMT Design

The GaN high-electron mobility transistor (HEMT) structure has been widely investigated, particularly for radio-frequency applications. This structure is suitable for high-frequency switching applications in power electronics because of the high breakdown field of GaN and the high mobility of the channel. In this paper, a physical model for predicting the power-switching operation of GaN-based HEMTs as a function of material and device parameters is proposed. Analytical equations for total losses and power dissipation density are derived and discussed both qualitatively and quantitatively.

Turn-on voltage engineering and enhancement mode operation of AlGaN/GaN high electron mobility transistor using multiple heterointerfaces

A novel device design for enhancement mode operation of III-nitride high electron mobility transistor (HEMT) structure has been proposed and demonstrated. The proposed HEMT device structure consists of a multi-heterojunction (SiO 2/Al x Ga 1− x N/GaN/Al y Ga 1− y N) design in contrast to a single AlGaN/GaN heterojunction commonly used in conventional III-nitride HEMT designs. Normally OFF operation of the proposed HEMT design is expected to take place for thicker GaN and the top Al x Ga 1− x N layers than previously allowed. The effects of design parameters on the value of the device turn ON voltage have been studied extensively using simulations. Various device structures have been developed based on the simulations results and epitaxially grown by MOCVD. I– V measurements support the effects of design parameters on the turn ON voltage predicted by the simulations and have confirmed the enhancement mode operation.

Advanced modelling of GaN/AlGaN HEMT devices with field plate

AbstractIn this paper we carry out detailed study and numerical modelling of the operation of the GaN/AlGaN High Electron Mobility Transistor (HEMT) with Field Plate (FP) optimisation. The FP has the effect of smoothing the potential gradient along the HEMT channel near the gate edge on the drain side, resulting in the enhancement of the breakdown voltage. We show that the main effect of the FP is a substantial decrease in the longitudinal component of the field EL, along with little variation of the normal component ET. In addition to the main peak of the EL field at the gate edge, there is a secondary peak under the FP edge which grows rapidly with drain bias and eventually surpasses the first. The appearance of the second peak should be taken into account in optimising of the HEMT design. The I‐V characteristics of the FP‐gated device remain practically the same as those of a device without a FP. (© 2007 WILEY‐VCH Verlag GmbH &amp; Co. KGaA, Weinheim)

Design and characterisation of high electron mobility transistors for use in a monolithic GaAs X-ray imaging sensor

A new design of monolithic GaAs pixel detector is proposed for medical and synchrotron applications. In this device a semi-insulating GaAs wafer will be used as both the detector element and the substrate for the integrated charge readout matrix. The charge readout matrix consists of High Electron Mobility Transistors (HEMTs), which are grown epitaxially onto the GaAs substrate. Experimental characterisation of HEMTs has been carried out and their suitability for the proposed imaging device is assessed. Temperature measurements on initial devices showed the threshold voltage to be stable from room temperature down to −15°C. HEMT designs with lower leakage current that operate in enhancement mode have been fabricated and modelled using the Silvaco simulation package. These optimised devices have been fabricated using a gate recess, and exhibit enhancement mode operation and significantly reduced gate leakage currents.

Aδ-doped In0.24Ga0.76As/GaAs pseudomorphic high electron mobility transistor using a graded superlattice spacer

A new δ -doped In0.24Ga0.76As/GaAs pseudomorphic high electron mobility transistor (HEMT) using a graded superlattice spacer grown by molecular beam epitaxy (MBE) has been successfully fabricated and investigated. The present device structure demonstrated a more than 40% enhancement of electron mobility and 20% higher product value of electron mobility and two-dimensional electron gas (2DEG) concentration than those of the conventional HEMT with single undoped spacer under the same growth specifications. Superior device characteristics were achieved by employing the thickness-graded superlattice spacer to accommodate the lattice-mismatch-induced strain and to improve the interfacial quality. For a gate length of 1 μ m, the maximum drain-to-source saturation current density and extrinsic transconductance of the present HEMT design are 165 mA mm−1and 107 mS mm−1, respectively, at room temperature.

Automatically aligned electron beam lithography on the nanometre scale

A scanning electron microscope (SEM) has been modified to enable it to be used for electron beam lithography. This involved modifications to the electron optics and sample stage of the SEM, as well as adding an image correlation system and pattern generator to provide the alignment and lithography functions. The instrument has been used for direct-write electron beam lithography to fabricate devices with dimensions on the nanometre scale. The standard SEM stage has been motorized and is used to move to each device. The location of each device is found by using a hierarchical image correlation technique and electron beam deflection system to achieve a device alignment accuracy of 80 nm. The main application is to write the gate electrodes in gallium arsenide high electron mobility transistors (HEMTs). A variety of HEMT designs have been written with exposed linewidths of 130 nm. The instrument has also been used to write large arrays of closely spaced electrodes as part of a semiconductor detector. Each detector contains 80 electrodes which are 160 nm wide, 60 μm long and separated by gaps of 370 nm. The full electron microscope functionality of the instrument is maintained to enable the results of the electron beam lithography to be analysed.

Application of photoreflectance spectroscopy to the study of interface roughness in InGaAs/InAlAs heterointerfaces

The achievement of high electrical performance InAlAs/InGaAs high-electron-mobility transistors (HEMTs) grown by metalorganic chemical vapor deposition, requires the growth of a good quality InGaAs channel/InAlAs spacer interface, in order to ensure good transport properties in the two-dimensional electron gas channel. In this article, the interface quality is evaluated as a function of growth interruption time, using photoreflectance spectroscopy. The experimental and theoretical approach used for this purpose is described. Layers representative of HEMT designs, namely 250 Å InGaAs single quantum wells between InAlAs layers were used for characterization. The interface roughness is estimated from the broadening of the high order quantum confined transitions. The results obtained suggest that the higher the growth interruption time, the smaller the interface roughness. Electrical characterization results indicate good agreement with the trends observed by photoreflectance.

Large-signal time-domain simulation of HEMT mixers

A large-signal HEMT (high electron mobility transistor) model and a time-domain nonlinear circuit analysis program have been developed. A systematic method to simulate HEMT mixers and design them for maximum conversion gain is presented. The transconductance-compression effect reduced the mixer's conversion gain at high frequencies. Simulation results from mixers designed to operate at 10, 20, and 40 GHz show that a reduction in parasitic conduction in the AlGaAs layer significantly increases the conversion gain.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>