High Efficiency CMOS Power Amplifier Research Articles

A Study and Analysis of High Efficiency CMOS Power Amplifier for IoT Applications

This paper presents a study and analysis of high efficiency CMOS power amplifier (PA) for Internet of Thing (IoT) application. The studied mainly focused on the topology employed in designing high efficiency PA in gigahertz range frequencies. This study covers the basic class-E PA and the topologies in designing class-E PA such as single-stage, two-stage, multistage and differential. The circuits structure and the performances of class-E PA is discussed. The analysis is focusing on the efficiency of the proposed PA. The latest CMOS PAs developments have been studied and a summarization of the performance specification for different topologies are elaborated.

Bayesian Neural Networks for Identification and Classification of Radio Frequency Transmitters Using Power Amplifiers’ Nonlinearity Signatures

The edge devices in an emerging Internet-of-Things (IoT) environment require comprehensive security measures that are within the power budget for ubiquitous computing. In this paper, a transmitter identification scheme consisting of a lightweight Bayesian neural network (BNN)-based classifier using raw time-domain data is presented. Evaluation is performed with data obtained in schematic-level simulation of high-efficiency CMOS power amplifier designs using a 65 nm process design kit (PDK). The Bayesian neural networks achieve 89.5% accuracy on the task of classifying six transmitters. Moreover, the BNN classifier is implemented on field-programmable gate array (FPGA) with parallel pseudo-Gaussian random number generators to achieve a throughput of more than 340,000 classifications per second, with average energy consumption for each classification task of 0.548 μJ. This low-power system enables comprehensive security for energy-constrained IoT devices and sensors.

2차 고조파 정합 네트워크를 포함하는 저손실 PCB 발룬을 이용한 고효율 CMOS 전력증폭기

2차 고조파 정합 네트워크를 포함하는 저손실 PCB 발룬을 이용한 고효율 CMOS 전력증폭기

A 2.5-GHz 1-V High Efficiency CMOS Power Amplifier IC with a Dual-Switching Transistor and Third Harmonic Tuning Technique

This paper presents a 2.5-GHz low-voltage, high-efficiency CMOS power amplifier (PA) IC in 0.18-µm CMOS technology. The combination of a dual-switching transistor (DST) and a third harmonic tuning technique is proposed. The DST effectively improves the gain at the saturation power region when the additional gain extension of the secondary switching transistor compensates for the gain compression of the primary one. To achieve high-efficiency performance, the third harmonic tuning circuit is connected in parallel to the output load. Therefore, the flattened drain current and voltage waveforms are generated, which in turn reduce the overlapping and the dc power consumption significantly. In addition, a 0.5-V back-gate voltage is applied to the primary switching transistor to realize the low-voltage operation. At 1 V of supply voltage, the proposed PA has achieved a power added efficiency (PAE) of 34.5% and a saturated output power of 10.1 dBm.

Envelope tracking CMOS power amplifier with high-speed CMOS envelope amplifier for mobile handsets

A high-efficiency CMOS power amplifier (PA) based on envelope tracking (ET) has been reported for a wideband code division multiple access (W-CDMA) and long term evolution (LTE) application. By adopting a high-speed CMOS envelope amplifier with current direction sensing, a 5% improvement in total power-added efficiency (PAE) and a 11 dB decrease in adjacent channel leakage ratio (ACLR) are achieved with a W-CDMA signal. Moreover, the proposed PA achieves a PAE of 25.4% for a 10 MHz LTE signal at an output power (Pout) of 25.6 dBm and a gain of 24 dB.

High gain and high efficiency CMOS power amplifier using multiple design techniques

A 60 GHz power amplifier (PA) using standard 90 nm CMOS technology is presented. This PA has power gain greater than 30 dB and 18.3% peak power added efficiency (PAE) under 2 V supply voltage. The parallel arrayed cascode power cells, which have a small number of fingers, are combined by the delay line to produce high gain and high PAE. Common gate inductors are inserted as gain booster circuits. A diode lineariser (DL) is adopted for increasing PAE and output P1dB (OP1dB). The measured saturation power is 13.2 dBm with its 11.5 dBm OP1dB. The measure power gain is above 25 dB over the whole frequency range (56–65 GHz). Due to the DL, the measured PAE exceeds 14% at the OP1dB power. This is believed to be the first CMOS PA having such high power gain and PAE.

A Compact High-Efficiency CMOS Power Amplifier With Built-in Linearizer

In this letter, a compact high-efficiency CMOS power amplifier (PA) with built-in linearizer that works at 2.4 GHz using TSMC 0.18 mum technology for digital wireless communications applications is presented. The cascode configuration is utilized to overcome the low break-down voltage problem and the hot-carrier effects for high power operations of CMOS devices. The linearizer design reduces the AM-AM quantities to extend the P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dB</sub> point while the AM-PM distortions are improved as well. The final designed PA exhibits P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dB</sub> of 20.6 dBm and 24.6% power-added-efficiency (PAE) with 35 dBm output-intercept-point in the third order (OIP3). The saturated output power is 22 dBm with 30% in PAE, while the chip size is less than 1 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

High efficiency CMOS power amplifier for 3 to 5 GHz ultra-wideband (UWB) application

A two-stage 0.18 mum CMOS power amplifier (PA) for ultra-wideband (UWB) 3 to 5 GHz using common source inductive degeneration is presented in this paper. Onwafer measurement shows an average power gain of 15.2 dB with gain flatness of 0.6 dB and an input 1 dB compression (P1dB) above - 6.1 dBm from 3 to 5 GHz while consuming 25 mW from a 1.8 V supply. Load-pull measurement also shows a power added efficiency (PAE) of 34% at 4 GHz with 50 Omega load impedance. Results obtained in this work could be used as a reference design for immediate PA implementation in commercial mobile or portable UWB transmitter or signal generator.