Abstract

This paper presents a 2.5-GHz low-voltage, high-efficiency CMOS power amplifier (PA) IC in 0.18-µm CMOS technology. The combination of a dual-switching transistor (DST) and a third harmonic tuning technique is proposed. The DST effectively improves the gain at the saturation power region when the additional gain extension of the secondary switching transistor compensates for the gain compression of the primary one. To achieve high-efficiency performance, the third harmonic tuning circuit is connected in parallel to the output load. Therefore, the flattened drain current and voltage waveforms are generated, which in turn reduce the overlapping and the dc power consumption significantly. In addition, a 0.5-V back-gate voltage is applied to the primary switching transistor to realize the low-voltage operation. At 1 V of supply voltage, the proposed PA has achieved a power added efficiency (PAE) of 34.5% and a saturated output power of 10.1 dBm.

Highlights

  • For modern communication systems, such as short-range wireless applications, a high-efficiency power amplifier plays an important role in maintaining the battery life

  • Efficiency and supply voltage represent a trade-off in switching-mode power amplifiers (PAs)

  • power added efficiency (PAE) is the ratio of the produced signal power and the dc power consumption

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Summary

Introduction

For modern communication systems, such as short-range wireless applications, a high-efficiency power amplifier plays an important role in maintaining the battery life. Several techniques have been proposed for improving efficiency at low supply voltages [6,7,8,9,10,11]. Large combiners lead to high insertion losses and enlarge the chip size Another approach to increase the efficiency of a low supply voltage PA is an injection-locking technique [10,11]. A high-efficiency CMOS PA IC operating at a low supply voltage proposed using combination with a third harmonic tuning technique [17]. PAfor topology was employed as A a detailed theoretical and circuit analysis was performed, and the optimum circuit parameters were basic structure, and 0.5-V positive, back-gate voltage was injected for low-voltage operation.

Dual-Switching Transistor
Switching Waveforms
Simulated
Back-Gate
Circuit
V was applied
Simulation Results
The proposed
Photograph
13. Measurement
16. Because
Conclusions
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