High Efficiency Charge Pump Research Articles

Design of a low-power and high-efficiency charge pump

Design of a low-power and high-efficiency charge pump

A High Power-Conversion-Efficiency Voltage Boost Converter with MPPT for Wireless Sensor Nodes.

A high power-conversion-efficiency voltage boost converter with MPPT for wireless sensor nodes (WSNs) is proposed in this paper. Since tiny wireless sensor nodes are all over complex environments, an efficient power management system (PMS) must be equipped to achieve long-term self-power supply and maintain regular operation. It is common to use Photovoltaic cells (PV) to harvest sunlight in the environment. However, most existing interface boost integrated circuits for the PV cell have low efficiency. This paper presents a voltage boost converter (VBC) with high power conversion efficiency (PCE) for WSNs. The integrated circuit (IC) designed in this paper includes a novel four-phase high-efficiency charge pump module, an ultra-low-power perturbation observation (P&O) MPPT control circuit module, a feedback control module, a nano-ampere current reference, etc. Manufactured in a standard 0.35 um complementary metal-oxide-semiconductor (CMOS) technology, the chip area is 3.15 mm × 2.43 mm. Test results demonstrate that when the output voltage of the PV cell is more than 0.5 V, VBC can improve the voltage to 3Vin, and the calculated voltage conversion efficiency can reach 99.4%. P&O MPPT algorithm makes output power improving 8.53%. Furthermore, when the output load current is 297uA, the output PCE achieves 85.1%.

Design of a Low Power and High-Efficiency Charge Pump Circuit for RFID Transponder EEPROM

Charge pump (CP) circuit is an essential part of a radio frequency identification electrically-erasable-programmable-read-only memory (RFID-EEPROM). A CP circuit generates boosted output voltage than the power supply voltage. However, the performance of the diode configured CP circuits is strongly affected by the extra power dissipation and the parasitic capacitance. The parasitic capacitors of the CP circuit are also responsible for consuming more power. In this research, an improved CP circuit is designed for achieving higher output voltage gain by reducing the parasitic capacitances. Moreover, the proposed circuit is consumed lower power, which made it more suitable for low power applications like RFID transponder. The proposed CP circuit is using the internal boosted voltage for backward control where active controls are applied to the charge transfer switch (CTS) to eradicate the reverse charge sharing trends. Simulated results showed that by using 1 pF pumping capacitor to drive the capacitive output load, the proposed circuit generates 9.56 V under 1.2 V power supply. In comparison with other research, works this CP circuit is consumed much lower power only 15.26 µW, which is lower than previous research works. Moreover, the proposed CTS CP circuit can produce a higher efficiency of 79.3%, which is found higher compared to other research works. Thus, the proposed design will be an essential module for low power applications like RFID transponder EEPROM.

A high-efficiency charge pump with charge recycling scheme and finger boost capacitor

A 16-phase 8-branch charge pump with finger boost capacitor is proposed to increase the power efficiency and it is implemented in a 0.35 μm high-voltage CMOS IC technology. Compared with the standard capacitor, the finger capacitor can significantly reduce the parasitic capacitance. By combining the charge recycling method and the finger capacitor, the proposed four-stage charge pump can achieve an efficiency of 47.2% and an output voltage of 13.7 V from a 3 V power supply. The proposed charge pump also has better current driving ability and the area of the chip is 2.32 mm × 0.28 mm.

A low-voltage with high pumping efficiency charge pump for flash memory

This paper proposed a high efficiency of power conversion and high pumping gain charge pump applied to the field of low power consumption like flash memory. The threshold voltage drop, body effect and the undesired charge transfer are three significant factors limiting the pumping gain and power conversion efficiency. In order to solve the threshold voltage drop and body effect, the charge transfer switches (CTS) are utilized in the proposed charge pump. What’s more, an optimized substrate control strategy and body-source diode are applied to eliminate undesired charge transfer for improving power efficiency. And a complementary branch scheme is employed to reduce the output voltage ripple. The proposed charge pump is implemented in SMIC 0.18 um standard technology and the simulation results indicate better performance and high efficiency of power conversion. The proposed charge pump satisfies the relevant specifications of the charge pump applied to flash memory.

A high-efficiency charge pump in BCD process for implantable medical devices * * Project supported by the National Natural Science Foundation of China (No. 61474092).

This paper presents a high-efficiency charge pump circuit composed of cascaded cross-coupled voltage doublers implemented in an isolated bipolar-CMOS-DMOS (BCD) technology for implantable medical devices. Taking advantage of the transistor structures in the isolated BCD process, the leakage currents caused by the parasitic PNP transistors in the cross-coupled PMOS serial switches are eliminated by simply connecting the inside substrate terminal to the isolation terminal of each PMOS transistor. The simple circuit structure leads to small parasitic capacitance in the voltage doubler, which in turn ensures high efficiency of the overall charge pump. The proposed charge pump with 5 cascaded voltage doublers is fabricated in a 0.35-μm isolated BCD process. Measurement results with 2-V power supply, 1-MHz driving clock frequency and 40-μA current load show that an efficiency of 72.6% is achieved, and the output voltage can be pumped to about 11.5 V at zero load current. The chip area of the charge pump is 1.6 × 0.35 mm2.

84% High efficiency dynamic voltage scaler with nano-second settling time based on charge-pump and BWC-DAC

This paper introduces an energy-efficient dynamic voltage scaler (DVS) based on charge- pump and binary-weighted capacitor digital to analog converter (BWC-DAC). Conventional DVS architectures suffer from long settling-time beside the limitation of coarse voltage resolution, so we propose DVS architecture based on BWC-DAC architecture. It takes advantage of DAC's reconfigurable structure to provide an output voltage scaled with high resolution of VIN/2N for input voltage VIN and N configuration bits; and Nano-second transition time. However, DAC inherently suffers from low power efficiency because it requires frequent reset to maintain the output voltage. To overcome this issue, a high efficiency charge-pump is employed to restore the charges in DAC's capacitors without the need to reset which results in improved power efficiency. The proposed DVS with a 6-bit DAC and a feedback controlled circuit have been implemented using a 130 nm CMOS process. The measurement results show an accurate 64 voltage levels of the 6-bit DAC from 0 V to 1.476 V, when supplied by an input voltage of 1.5 V. We achieved a peak efficiency of 84% for load current ranging from 1 μA–14.76 μA. Furthermore, it provides an extremely short settling time that is as short as 83.6 Nano second.

High Pumping Gain Dickson Charge Pump Using Improved Bootstrapped Technique

This paper proposed an improved bootstrapped type high-efficient charge pump circuit based on the Dickson charge pump in order to get a higher pumping efficiency. It is not only avoid the threshold voltage drop in conventional Dickson charge pump circuits but enable them to generate a higher output voltage. Simulation by HSPICE shows that for conventional Dickson charge pump, it convert the input low DC-voltage (Vin=1.5V) up to 3.8 times of it (VOUT=5.77V), the pump efficiency was 76.93%. Our work, however, can convert the low input DC-voltage (Vin=1.5V) up near to 4.76 times of it (VOUT=7.14V), the pump efficiency can reaches as high as 95.2%.

A continuous conduction mode low-ripple high-efficiency charge-pump boost converter

In this paper, a new continuous conduction mode (CCM) low-ripple high-efficiency charge-pump boost converter is presented. Its components include a double voltage charge pump and a low pass LC filter. The voltage boost ratio of the positive low-ripple output voltage of the proposed converter is (1 + D) where D is the duty cycle of the control switching signal waveform. Since the energy storage inductor is connected to the power source and the load at all times, the proposed converter always operates in CCM, the transient responses are fast, and the current stress on the output capacitor is reduced and the output voltage ripple is small. In this paper, the operation principles of the CCM low-ripple high-efficiency charge-pump boost converter are described in detail. Its circuitry is designed and implemented with a TSMC 0.35 μm CMOS processes whose operation frequency is 1 MHz. The circuitry is simple and the power conversion efficiency is up to 90.95 %, and the transient response is only 7 μs.

High-Efficiency Charge Pump LED Driver Circuit Design

In this paper, Using CSMC 0.5μm CMOS process to design each sub-module, the circuit simulation, and adjustment and validation of parameters have been carried out by simulation tools. The low static power and high conversion efficiency charge pump LED driver circuit has been designed. The circuits nucleus module is adaptive charge pump (1x/1.5x/2x charge pump), to converse a wider range of input voltage to a constant output voltage with high efficiency. This circuit only needs some external capacitors, and dont need inductor. So it reduces EMI electromagnetic interference and application cost, etc.

A High Efficiency Charge Pump for Low Voltage Devices

A charge pump is a kind of DC to DC converter that uses capacitors as energy storage elements to create a higher or lower voltage power source. Charge pumps make use of switching devices for controlling the connection of voltage to the capacitor. Charge pumps have been used in the nonvolatile memories, such as EEPROM and Flash memories, for the programming of the floating-gate devices. They can also be used in the low-supply-voltage switched-capacitor systems that require high voltage to drive the analog switched. This paper includes voltage analysis of different charge pumps. On the basis of voltage analysis a new charge pump is proposed.

Wireless Front-End With Power Management for an Implantable Cardiac Microstimulator

Inductive coupling is presented with the help of a high-efficiency Class-E power amplifier for an implantable cardiac microstimulator. The external coil inductively transmits power and data with a carrier frequency of 256 kHz into the internal coil of electronic devices inside the body. The detected cardiac signal is fed back to the external device with the same pair of coils to save on space in the telemetry device. To maintain the power reliability of the microstimulator for long-term use, two small rechargeable batteries are employed to supply voltage to the internal circuits. The power management unit, which includes radio frequency front-end circuits with battery charging and detection functions, is used for the supply control. For cardiac stimulation, a high-efficiency charge pump is also proposed in the present paper to generate a stimulated voltage of 3.2 V under a 1 V supply voltage. A phase-locked-loop (PLL)-based phase shift keying demodulator is implemented to efficiently extract the data and clock from an inductive AC signal. The circuits, with an area of 0.45 mm², are implemented in a TSMC 0.35 μm 2P4M standard CMOS process. Measurement results reveal that power can be extracted from the inductive coupling and stored in rechargeable batteries, which are controlled by the power management unit, when one of the batteries is drained. Moreover, the data and clock can be precisely recovered from the coil coupling, and a stimulated voltage of 3.2 V can be readily generated by the proposed charge-pump circuits to stimulate cardiac tissues.

High-Efficiency CTS Charge Pump Using Three-Level Addressing Method

This paper proposes a new addressing method for high-efficiency switching-capacitor DC-DC voltage converter based on combination of CTS (charge-transfer-switch) charge pump and cross-coupled output stage is proposed in order to get a high output power and pump-efficiency. By using three level addressing methods, it can increase both of pump-efficiency and power-efficiency. The proposed three level addressing mixed-structure charge pump can operate at as high as 1MHz switching-frequency on the 0.1 μF pump-capacitors. Simulation by using HSPICE level 3 model shows that our work can convert the input low DC-voltage (Vin=1.5V) up near to 11.26 times of it (VOUT=16.9V), so that more output power can be generated with a little power loss. The newly proposed addressing method for DC-DC charge pump circuit is suitable for various low-voltage applications.

High Pumping Gain Dickson Charge Pump Using Bootstrapped Technique

This paper proposed a bootstrapped type high-efficient charge pump circuit based on the Dickson charge pump for high output power and pump-efficiency. By using bootstrapped technique, it can increase both of pump-efficiency and power-efficiency. The proposed bootstrapped based charge pump can avoid the threshold voltage drop and enable to generate a higher output voltage. Simulation by using HSPICE level 3 model shows that for conventional Dickson charge pump, it convert the input low DC-voltage (Vin=1.5V) up to 3.8 times of it (VOUT=5.77V), the pump efficiency was 76.93%. Our work, however, can convert the low input DC-voltage (Vin=1.5V) up near to 4.4 times of it (VOUT=6.62V), pump efficiency can reach up to 88.26%.

A gain-optimising regulated charge pump

A high-efficiency charge-pump regulator formed by the proposed reconfigurable charge pump is presented in this article. The voltage gain of the reconfigurable charge pump can be adaptively adjusted based on the input voltage and the regulated output voltage. Enhancement of power efficiency is therefore achieved by reducing the conduction loss of the cascaded linear regulator due to the optimised gain of the reconfigurable charge pump. The proposed charge-pump regulator was implemented in commercial complementary metal-oxide semiconductor (CMOS) 0.35 μm technology. The active chip area is 0.46 mm2. The input range is from 1.5 to 3.3 V. The experimental results show that the proposed charge-pump regulator improves the power efficiency by as much as 40% when regulated at 1.2 V.

A high efficient, low power, and compact charge pump by vertical MOSFETs

This paper examines the impact on the charge pump performance by utilizing the merit of the back-bias effect free for the vertical MOSFETs. The simulation results show that the charge pump circuits composed of the vertical MOSFETs can both shrink the charge pump area and lower the power consumption by more than 90% in comparison with the conventional charge pump circuits composed of the planar MOSFETs.

A high efficiency charge pump circuit for low power applications

A high efficiency charge pump circuit is designed and realized. The charge transfer switch is biased by the additional capacitor and transistor to eliminate the influence of the threshold voltage. Moreover, the bulk of the switch transistor is dynamically biased so that the threshold voltage gets lower when it is turned on during charge transfer and gets higher when it is turned off. As a result, the efficiency of the charge pump circuit can be improved. A test chip has been implemented in a 0.18 μm 3.3 V standard CMOS process. The measured output voltage of the eight-pumping-stage charge pump is 9.8 V with each pumping capacitor of 0.5 pF at an output current of 0.18 μA, when the clock frequency is 780 kHz and the supply voltage is 2 V. The charge pump and the clock driver consume a total current of 2.9 μA from the power supply. This circuit is suitable for low power applications.

An area-saving and high power efficiency charge pump built in a TFT-LCD driver IC

An area-saving and high power efficiency charge pump is proposed, and methods for optimizing the operation frequency and improving the power efficiency are discussed. Through sharing coupling capacitors the proposed charge pump realizes two DC–DC functions in one circuit, which can generate both positive and negative high voltages. Due to sharing of the coupling capacitors, as compared with a previous charge pump designed by us for a TFT-LCD driver IC, the die area and the amounts of necessary external capacitors are reduced by 40% and 33%, respectively. Furthermore, the charge pump's power efficiency is improved by 8% as a result of employing the new topology. The designed circuit has been successfully applied in a one-chip TFT-LCD driver IC implemented in a 0.18 μm low/mid/high mixed-voltage CMOS process.

Analysis and Modeling of On-Chip Charge Pump Designs Basedon Pumping Gain Increase Circuits With a Resistive Load

A complete equivalent model and analysis of high-efficiency charge-pump gain-increase (PGI) circuits with resistive loads are proposed. Based on this simple analytical model, the characteristics of PGI circuits can be approximately predicted and several handy equations, which are useful for pencil-and-paper design, can also be found for planning the desired circuit to achieve good enough performance with an acceptable accuracy tolerance in the steady state. In addition, an optimized design method for PGI circuits with resistive loads is developed in terms of the total number of gain stages in the design and the ratio between pump capacitors. For 1.5 V supply voltage operation, reliability and accuracy are demonstrated by comparisons between SPICE simulations of the PGI circuit and the results from the equivalent model. The model also has been validated by means of measurements taken from a test chip and typically shows relative open-loop output voltage errors lower than 8%. Finally, although the derivation of the model was based on a PGI circuit, it is shown that the design strategy can also be applied to other charge pump designs that have no voltage drop between the inner stages and the output stage.

Novel Low-Power DC–DC Converter Using High-Efficiency Charge Pump Circuits for Flat Panel Displays

A novel design for a low-power DC–DC converter using high-efficiency charge pump circuits for flat panel displays (FPDs) is proposed. The designed converter uses a variable voltage level shifter to decrease the conduction power loss of the charge pump circuit. The output voltage and the output current of the proposed DC–DC converter consisting of five charge pump circuits operating at 3.3 V are 17 V and 10 mA, respectively. The power efficiency and the ripple voltage of the designed charge pump circuits are 84.9% and 65 mV, respectively, which is a significant enhancement over those of Dickson charge pump circuits. These results indicate that our newly designed, low-power DC–DC converter using high-efficiency charge pump circuits holds promise for potential applications in mobile devices fabricated using FPDs operating at low voltages.