High-efficiency Buck Converter Research Articles

A high efficiency buck converter based on PLL for frequency stabilization

A high efficiency Buck converter circuit based on Phase-locked loop (PLL) to achieve frequency stabilization is proposed to solve the problems of reduced converter efficiency, unstable output and high electromagnetic interference caused by unstable switching frequency. Since the increase of load current increases the switching frequency in the conventional adaptive on-time (AOT) control, a phase-locked loop is designed to achieve the switching frequency stabilization by forming a negative feedback. In addition, a bootstrap high-voltage gate driver circuit is designed to drive the dual NMOS power tubes in order to achieve high conversion efficiency and optimize the chip area. The proposed Buck circuit is simulated and verified based on SMIC 0.18 μm CMOS 2P4M process, with an input voltage of 2.5V–5.5V, an output voltage of 0.8V–4V, a switching frequency variation rate of only 8.5 kHz/A over the load range of 0.5A–3A, and a peak efficiency of 94.8 % over the full load range is achieved, and the undershoot/overshoot recovery time of the load transient response is only 5.4μs and 6.9μs.

Mode Switching Technique for High Efficiency Buck Converter

In order to achieve high efficiency in a wider load range, a PWM/PFM/Power-Saved mode dc–dc buck converter is proposed. The mode switching technique is based on an accurate power loss model consisting of critical components/parameters: The size of the power transistor and the ON/OFF status of power-hungry subcircuits. The circuit of mode switching technique is achieved by the reference, pulse skipped modulation (PSM) comparator and feedback resistors, and its own consumption of quiescent current is extremely low. At ultra-light load, by detecting the ZCD duration and the ripple of the output, the system can switch to the Power-Saved-Mode. The proposed buck converter was implemented by using a 0.18 [Formula: see text]m CMOS process. It achieves a peak efficiency of 97% and [Formula: see text]90% efficiency from 100 [Formula: see text]A to 600 mA. A 360 nA quiescent current is achieved. With a low output ripple of less than 60 mV, the input voltage range and regulated output voltage are 3.6–5 V and 1.2–3.3 V, respectively.

A New Improved Second-Order Delta-Sigma-Modulation Buck Converter With Low-Noise and Transient-Acceleration Loops

In this article, we propose a new improved fast-transient-response and low-noise high-efficiency buck converter with second-order continuous-time delta-sigma-modulation (CT-DSM) techniques. First, by utilizing the oversampling theorem and noise-shaping technique with the second-order delta-sigma modulation, the output noise within the bandwidth can be reduced effectively. Second, the adding of the transient acceleration loop not only can improve the transient recovery time when the load current changed but also lowers the undershoot and overshoot voltage. Third, a rail-to-rail operational transconductance amplifier without voltage dividers is employed in the proposed converter, which helps sensing the inductor current, moving the inductor pole to a high frequency, speeding up the transient response, and stabilizing the proposed converter modules. Finally, the proposed converter has been implemented with TSMC 0.18 μm 1P6M process and occupies an area of 1.19 × 1.19 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . When the load current changed from 50 to 500 mA and 500 to 50 mA, the transient recovery time was both 4 μs, which improved 8 and 16 μs than the traditional CT-DSM converter. The output voltage ripples are kept under 13 mV and the overshoot and undershoot voltage is 20 and 14 mV, respectively. The measured output-to-noise ratio is 80.7 dB, with the sampling frequency of 10 MHz. The peak efficiency is 92.1%, at the output voltage of 2.5 V and load current of 150 mA.

A High-Efficiency Current-Mode Buck Converter With a Power-Loss-Aware Switch-On-Demand Modulation Technique for Multifunction SoCs

Modern multifunction systems on chip often require a high-efficiency buck converter over a wide load current range as the main power source, for which complex multimode operation with mode detection/change is a frequent compromise between efficiency and transient response. This paper proposes a novel power-loss-aware switch-on-demand modulation (PLASOM) technique based on accurate power loss modeling to switch critical components/parameters of power loss on demand: the ON/OFF status and the size of the power transistor, the dead time, and the ON/OFF status of power-hungry subcircuits. The proposed PLASOM-based converter can work as either an adaptive on-time mechanism with constant frequency or a cycle-extended adaptive ON/OFF-time mechanism with variable frequency without mode detection/change, so that the conversion efficiency and transient response can be improved. A proposed buck converter with the PLASOM technique was implemented using the TSMC 90-nm 1/3.3-V CMOS process. Experimental results show that a conversion efficiency higher than 90% was achieved over the 1–500 mA load current range, whereas the voltage variation/recovery time during the 0.1–500 mA load transient were less than 50 mV/25 μs. Performance evaluations indicate that the proposed PLASOM technique is favorable for wide load current range buck converters in terms of conversion efficiency, transient response, and voltage ripples.

High Efficiency Buck-Converter with Short Circuit Protection

This paper proposes a DC-DC Buck-Converter with DT-CMOS (Dynamic Thresholdvoltage MOSFET) Switch. The proposed circuit was evaluated and compared with a CMOS switch by both the circuit and device simulations. The DT-CMOS switch reduced the output ripple and the conduction loss through a low on-resistance. Overall, the proposed circuit showed excellent performance efficiency compared to the converter with conventional CMOS switch. The proposed circuit has switching frequency of 1.2MHz, 3.3V input voltage, 2.5V output voltage, and maximum current of 100mA. In addition, this paper proposes a SCP (Short Circuit Protection) circuit to ensure reliability.

A fast and high efficiency buck converter with Switch-On-Demand Modulator for wide load range applications

This paper presents a buck converter with a switch-on-demand modulator (SOM) for achieving a fast transient response, small voltage ripple, and high power efficiency over a wide load range. Switching power MOS on or off depending on the energy demand of the load circuit results in a hybrid operation of pulse width modulation (PWM) and pulse frequency modulation (PFM). The proposed buck converter uses 90nm CMOS process and can achieve a transient response time of less than 2µs and a voltage ripple of 18mV at a load current range of 10mA∼500mA with a power efficiency above 88%.

A High-Efficiency DC–DC Converter Using 2 nH Integrated Inductors

Historically, buck converters have relied on high-Q inductors on the order of 1 to 100 muH to achieve a high efficiency. Unfortunately, on-chip inductors are physically large and have poor series resistances, which result in low-efficiency converters. To mitigate this problem, on-chip magnetic coupling is exploited in the proposed stacked interleaved topology to enable the use of small (2 nH) on-chip inductors in a high-efficiency buck converter. The dramatic decrease in the inductance value is made possible by the unique bridge timing of the stacked design that causes magnetic coupling to boost the converter's efficiency by reducing the current ripple in each inductor. The magnetic coupling is realized by stacking the two inductors on top of one another, which not only lowers the required inductance, but also reduces the chip area consumed by the two inductors. The measured conversion efficiency for the prototype circuit, implemented in a 130-nm CMOS technology, shows more than a 15% efficiency improvement over a linear converter for low output voltages rising to a peak efficiency of 77.9 % for a 0.9 V output. These efficiencies are comparable to converters implemented with higher Q inductors, validating that the proposed techniques enable high-efficiency converters to be realized with small on-chip inductors.

Analysis of buck converters for on-chip integration with a dual supply voltage microprocessor

An analysis of an on-chip buck converter is presented in this paper. A high switching frequency is the key design parameter that simultaneously permits monolithic integration and high efficiency. A model of the parasitic impedances of a buck converter is developed. With this model, a design space is determined that allows integration of active and passive devices on the same die for a target technology. An efficiency of 88.4% at a switching frequency of 477 MHz is demonstrated for a voltage conversion from 1.2-0.9 volts while supplying 9.5 A average current. The area occupied by the buck converter is 12.6 mm/sup 2/ assuming an 80-nm CMOS technology. An estimate of the efficiency is shown to be within 2.4% of simulation at the target design point. Full integration of a high-efficiency buck converter on the same die with a dual-V/sub DD/ microprocessor is demonstrated to be feasible.