Abstract
In order to achieve high efficiency in a wider load range, a PWM/PFM/Power-Saved mode dc–dc buck converter is proposed. The mode switching technique is based on an accurate power loss model consisting of critical components/parameters: The size of the power transistor and the ON/OFF status of power-hungry subcircuits. The circuit of mode switching technique is achieved by the reference, pulse skipped modulation (PSM) comparator and feedback resistors, and its own consumption of quiescent current is extremely low. At ultra-light load, by detecting the ZCD duration and the ripple of the output, the system can switch to the Power-Saved-Mode. The proposed buck converter was implemented by using a 0.18 [Formula: see text]m CMOS process. It achieves a peak efficiency of 97% and [Formula: see text]90% efficiency from 100 [Formula: see text]A to 600 mA. A 360 nA quiescent current is achieved. With a low output ripple of less than 60 mV, the input voltage range and regulated output voltage are 3.6–5 V and 1.2–3.3 V, respectively.
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