The performance and architecture of a high dynamic range camera (HDRC) chip and the conceptional advantages for its adaptation to image processing systems in traffic environments are discussed. The HDRC chip was developed with 64*64 pixels using a standard digital 1.2- mu m CMOS technology. It is shown that the implementation proves the functionality and indicates the system performance of a highly dynamic range camera is feasible.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>