High Density Printed Circuit Boards Research Articles

Fast Calculation Method for Crosstalk of High-Density Printed Circuit Board by Using Machine Learning

Fast Calculation Method for Crosstalk of High-Density Printed Circuit Board by Using Machine Learning

Crosstalk Reduction in High-Density Radio Frequency Printed Circuit Boards: Leveraging FR4 Coating Layers

The escalating component density in radio frequency (RF) systems presents a growing challenge related to the coupling of adjacent microstrip lines in high-density printed circuit boards (PCBs). As a result, to tackle this prominent issue, there is a continuous pursuit of innovative techniques to effectively minimize the coupling effects among closely spaced microstrip lines. This paper proposes a reduction in the coupling of adjacent lines by utilizing a coating (stiffener) layer, which is commonly used in rigid-flex PCB fabrication. For this purpose, a reference 50 Ohm coupled line performance was compared to three coupled lines with track widths of 1.39 mm, 1.30 mm, and 1.25 mm, respectively, all at a fixed distance between the tracks. These decreasing widths were used to achieve the same 50 Ohm impedance for the coupled lines when covered with different coating layers. Each of these three coupled lines was covered with different coating (stiffener) layers, measuring 0.1 mm, 0.3 mm, and 0.5 mm in thickness, respectively. The manufactured device under test (DUT) structures underwent time-domain reflectometry (TDR) and S-parameter measurements. The TDR measurements of the DUT structures with coating layers demonstrated excellent conformity to the 50 Ohm reference coupled line. Meanwhile, the S21 measurements indicated a significant decrease in the crosstalk. For example, for a coating layer thickness of 0.3 mm, the crosstalk decreased by approximately 5–6 dB within the frequency range up to 5 GHz. When the coating layer thickness was 0.5 mm, the crosstalk decreased by approximately 10 dB or more.

Superconformal Deposition for Building 3D Circuitry

State of the art manufacturing of microelectronics involves the electrodeposition of copper for fabricating on-chip interconnects, through-silicon-vias for chip stacking, and high density printed circuit boards. This lecture will present a selection of highlights related to superconformal electrodeposition of Cu ranging from its history to its impact on processing of microelectronic circuitry and, more generally, the understanding of additive effects in electrodeposition. The story begins in the mid-20th century with the formal discovery of the effectiveness of plating additives in yielding smooth surfaces i.e. brighteners and levelers, before pivoting to the IBM paradigm changing introduction of complex 3-D Damascene Cu superfilling for on-chip interconnects in 1997. The role of electroanalytical, metallurgical, and surface science measurements along with insights, and modeling to develop a mechanistic understanding of morphological and microstructural evolution during trench and via filling will be detailed. The lessons learned and their extension to other chemical systems and applications will be discussed along with the challenges that lie ahead.

Facile dynamic current deposition of high tensile gradient Cu foil with (110) preferred orientation

The conductive copper (Cu) foil is an important raw material in the electronic industry. However, the traditional Cu foil with low tensile strength (∼350 MPa) and poor toughness is prone to breakage during production and usage, which is not conducive to its application in high-density printed circuit boards and high-energy-density batteries. In this work, we report a facile dynamic current deposition (DCD) method for preparing a gradient Cu foil with adjustable thickness (9–50 µm) and a highly preferred crystal orientation of Cu (110). The gradient Cu foil transitions gradually from micron-scale coarse grains to nano-scale fine grains, which promotes its tensile strength (∼840 MPa) while maintaining toughness (∼3.6%). Particularly, the gradient Cu foil shows a high conductivity of 3.3 × 107 S m−1, indicating its promising application in negative electrode current collectors of lithium-ion batteries and printed circuit boards. The facile DCD method can also provide guidance for the fabrication of other metallic materials.

Next-Generation High-Density PCB Development by Fan-Out RDL Technology

High-density interconnect (HDI) printed circuit boards (PCBs) are in high demand for smartphones, particularly those with fifth generation (5G) functionality, due to their smaller form factors, higher interconnection densities, and improved integrative ability. Various advanced PCB technologies are available, including HDI PCBs and substrate-like PCBs (SLPs). However, even for substrate-like PCBs, the line width (L) and spacing (S) of the copper traces are limited to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$25~\mu \text{m} / 25~\mu \text{m}$ </tex-math></inline-formula> , and fine-line development also faces yield and cost challenges. Accordingly, the present study utilizes an redistribution layer (RDL) first fabrication process to develop a fine line width/spacing ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10~\mu \text{m} / 10~\mu \text{m}$ </tex-math></inline-formula> ) Fan-out interposer (FOI) on PCB architecture with a higher I/O (Input/Output) density, greater yield, and lower cost. A three-dimensional (3D) ANSYS finite element (FE) model combined with volume fractions approach applied to equivalent thermomechanical properties of the multilayer RDL is introduced. The validity of the simulation model is confirmed by comparing the numerical results for the out-of-plane deformation of the top surface of the FOI with the experimental observations. Then, the effects of five design parameters on the warpage and solder joint stress performance of the FOI-PCB architecture are identified through parametric analysis. Finally, a second-order response surface methodology (RSM) model and Box-Wilson central composite design (CCD) method are employed to examine the interactive effects of the structural design factors of the FOI-PCB architecture on the FOI warpage under typical manufacturing thermal loading conditions. It is shown that a smaller overall size of the FOI is beneficial in reducing the warpage by minimizing the coefficient of temperature expansion (CTE) mismatch between the interposer and the PCB.

Design, Modeling, and Evaluation of a Class-A Triaxial Force-Balance Accelerometer of Linear Based Geometry

Abstract A new class-A force-balance accelerometer (FBA) is designed, simulated, and evaluated. The focus of this work was to design a low-cost but high-performance instrument. The FBA has output voltage proportional to ground acceleration, flat response from direct current to 200 Hz, output range ± 10 V differential (40Vpp, peak-to-peak) and sensitivity 2.5 V/g, which provides a ± 4g range. Unlike other well-established designs with rotational pendulum systems and single-coil actuators that present partially nonlinear performance, the proposed design is based on a linear motion spring-mass mechanism with two parallel leaf springs and a double symmetrical magnet-coil force actuator. This architecture ensures that the displacement transducer’s response is linear and that an acting force on the seismic mass is not disturbed by any cross-axial motion. This force depends on displacement only, as imposed by the electronic control circuit, which is implemented on a small high-density printed circuit board (PCB) mounted on top of the mechanical construction. The plates of the variable capacitance displacement transducer consist of ordinary PCBs for cost efficiency. The coils of the force actuator are placed on each side of the moving plate of the capacitive transducer and the magnets are placed on the aluminum rigid frame of the device. The central moving plate of the variable capacitor and the attached force actuator coils, along with some extra aluminum mass, consist the accelerometer’s seismic mass. The performance of the accelerometer is evaluated in terms of earthquake data records and in comparison of its response with that of a commercial FBA with corresponding specifications. The instrument’s self-noise was also measured over a long period of operation and proved to comply with typical FBA application requirements and commercial product standards.

Adhesion mechanism between mold resin and sputtered copper for electromagnetic wave shield packages

As mobile information and communication terminals become smaller and more sophisticated, electronic device manufacturers are increasingly demanding that electromagnetic interference measures be added to individual electronic components assembled on high-density printed circuit boards. Therefore, semiconductor device products require a process for forming electromagnetic wave shielding film. Sputtered film deposition methods with stable processes are increasingly used for the formation of shield films. Although Cu is often used as the shield film, there has been little discussion of the adhesion mechanism with the mold resin used in semiconductor device products. In this work, Cu film was sputter-deposited onto mold resin under a variety of conditions, and the factors that influence adhesion were investigated. The results show that it is necessary to carry out degassing in the sputtering equipment at temperatures higher than 180°C, above which the amount of degassing increases. No clear relationship was found between surface roughness and adhesion. The exposure ratio of the SiO2 filler was found to be related to adhesion. The mechanism of adhesion between the mold resin and sputter-deposited Cu film was considered from the experimental results, and the following models are proposed. Plasma etching exposes SiO2 filler at the surface of the mold resin and increases the surface free energy. The surface becomes activated, which is thought to create adhesion between the Cu and SiO2 filler.

A Method of Optimizing Characteristic Impedance Compensation Using Cut-Outs in High-Density PCB Designs.

The modern era of technology contains a myriad of high-speed standards and proprietary serial digital protocols, which evolve alongside the microwave and RF realm. The increasing data rate push the requirements for hardware design, including modern printed circuit boards (PCB). One of these requirements for modern high-speed PCB interfaces are a homogenous track impedance all the way from the source to the load. Even though some high-speed interfaces don’t require any external components embedded into the interconnects, there are others which require either passive or active components—or both. Usually, component package land-pads are of fixed size, thus, if not addressed, they create discontinuities and degrade the transmitted signal. To solve this problem, impedance compensation techniques such as reference plane cut-out are employed for multiple case studies covering this topic. This paper presents an original method of finding the optimal cut-out size for the maximum characteristic impedance compensation in high-density multilayer PCB designs, which has been verified via theoretical estimation, computer simulation, and practical measurement results. Track-to-discontinuity ratios of 1:1.75, 1:2.5, and 1:5.0 were selected in order to resemble most practical design scenarios on a 6-layer standard thickness PCB. The measurements and simulations revealed that the compensated impedance saturation occurs at (150–250%) cut-out widths for a 50 Ω microstrip.

Design and Optimization Methods of the Header of HDI PCB Rogowski Current Sensors

Printed circuit board (PCB)-based headers of Rogowski current sensors (HRCSs) have garnered growing interest from researchers in recent years, and they have been widely applied in many electrical scenarios due to their advanced features, such as nondeformable volume, flexible shape and size, and low cost. The determination of PCB HRCS parameters mainly depends on a time-consuming finite-element simulation, but these simulations cannot be used to calculate PCB HRCSs with a complex irregular structure or high-density thin winding wire. This article presents a method to calculate a PCB HRCS to address complex irregular structures and high-density thin winding wire. Furthermore, because it does not involve the time-consuming meshing process, this method is relatively fast. Taking two HRCSs with a given complex structure and thin winding wire as examples, we used the proposed method to determine its sensitivity, anti-interference characteristics, and the influence of the obtained internal parasitic capacitance and inductance parameters on the measured output voltage. Moreover, the optimal structural parameters of these PCB HRCSs are discussed when the installation space and the cross section of the measured conductor are given. The results of the high-density PCB HRCS experiments verify the proposed method.

Data-Driven Life Modeling of Electrochemical Migration on Printed Circuit Boards Under Soluble Salt Contamination

Under the air pollution environment, the dust enters the electronic products and deposits on the printed circuit boards (PCB) during the service life. Soluble salts in the airborne dust can reduce the critical humidity and increase the ion concentrations on condensed water film on PCB, which has been proven to aggravate the insulation failure of the high-density PCB caused by electrochemical migration (ECM). It is practical application significance for how to establish a life model to evaluate the ECM of PCB under the interaction of soluble salt with temperature, relative humidity, and electric field strength. In this article, through the temperature humidity bias acceleration experiment, the ECM failure of PCB under the contamination of the different concentrations of NaCl solution is simulated, and the ECM characteristics and failure mechanism are studied through the change of surface insulation resistance (SIR) and the morphology and element compositions of migration products. The time to the insulation failure of PCB under different conditions are obtained by the analysis of SIR curves. Based on the data-driven method, the life modeling of ECM failure of PCB under soluble salt contamination is studied by multivariate non-linear regression and machine learning methods, such as support vector regression, gradient boost regression tree, and random forest regression. It is proved that it is valid to use machine learning to establish the ECM failure life model of PCB in complex environments with limited life data.

Equation-Based Solutions to Coupled, Asymmetrical, Lossy, and Nonuniform Microstrip Lines for Tab-Routing Applications

In this paper, analytical equation-based solutions are derived to allow quick and accurate calculations directly from the physical parameters of coupled, asymmetrical, lossy, and nonuniform microstrip lines with interdigital trapezoidal tabs incorporated, resulting in their corresponding scattering parameters. Capacitance and inductance matrices under a quasi-static condition are derived from the cross-sectional dimensions of asymmetrical coupled microstrip lines with unequal widths. They are converted into a frequency-dependent resistance–inductance–conductance–capacitance model, allowing complete equation-based solutions to their four-port Z-matrix, S-matrix, and ABCD-matrix. As an application example of tackling the complexity of transmission lines, the derived analytical method is applied to a transitional structure with linearly varying trace width in tabbed microstrip lines by the method of segmentation. In addition, a new concept of tab-coupling fringing capacitance is specifically introduced to compensate for underestimated mutual capacitance at tab positions, which will improve the accuracy of the proposed approach. Numerical modeling results from commercial simulation tools are compared for validation purposes. As a conclusion, the proposed method and its versatility are demonstrated with applications to practical high-speed and high-density printed circuit board designs, which renders itself effective and efficient in an optimization process.

Direct Time-Domain TAN Model of 3D Multilayer Hybrid PCB: Experimental Validation

The multilayer technology constitutes the ultimate solution for the design of high-density printed circuit board (PCB). Challenging modeling method is required to predict the signal integrity (SI) of the multilayer PCB. This paper addresses an unfamiliar direct time-domain model of a 3-D multilayer hybrid PCB. The subnetwork primitive elements of the equivalent graph are constituted by lumped components, interconnect lines, vias, pads, and anti-pads. The tensorial analysis of networks (TANs) is used to solve the problem related to the graph topology in the function of the PCB design parameters. The TAN concept is based on the interaction between the primitive elements. The mesh currents constitute the proposed computational unknowns. The unfamiliar model is validated with a three-port network prototype constituted by the six-layer PCB, including passive SMD components. In the frequency domain, S-parameter validation from 100 kHz to 5 GHz is presented. By using 80-Mb/s and 0.5-Gb/s rate data patterns, the proposed TAN model is validated by both simulations and measurements in the time domain. The transient results present vector magnitude relative error accuracy lower than 15%. Thanks to the computation speed and adaptability to multilayer hybrid structures, the TAN model is a prominent approach for the SI and power integrity analyses of 3-D multilayer structures.

A Novel Soft Switching Bidirectional DC–DC Converter Using Magnetic and Capacitive Hybrid Power Transfer

This paper proposes a new bidirectional dc-dc converter capable of improving the convenience and modularity of the dc power grid system. By the unique operation of the $LC$ resonant transformer, the proposed converter achieves bidirectional power control with only two switches. Also, the resonant transformer drives the soft switching turn-on and turn-off over a wide power range. Hence, the circuit has high potential to downsize the converter by exploiting high frequency and simplicity. This paper provides the operating principle and the experimental verification of the proposed circuit. A prototype was fabricated by using a simple and high-density printed circuit board ($\geq$ 10 W/cc). It is verified that the circuit resonant operation successfully drives bidirectional power control with high efficiency ($\geq$92%). An application example is also provided for dc grid system integration.

Preparation of High-Speed Signal Transmission Line on Thin Polyimide Layer By All-Wet Process

Polyimide materials are widely used for printed circuit board as substrate/insulation layer because of its high mechanical stability, high electrical insulation properties, high heat resistance, etc. Low dielectric constant and superior flat surface are requested for applying to high speed signal circuit. Applying the polyimide film to high-speed circuit board, high adhesion length and superior flat interface between metal wiring and polyimide is needed. Our group proposed an all-wet process to fabricate the diffusion barrier layer and Cu wiring by using an organosilane layer as an adhesive/catalyst layer [1, 2]. Additionally, wet processes offer relatively simple procedures and tools, and usually are cost effective. In previous study, an immobilized aminosilane film on polyimide works as an adhesion layer and a catalyst supporting layer for electroless deposition of NiB. This process showed superior smooth surface of catalyzed polyimide because of without etching processes. Adhesion of electroless-deposited NiB film on superior smooth polyimide is a particular need for realizing a high-density printed circuit board [3,4]. In this investigation, this technique was applied for preparation of the silicone chip substrate called interposer. The high-speed signal transmission line for interposer was developed by our proposed method. Soluble block copolymerization polyimide (Q-VR-X1014, PI R&D CO.,LTD) was used for polyimide film source, and thin polyimide layer with and superior flat surface was prepared on glass substrate by spin-coating. After drying, hydrophilic surface of polyimide was developed by UV-irradiation in 10 min. Aminosilane layer in the polyimide was formed in toluene solution containing aminocilane molecule at 60 oC, 10 min. Then, modified surface was catalyzed by palladium, and thin metal layer as seedlayer/adhesion layer and conductive layer were formed by electroless NiB deposition and Cu electrodeposition, respectively. Cu electrodeposition was carried out using alkaline electrolytes bath (Meltex Inc). First, Cu electrodeposition on polyimide was investigated. Figure 1 shows schematic illustration of electrodeposited Cu film on aminocilane-modified polyimide film. To form Cu conductive layer using electrodeposition with conventional acidic bath, film peeling between Pd/aminosilane interfaces was observed. Acid condition was affected for Pd catalyst layer, and Pd was dissolved from the aminocilane supporting layer. We therefore used the alkaline electrolytes bath for Cu electrodeposiotion. We optimized operating condition of electrodeposition and thermal annealing to decrease electronic conductivity, adhesion strength. Using this optimized condition, Cu film with 2 μΩcm could be obtained. Second, roughness of the surface and its interface was measured. Figure 2 shows cross sectional TEM image of electrodeposited Cu film on aminosilane-modified polyimide film after annealing. Roughness of interface between polyimide and NiB was not observed and superior smooth interface was obtained using this technique. Moreover, surface roughness of deposited Cu film was very smooth of Rq = 14 nm. Final, a coplanar waveguide as high-speed signal transmission line was fabricated by this technique. Cu wiring was prepared by semi-additive method. Line width was 100 μm, and film thickness and space between grand and signal line was varied. The characteristic impedance of the fabricated coplanar waveguide showed almost the same value of the theoretical designed one that was 50 Ω.

Near end crosstalk reduction using slow wave structures

Slow wave structures concept is used to mitigate near-end crosstalk by adjusting electrical length (phase velocity) of microstrip line. Proposed microstrip line configuration consists of periodic shunt capacitive stubs, which affect the phase constant and characteristic impedance of the line. Designed low-crosstalk microstrip line is simulated and feather fabricated. Near-end crosstalk reduction around 15 dB is achieved by means of slow wave technique. Measurement results are in good agreement with simulations. Proposed microstrip line shows promising technique in high-density printed circuit boards.

(Invited) A Wet Process of Copper Wiring on Surface Modified Polyimide Film By Aminosilanes

Polyimide (PI) film is widely used in several applications especially in the electronics industry, e.g., as a base material for flexible printed wiring assembly, because of its excellent mechanical and thermal stability and a low dielectric constant. Our group proposed an all-wet process to fabricate the diffusion barrier layer and Cu wiring by using an organosilane layer as an adhesive/catalyst layer as shown in fig. 1 [1, 2]. Additionally, wet processes offer relatively simple procedures and tools, and usually are cost effective. In previous study, an immobilized aminosilane film on polyimide works as an adhesion layer and a catalyst supporting layer for electroless deposition (ELD) of NiB. Adhesion of NiB-ELD film on ultra-smooth polyimide is a particular need for realizing a high-density printed circuit board [3]. We have reported that an induction time of NiB-ELD was changed by the number of amino groups in aminosilane, and a shorter induction time was found in the aminosilane having two or three amino groups as compared with that having single. Our recent critical problem is in the step of Cu deposition onto NiB-ELD: a low reduction rate of cupric ion in sulfuric acid, or if the reduction proceeded, the film peeling was observed. We therefore used the alkaline electrolytes developed by Japanese company or it’s improved to fabricate Cu wiring, and examined thermal annealing effect on the electronic conductivity, crystallinity.

A 10-Gbps × 12-Channel Pluggable Parallel Optical Transceiver Based on CXP Interface Specifications

A novel 10-Gbps × 12-channel pluggable parallel optical transceiver is designed and fabricated. Compared with other optical transceivers, this transceiver emphasizes small size, high-density, low power consumption, and high transmission speed. Most importantly, its optical coupling structure is simplified to promote cost-effective large-scale production. This transceiver is electrically pluggable and consists of transmitter and receiver modules linked by parallel multi-mode fibers. Each module consists of a six-layered high-speed, high-density printed circuit board, the size of which is 30 mm × 18 mm × 1 mm, packaged with optoelectronic devices and corresponding control chips. The printed circuit boards not only provide a high-speed electrical connection between the I/O interfaces and high-speed chips, but they also supply power and ground planes to those chips. End-to-end error-free transmission at 10.3125 Gbps was obtained for a 231 − 1 non-return-to-zero pseudo-random bit sequence.

Suppression of Crosstalk in High-density Printed Circuit Boards by Coating Electroless-plated Ni-P Alloy Film on Signal Lines

High-density printed circuit boards (PCBs) with less than 50 μm/50 μm line/space has been developed. Since the spacing between adjacent signal lines becomes very narrow in the PCBs, the crosstalk from electromagnetic interference in adjacent lines becomes serious. The authors have proposed a magnetic method of reducing the crosstalk. PCBs with electroless-plated Ni-P alloy film on the signal lines were fabricated. From an experiment using a PCB-TEG with a 130 μm/50 μm line/space and 25-mm line length, crosstalk was suppressed throughout a wide frequency range. In using 6-μm thick Ni98P2.0 (wt.%) alloy film, the suppressed crosstalk was up to 12 dB around 1 GHz. However, the influence of transmission and reflection in the main signal line was very small.

Signal integrity analysis of high speed and high density PCB design based on FPGA

According to the Moore's law,it becomes more and more complex to design high-speed and high-density Printed Circuit Board (PCB).As to Signal Integrity (SI) of large or extra large high-speed and high-density PCB,a research method combing theory analysis and mode simulation with project practice was introduced;meanwhile,some solutions or design rules were put forward.Following issues were discussed:PCB stack-up,the styles of transmission line,characteristic impedance calculation,topology,terminations,delay matching,crosstalk,differential pair layout,etc.On this basis,a few of principles were given about multilayers PCB design based on Field Programmable Gate Array (FPGA).Specific project application proves that high-speed and high-density PCB design can get good practical results driven by these principles or mechanisms.

Cross-Talk Suppression in High-Density Printed Circuit Boards Using Magnetic Composite Filled in Spacing Between Signal Lines

Recently, high-density printed circuit boards (HD-PCBs) with less than 50 mum/50 mum line/space has been developed. In the HD-PCB, since the spacing between adjacent signal lines becomes very small, the crosstalk electromagnetic interference among adjacent lines becomes serious. In general, in order to suppress the crosstalk, the ground line is located at the spacing between signal lines because of the decrease of mutual capacitance among adjacent signal lines. The authors have proposed a magnetic method for reducing the crosstalk. The composite magnetic material was filled in the spacing between signal lines instead of the ground line. The magnetic composite is composed of Fe-Si-B-Cr amorphous particles with a mean diameter of 6 mu m and epoxy resin. From the experiments using the PCB-TEG with a 130 mum/50 mum line/space and 25-mm line length, the crosstalk was suppressed in the wide frequency range by using the magnetic composite. In the case of using 51 vol.% amorphous composite, the crosstalk suppression was up to 20 dB around 1 GHz. The influence of the magnetic composite on the transmission and reflection in the main signal line was very small. Therefore, the proposed method is effective for crosstalk suppression without influence on the signal transmission.