High Density Of Interface States Research Articles

Plasma deposited amorphous silicon passivation layers on InAs surfaces

The compound semiconductors (InAs, GaSb, AlSb) having nearly matched lattice constants (≈6.1 Å) are of great interest in fabrication of infrared micro/optoelectronics, but are hampered significantly by a high density of interface states that lead to degenerately doped surface layers. Native oxides are a cause of interface states, as well as a barrier to the effective passivation of dangling bonds, and must be removed. Re-oxidation must then be prevented prior to deposition of a passivant. We demonstrate effective removal of the native oxide of InAs through utilization of an amorphous silicon plasma enhanced chemical vapor deposition process. A hydrogen-diluted silane plasma provides a reducing environment to react and remove indium and arsenic oxide species while a thin layer of amorphous silicon is grown to passivate and prevent re-oxidation of the InAs surface. The reduction of native oxide species via hydrogen-diluted argon plasma as a pretreatment prior to amorphous silicon was also explored. The surface chemistry is verified via depth profiling X-ray photoelectron spectroscopy, and the impact of a hydrogen-argon plasma pretreatment investigated to further reduce oxygen concentration at the InAs/amorphous silicon interface.

An ITO-Free Kesterite Solar Cell.

Photovoltaic thin film solar cells based on kesterite Cu2 ZnSn(S, Se)4 (CZTSSe) have reached 13.8% sunlight-to-electricity conversion efficiency. However, this efficiency is still far from the Shockley-Queisser radiative limit and is hindered by the significant deficit in open circuit voltage (VOC ). The presence of high-density interface states between the absorber layer and buffer or window layer leads to the recombination of photogenerated carriers, thereby reducing effective carrier collection. To tackle this issue, a new window structure ZnO/AgNW/ZnO/AgNW (ZAZA) comprising layers of ZnO and silver nanowires (AgNWs) is proposed. This structure offers a simple and low-damage processing method, resulting in improved optoelectronic properties and junction quality. The ZAZA-based devices exhibit enhanced VOC due to the higher built-in voltage (Vbi ) and reduced interface recombination compared to the usual indium tin oxide (ITO) based structures. Additionally, improved carrier collection is demonstrated as a result of the shortened collection paths and the more uniform carrier lifetime distribution. These advances enable the fabrication of the first ITO-free CZTSSe solar cells with over 10% efficiency without an anti-reflectivecoating.

Interface and oxide trap states of SiO2/GaN metal–oxide–semiconductor capacitors and their effects on electrical properties evaluated by deep level transient spectroscopy

The relationship between the electrical properties and the carrier trap properties of the SiO2/GaN metal–oxide–semiconductor (MOS) capacitors was investigated using electrical measurements and deep level transient spectroscopy (DLTS). The capacitance–voltage (C–V) measurement showed that the frequency dispersion of the C–V curves became smaller after an 800 °C annealing in O2 ambient. DLTS revealed that before the annealing, the interface trap states, in a broad energy range above the midgap of GaN, were detected with the higher interface state density at around 0.3 and 0.9 eV below the conduction band minimum (EC) of GaN. Moreover, the oxide trap states were formed at around 0.1 eV below the EC of GaN, plausibly indicating a slow electron trap with a tunneling process. Although both trap states affect the electrical reliability and insulating property of the SiO2/GaN MOS capacitors, they were found to drastically decrease after the annealing, leading to the improvement of the electrical properties.

Investigation of Reducing Interface State Density in 4H-SiC by Increasing Oxidation Rate.

Detailed investigations of the pre-oxidation phosphorus implantation process are required to increase the oxidation rate in 4H-SiC metal-oxide-semiconductor (MOS) capacitors. This study focuses on the SiO2/SiC interface characteristics of pre-oxidation using phosphorus implantation methods. The inversion channel mobility of a metal-oxide-semiconductor field effect transistor (MOSFET) was decreased via a high interface state density and the coulomb-scattering mechanisms of the carriers. High-resolution transmission electron microscopy (HRTEM) and scanning transmission electron microscopy (STEM) were used to evaluate the SiO2/SiC interface's morphology. According to the energy-dispersive X-ray spectrometry (EDS) results, it was found that phosphorus implantation reduced the accumulation of carbon at the SiO2/SiC interface. Moreover, phosphorus distributed on the SiO2/SiC interface exhibited a Gaussian profile, and the nitrogen concentration at the SiO2/SiC interface may be correlated with the content of phosphorus. This research presents a new approach for increasing the oxidation rate of SiC and reducing the interface state density.

Preparation of high specific surface mPSi/Al2O3/ZnO microcapacitors

In this study, a new concept is explored for an electrolyte-free microcapacitor fabrication based on mesoporous silicon (mPSi) and zinc oxide (ZnO) electrodes, separated by aluminum oxide (Al2O3) as a dielectric layer. For this conception, we gathered various techniques in order to have the best system, namely: •Electrochemical etching to form mPSi.•Aluminum (Al) thin film deposited on mPSi by physical vapor deposition (PVD).•Oxidation of Al in a rapid thermal processing (RTP) furnace heated to 600 °C under pure oxygen gas injection for 300 s.•Coating the ZnO layer on the assembly electrochemically. The designed device was characterized under DC and AC currents with a specific capacitance of 160 nF/cm2 for a DC of 40 nA/cm2, low series resistance (38.7 Ω) and high ohmic resistance (1.69 MΩ). The latest value of Rox indicates a very high ohmic resistance across the Al2O3 dielectric layer. The studied device shows good stability for galvanoplastic charge–discharge cycles exceeding 1200 cycles with an efficiency of about 60%. In AC, the decrease of the capacitance values with a frequency increase indicates the presence of numerous charge traps near the interface of Al2O3 with the electrodes. The conductance measurements demonstrate a high interface state density (Nss) value of 1.6 × 1012 cm−2. The calculated leakage current was about two to three times higher than that obtained in the literature.

ALD growth of ZnO on GaN: Schottky barrier height engineering using ZnO interlayer

Electrical properties of Pt/GaN Schottky diodes have been explored using ZnO interlayers (ILs) grown by thermal atomic layer deposition, which were systematically tuned by varying the growth temperature and thickness of ZnO ILs. For the 20-nm-thick ZnO ILs grown at different temperatures, the growth temperature of 100 °C showed the best rectifying characteristics. The thermionic field emission (TFE) model could explain the forward current characteristics for the growth temperatures of 80, 100 and 150 °C while the tunneling current became dominant for the growth temperature of 200 °C. For the ZnO ILs grown at 100 °C with different thicknesses, the barrier height decreased first and then increased with increasing the ZnO thickness. The samples revealing high interface state density showed the strong tunneling current. It is inferred from the result that both growth temperature and thickness of ZnO IL can be modulated to achieve good Schottky or ohmic contacts for GaN based devices.

Nitrogen Annealing As a Sustainable Method for Interface Trap Passivation in 4H-SiC Mosfets

Silicon Carbide (4H-SiC) has emerged as a leading wide band gap semiconductor for high-power, high-temperature applications1. 4H-SiC metal-oxide semiconductor-field-effect transistors (MOSFETs) have lower power dissipation compared to silicon, allowing for low-noise and high-efficiency all-electric vehicle drives, fast-charging stations, solar inverters, and more. While these devices provide substantial advancements for next-generation energy efficient power systems, 4H-SiC may also offer additional functionality in the form of integrated circuits (ICs) at high temperatures (>300 °C). Because of its high noise immunity and low static power consumption, lateral complementary-metal-oxide-semiconductor (CMOS) IC technology in 4H-SiC is desirable for large-scale integration2. This technology necessitates the use of both n- and p-channel MOSFETs that can operate at high temperatures.Despite the advances of 4H-SiC MOSFETs, the high density of interface states (Dit) at the 4H-SiC/SiO2 interface prevents reaching full potential resulting in high channel resistance and low mobility. Alternatives to nitric oxide (NO) annealing, the most common method adopted to reduce Dit in 4H-SiC3,4, are actively sought due to its toxicity and relatively expensive cost. Annealing in pure nitrogen (N2)5,6 at high temperatures (1400 °C-1600 °C) has been recently demonstrated promising results for 4H-SiC MOSFET processing. In this work, we report Dit measurements consistent with [6] and attempt to correlate the nitrogen areal densities of the near interfacial regions with the Dit for high temperature N2 annealing processes compared to NO. In our study, metal oxide semiconductor capacitors were fabricated on p- and n-type 4H-SiC epitaxial layers. Gate oxides were thermally grown at 1150 °C for 10 h in dry O2 resulting in a ~ 60 nm thick oxide layer. Selected samples are then annealed in flowing N2 at high temperatures (1400 °C, 1 h; 1450 °C, 1 h; and 1500 °C, 30 minutes or 1 h) or NO (1175 °C, 2 h). X-ray photoelectron spectroscopy (XPS), carried out after etching the oxide, indicates that the amount of nitrogen at the interface due to high temperature N2 annealing is ~ 4 × higher than NO annealed devices. Simultaneous high frequency (100 kHz)- low frequency CV was performed to extract interface trap densities (Dit) for each process and compared at room temperature (27 °C) with reference 1175 °C, 2 h NO annealed samples. The comparison reveals that, N2 annealing at 1500 °C for 30 minutes with a flow rate of 3 LPM results in Dit values comparable to NO annealing across the bandgap. Moreover, nitrogen annealing is more effective in reducing Dit near the valence band than NO annealing, while the opposite is true close to the conduction band-edge, consistent with previous reports [6] and observed in atomistic models of these interfaces using the density functional theory7. Nitrogen annealing also decreases the positive fixed charges at the interface of p-type 4H-SiC and SiO2, as evidenced from the flat band voltage comparison. The oxide breakdown voltage for the devices made with 1500 °C N2 annealing was similar to that of NO annealed devices. XPS analysis of the N2 annealed devices, their behavior under high temperature and bias, and their potential to substitute NO will be further discussed.The authors gratefully acknowledge the support from the National Renewable Energy Laboratory/ US Department of Energy sub-contract NREL-AHL-9-92362-01.

The current transport mechanism of Al/Beetroot/Cu used as an organic semiconductor Schottky diode is superior than natural dye-based thin film devices

The development and characterization of an organic thin-film diode based on herbal dyes has been presented. The electronic parameters of the diode are retrieved using a thermionic emission approach from the I-V characteristics. Furthermore, the computed values of ideality factor (n), barrier height (ϕ) and series resistance (Rs) of Al/Beetroot/Cu using the Cheung and Cheung functions are 4.5, 0.73 eV and 1.10 KΩ, respectively. The values of Rs in these two different approaches are very similar, but a discrepancy in values of n confirms the existence of high Rs and high interface state density. The band gap of betanin and temperature dependence of n, ϕ, and Rs confirm the semiconducting behaviour of beet root. We observed a linear relationship between ϕ and 1/n for Al/Beetroot/Cu, confirming that the device is a Schottky diode. The fact that quantum tunneling plays a significant role in the charge conduction procedure with thermionic emission is confirmed by the parabolic conductance of Al/Beetroot/Cu. We have identified that Schottky emission dominates Poole-Frenkle emission for the Al/Beetroot/Cu diode based on both theoretical and experimental values of β. The G(V) vs V plot was used to explain the existence of the reported dye's trapping effect. We also calculated the device's trap energy (Ec), which is substantially lower than previously reported organic diodes. The theoretically estimated value of the insulating temperature for Al/Beetroot/Cu is 133 K. When we utilise beetroot dye instead of indigo dye, the value of n and Rs decreases from 11.65 to 4.5 and 430 KΩ to 1.1 KΩ, respectively, according to the comparison analysis. The trap energy drops from 0.0732 to 0.021 eV once more.

Comparison of electrical characteristics of Schottky junctions based on CdS nanowires and thin film

CdS nanowires and film Schottky diodes are fabricated and diode properties are compared. Effect of SnO2 on CdS film diode properties is investigated. CdS film/Au on 100 nm SnO2 substrate demonstrates like-resistor characteristics and increase in SnO2 thickness corrects resistor behavior, however the effective reverse saturation current density J o is significantly high and shunt resistance are considerably low, implying that SnO2 slightly prevents impurities migration from CdS films into ITO but cause additional issues. Thickness of CdS film on diode properties is further investigated and increasing CdS film thickness improved J o by one order of magnitude, however shunt resistance is obviously low, suggesting intrinsic issues in CdS film. 100 nm CdS nanowire/Au diodes reduce J o by three orders of magnitude in the dark and two orders of magnitude in the light respectively and their shunt resistance is significantly enhanced by 70 times when comparing with those of the CdS film diodes. The wide difference can be attributed to the fact that CdS nanowires overcome intrinsic issues in CdS film and thus demonstrate significantly well- defined diode behavior. Simulation found that CdS nanowire diodes have low compensating acceptor type traps and interface state density of 5.0 × 109 cm−2, indicating that interface recombination is not a dominated current transport mechanism in the nanowire diodes. CdS film diodes are simulated with acceptor traps and interface state density increased by two order of magnitude and shunt resistance reduced by one order of magnitude, indicating that high density of interface states and shunt paths occur in the CdS film diodes.

Impact of oxide/4H-SiC interface state density on field-effect mobility of counter-doped n-channel 4H-SiC MOSFETs

We investigated the effect of interface state density on the field-effect mobility (μ FE) of 4H-SiC counter-doped metal-oxide-semiconductor field-effect transistors (MOSFETs). We fabricated counter-doped MOSFETs with three types of gate oxides i.e. SiO2, Al2O3 formed via atomic layer deposition, and Al2O3 formed via metal layer oxidation (MLO). A maximum μ FE of 80 cm2 V−1 s−1 was obtained for the MLO-Al2O3 FET, which was 60% larger than that of the SiO2 FET. In addition, we evaluated the electron mobility in the neutral channel (μ neutral) and the rate of increase in the free electron density in the neutral channel with respect to the gate voltage (dN neutral/dV G), which are factors determining μ FE. μ neutral depended only on the channel depth, independent of the type of gate oxide. In addition, dN neutral/dV G was significantly low in the SiO2 FET because of carrier trapping at the high density of interface states, whereas this effect was smaller in the Al2O3 FETs.

Selective hydrogenation improves interface properties of high-k dielectrics on 2D semiconductors

The integration of high-k dielectrics with two-dimensional (2D) semiconductors is a critical step towards high-performance nanoelectronics, which however remains challenging due to the high density of interface states and the damage to the monolayer 2D semiconductors. In this study, we propose a selective hydrogenation strategy to improve the interface properties while the 2D semiconductors are not affected. Using the interface of monolayer molybdenum disulfide (MoS2) and silicon nitride as an example, we show substantially improved interface properties for electronic applications after the interfacial hydrogenation, as evidenced by reduced inhomogeneous charge redistribution, increased band offset, and nearly intact electronic properties of MoS2. Importantly, this hydrogenation process selectively occurs only at the silicon nitride surface and is compatible with the current semiconductor fabrication process. We further show that this strategy is general and applicable to other interfaces between high-k dielectrics and 2D semiconductors such as hafnium dioxide (HfO2) on the monolayer MoS2. Our results demonstrate a simple yet viable way to improve the integration of high-k dielectrics on a broad range of 2D transition metal disulfide semiconductors, shedding light on practical electronic and optoelectronic applications.

Observation and Suppression of Stacking Interface States in Sandwich-Structured Quantum Dot Light-Emitting Diodes.

Interfacial quality of functional layers plays an important role in the carrier transport of sandwich-structured devices. Although the suppression of interface states is crucial to the overall device performance, our understanding on their formation and annihilation mechanism via direct characterization is still quite limited. Here, we present a thorough study on the interface states present in the electron transport layer (ETL) of blue quantum dot (QD) light-emitting diodes (QLEDs). A ZnO/ZnMgO bilayer ETL is adopted to enhance the electron injection into blue QDs. By probing the ETL band structure with photoelectron spectroscopy, we discover that substantial band bending exists at the ZnO/ZnMgO interface, elucidating the presence of a high density of interface states which hinder electron transport. By inserting a ZnO@ZMO interlayer composed of mixed ZnO and ZnMgO nanoparticles, the band bending and thus the interface states are observed to reduce significantly. We attribute this to the hybrid surface properties of ZnO@ZMO, which can annihilate the surface states of both the ZnO and ZnMgO layers. The introduction of a bridging layer has led to ∼40% enhancement in the power efficiency of blue QLEDs and noticeable performance boosts in green and red QLEDs. The findings here demonstrate a direct observation of interface states via detailed band structure studies and outline a potential pathway for eliminating these states for better performances in sandwich-structured devices.

Experimental Study on Static and Dynamic Characteristics of Ga2O3 Schottky Barrier Diodes With Compound Termination

In this letter, the ultrafast reverse recovery <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">β</i> -Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> Schottky barrier diode (SBD) with improved breakdown voltage is proposed and investigated experimentally. It features the compound termination, consisting of air space field plate and thermal oxidation terminal. The compound termination not only reduces high-density interface states at the dielectric/Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> interface and the electron concentration in the oxidation terminal, but also modulates the electric-field distribution and suppresses the peak electric-field at the bottom of anode. Therefore, the reverse leakage current is suppressed as well as the reverse recovery and breakdown characteristics are improved effectively. The Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> SBDs with the diameter of 1000 μm obtain ultrashort reverse recovery time of 7.5 ns and ultralow reverse recovery charge of 1.0 nC at <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">di</i> / <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dt</i> = 50 A/μs with its breakdown voltage up to 400 V, maintaining good rectification characteristics. The temperature-dependences of both forward conduction and reverse recovery characteristics are discussed in temperature range from 300 to 500 K. The results prove that the superior electronics performance of the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">β</i> -Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> SBDs with good electronics thermal tolerance can overcome the low thermal conductivity of <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">β</i> -Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> to a certain extent. The fabricated <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">β</i> -Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> SBDs have great potential for high power and high-frequency applications.

Probing the surface potential of SiO2/4H-SiC(0001) by terahertz emission spectroscopy

Terahertz (THz) emission spectroscopy (TES) was used to evaluate the properties of interfaces between thermally grown oxides and 4H-SiC(0001) substrates. Metal–oxide–semiconductor (MOS) structures with transparent electrodes were irradiated with a femtosecond laser pulse and the emitted THz signal was measured by changing the applied gate voltage. The amplitude of the THz pulse signal is dependent on the electric field, namely, band bending near the SiO2/SiC interfaces, and thus contains information on the change in the surface potential of the SiC MOS structures. We compared the peak THz amplitude (ETHz) and gate voltage (Vg) curves taken from SiC MOS structures with different interface qualities and observed a steep ETHz–Vg curve for a high-quality SiO2/SiC interface as compared with the curve for a structure with a higher interface state density. We also compared the ETHz–Vg and capacitance–voltage characteristics of SiC MOS capacitors and investigated the mechanism of THz emission from the SiC MOS structures to validate the ability of the TES technique for characterizing SiO2/SiC interfaces.

A Study on Solution-Processed Y2O3 Films Modified by Atomic Layer Deposition Al2O3 as Dielectrics in ZnO Thin Film Transistor

In this work, Y2O3–Al2O3 dielectrics were prepared and used in ZnO thin film transistor as gate insulators. The Y2O3 film prepared by the sol–gel method has many surface defects, resulting in a high density of interface states with the active layer in TFT, which then leads to poor stability of the devices. We modified it by atomic layer deposition (ALD) technology that deposited a thin Al2O3 film on the surface of a Y2O3 dielectric layer, and finally fabricated a TFT device with ZnO as the active layer by ALD. The electrical performance and bias stability of the ZnO TFT with a Y2O3–Al2O3 laminated dielectric layer were greatly improved, the subthreshold swing was reduced from 147 to 88 mV/decade, the on/off-state current ratio was increased from 4.24 × 106 to 4.16 × 108, and the threshold voltage shift was reduced from 1.4 to 0.7 V after a 5-V gate was is applied for 800 s.

Operation and performance of the 4H-SiC junctionless FinFET

This work presents a comprehensive study on the behaviour and operation of a vertical 1.2 kV 4H-SiC junctionless power FinFET. The increased bulk conduction in the channel of this topology may bring reductions in the channel resistance compared to trench MOSFETs, whose performance is limited by the high interface state density. For this purpose, finite element (FE) simulations are used to examine the operation of this device. It is hence demonstrated that the junctionless FinFET can attain a high average channel drift mobility well above 100 cm2/(Vs), leaving the resistance to be determined by the drift and substrate regions. This allows the FinFET to turn on and reach its steady state current using a much (> 3x) smaller gate overdrive than standard designs. On the other hand, however, the overly high field in the gate oxide, the lack of an efficient mechanism for hole extraction, and the low threshold voltage can cause significant reliability issues. Furthermore, it is shown that the high input capacitance of the FinFET can limit its switching speed to slower levels than in standard trench MOSFETs, which raises the need for further development of the original design proposed for vertical GaN devices. In this context, it is demonstrated that the addition of a p-shield below the trenches can alleviate the off-state reliability issues and increase the speed, while still maintaining a competitive R on ∼ 2mΩ cm2 even without the use of n-JFET enhancement doping.

Dimensionality-Reduced Fermi Level Pinning in Coplanar 2D Heterojunctions.

Electronic transport through a metal|semiconductor (M|S) heterojunction is largely determined by its Schottky barrier. In 3D M|S junctions, the barrier height determines the turn-on voltage and is often pinned by the interface states, causing Fermi level pinning (FLP). The pinning strength in 3D depends on the ratio Ci/CM between the interface quantum capacitance Ci and the metal surface capacitance CM. In 2D, the interface dipole does not influence the band alignment, but still affects the Schottky barrier and transport. In light of the general interest in building 2D electronics, in this work we discover the relevant material parameters which dictate the behavior and strength of FLP in 2D M|S contacts. Using a multiscale model combining first-principles, continuum electrostatics, and transport calculations, we study a realistic Gr|MoS2 interface as an example with high interface state density (Ci/CM ≫ 1). Transport calculations show partial pinning with a strength P ∼ 0.6, while a 3D junction with similar heterogeneity gives full pinning with P = 1 as expected. We further show that in 2D M|S contacts the turn-on voltage and pinning strength are affected by a physical parameter l/λD, the ratio between the interface width l, and the thermal de Broglie wavelength λD. Pinning is absent for ideal line-contacts (l/λD = 0), but increases for realistic l/λD values.

Short-Channel Effects in SiC MOSFETs Based on Analyses of Saturation Drain Current

In this brief, the minimum channel length (the channel length at which short-channel effects (SCEs) begin to occur) in SiC MOSFETs was experimentally determined. We fabricated 4H-SiC MOSFETs with various channel lengths and acceptor concentrations and analyzed their electrical characteristics. We propose a method for determining the minimum channel length in silicon carbide (SiC) MOSFETs, focusing on the increased rate of the drain current in the saturation region, and define the minimum channel length for the fabricated SiC MOSFETs with various acceptor concentrations in the p-body region. The relationship between the minimum channel length and the acceptor concentration for these SiC MOSFETs shows a similar tendency to that for Si MOSFETs. The obtained minimum channel lengths in the SiC MOSFETs are slightly longer than those in Si MOSFETs, which is caused by the larger built-in potential of SiC compared to that of Si and the existence of a high density of interface states, which enhance the SCEs. This work provides guidelines for the design of SiC MOSFETs that utilize very short-channel structures.

Electrical Properties of Ultra-Thin Body (111) Ge-On-Insulator n-Channel MOSFETs Fabricated by Smart-Cut Process

We have systematically examined electrical characteristics of ultra-thin body (UTB) (111) Ge-on-insulator (GOI) n-channel metal-oxide-semiconductor field-effect transistors (nMOSFETs) fabricated by the smart-cut process and have compared their electrical properties with those of (100) ones. The (111) GOI thickness was varied from 29.4 to 7.3 nm. The normal MOSFET operation of a 7.3 nm-thick (111)-oriented GOI nMOSFET has been demonstrated with a reasonable ON/OFF ratio of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> . However, degradation in the effective electron mobility and subthreshold swing (SS) of the (111) GOI nMOSFETs with decreasing the GOI thickness ( T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GOI</sub> ) was observed. Raman analyses and electrical characteristics of GOI nMOSFET under back-gate operation has suggested that a high interface state density at (111) GOI/buried oxide interfaces as well as low GOI film quality near the back interfaces can be an origin of this degradation of the electrical properties with thin body channels.

Characteristics and mechanisms of subthreshold voltage hysteresis in 4H-SiC MOSFETs* *Project supported by the National Key Research and Development Program of China (Grant No. 2017YFB0903203), the National Natural Science Foundation of China (Grant No. 62004033), and China Postdoctoral Science Foundation (Grant No. 2020M683287).

In order to investigate the characteristics and mechanisms of subthreshold voltage hysteresis (ΔV th,sub) of 4H-SiC metal–oxide–semiconductor field-effect transistors (MOSFETs), 4H-SiC planar and trench MOSFETs and corresponding P-type planar and trench metal–oxide-semiconductor (MOS) capacitors are fabricated and characterized. Compared with planar MOSFEF, the trench MOSFET shows hardly larger ΔV th,sub in wide temperature range from 25 °C to 300 °C. When operating temperature range is from 25 °C to 300 °C, the off-state negative V gs of planar and trench MOSFETs should be safely above –4 V and –2 V, respectively, to alleviate the effect of ΔV th,sub on the normal operation. With the help of P-type planar and trench MOS capacitors, it is confirmed that the obvious ΔV th,sub of 4H-SiC MOSFET originates from the high density of the hole interface traps between intrinsic Fermi energy level (E i) and valence band (E v). The maximum ΔV th,sub of trench MOSFET is about twelve times larger than that of planar MOSFET, owing to higher density of interface states (D it) between E i and E v. These research results will be very helpful for the application of 4H-SiC MOSFET and the improvement of ΔV th,sub of 4H-SiC MOSFET, especially in 4H-SiC trench MOSFET.