High Density Interconnect Technology Research Articles

Challenges in introducing high-density interconnect technology in printed circuit boards for space applications

Challenges in introducing high-density interconnect technology in printed circuit boards for space applications

Effects of surface diffusion and solder volume on porous-type Cu3Sn in Cu/Sn/Cu microjoints

High-density interconnection technology is critical for semiconductor packages, which require high speed and multifunctional demands. The shrinkage of solder volume is needed for the miniaturization of devices. Fewer studies investigate using Cu3Sn than Cu6Sn5 in large solder joints. However, Cu3Sn has a significant and critical effect on microjoints. Cu6Sn5 can transform completely to Cu3Sn, which may cause unexpected problems in microjoints. The interfacial reactions in large and small solder joints are different. Porous-type Cu3Sn is an unusual structure at the interface. In this study, we utilize the transient liquid-phase bonding (TLP) process on microbumps to drive the transformation of Cu6Sn5 to Cu3Sn. Porous-type Cu3Sn is loose and unfavorable for joint strength. High-temperature bonding, microbumps and flux residues induce porous structure formation.

High-Density Interconnect Technology Assessment of Printed Circuit Boards for Space Applications

Abstract High-density interconnect (HDI) printed circuit boards (PCBs) and associated assemblies are essential to allow space projects to benefit from the ever increasing complexity and functionality of modern integrated circuits such as field-programmable gate arrays, digital signal processors and application processors. Increasing demands for functionality translate into higher signal speeds combined with an increasing number of input/outputs (I/Os). To limit the overall package size, the contact pad pitch of the components is reduced. The combination of a high number of I/Os with a reduced pitch places additional demands onto the PCB, requiring the use of laser-drilled microvias, high-aspect ratio core vias, and small track width and spacing. Although the associated advanced manufacturing processes have been widely used in commercial, automotive, medical, and military applications, reconciling these advancements in capability with the reliability requirements for space remains a challenge. Two categories of the HDI technology are considered: two levels of staggered microvias (basic HDI) and (up to) three levels of stacked microvias (complex HDI). In this article, the qualification of the basic HDI technology in accordance with ECSS-Q-ST-70-60C is described. At 1.0-mm pitch, the technology passes all testing successfully. At .8-mm pitch, failures are encountered during interconnection stress testing and conductive anodic filament testing. These failures provide the basis for updating the design rules for HDI PCBs.

Thin Film Characterization on Cu/SnAg Solder Interface for 3D Packaging Technologies

Copper is a commonly used interconnect metal in microelectronic interconnects due to its exceptional electrical and thermal properties. Particularly in applications of the 2.5 and 3D integration, Cu is utilized in through-silicon-vias (TSVs) and flip chip interconnects between microelectronic chips for providing miniaturization, lower power and higher performance than current 2D packaging approaches. SnAg capped Cu pillars are a common high-density interconnect technology for flip chip bonding. For these interconnects, specific properties of the Cu surface, such as roughness and cleanliness, are an important factor in the process to ensure quality solder bumps. During electroplating, tight processing parameters must be met so that defects are avoided, and high bump uniformity is achieved. An understanding of the interactions at the solder and Cu pillar interface is needed, based on the electroplating parameters, to determine the best method for populating solder on the wafer surface. In this study, surface treatment techniques such as oxygen plasma cleaning were performed on the Cu surfaces and the SnAg plating chemistry for depositing the solder were evaluated through hull cell testing to qualitatively determine the range of current densities to investigate. It was observed that current density while plating played a large role in solder bump deposition morphology. At the higher current densities greater than 60 mA/cm2, bump height non-uniformity and dendritic growth are observed and at lower current densities, less than or equal to 60 mA/cm2, uniform, continuous bump height occurred.

Embedded Multidie Interconnect Bridge—A Localized, High-Density Multichip Packaging Interconnect

This article provides an overview of the embedded multidie interconnect bridge (EMIB) multichip packaging (MCP) technology. EMIB is a unique packaging paradigm that provides very high-density interconnects (currently in the range of 500–1000 I/O/mm) localized in between two devices, thus enabling high-bandwidth (BW) on-package links while leaving the rest of the package structures and designs unaffected. The construction of the silicon bridge and the package to allow high BW electrical signaling between two dies is discussed in detail. Examples of the EMIB implementations for the links between the field-programmable gate array (FPGA) logic and high bandwidth memory generation 2 (HBM2) memory stacks, graphics die and HBM2 memory stacks, FPGA logic die, and high-performance transceiver die are described. EMIB packaging is compared with similar high-density interconnect technologies such as silicon interposer with through-silicon vias (TSVs) and other fan-out-based package technologies. Design optimization strategies for power delivery and I/O routing in the presence of an embedded bridge are highlighted.

Novel high-density interconnection technology for the CBM Silicon Tracking System

In the Silicon Tracking System of the Compressed Baryonic Matter experiment at the future accelerator facility FAIR, double-sided microstrip sensors with sizes up to 62 x 124 mm will be connected to the readout electronics by means of up to 50 cm long lightweight microcables. The well-established aluminum to aluminum TAB bonding technology between die and microcable is highly manual and time-consuming. Therefore, a novel high-density interconnection technology based on a copper-polyimide flex microcable has been developed. It combines gold stud bumping on the die with solder paste printing on the microcable and a flip chip interconnection process. Shear strength and cross-section analysis have been performed on the bonded structures to optimize the solder paste reflow as well as the flip chip bonding process. First underfill application studies have been conducted successfully.

Electron backscatter diffraction characterization of electrolytic Cu deposition in the blind-hole structure: Current density effect

Blind-hole (BH) filling via direct-current Cu electrodeposition is widely used in high-density interconnection technology for advanced printed circuit boards (PCBs). In this study, electrolytic Cu BH fillings deposited at various current densities (j=2, 4, 5, and 6A/dm2) were investigated using transmission X-ray microscopy (TXM), field-emission scanning electron microscopy (FE-SEM), and electron backscatter diffraction (EBSD). The TXM, FE-SEM, and EBSD investigations indicated that the Cu deposition morphology (e.g., void formation and concave surface Cu) and its crystallographic microstructure (e.g., orientation and twin structure) were strongly dependent on j. The formation of voids and concave surface Cu in the BH fillings inevitably degraded the thermomechanical and electrical characteristics of the Cu deposition, deteriorating the reliability of PCB Cu interconnection. These dependencies revealed that j is an important factor of the Cu electrodeposition in the BH structure and should be reduced to a level of j<4A/dm2 to avoid the undesired microstructures. This knowledge serves to advance the understanding of the role of the current density in the Cu BH filling process.

Electron backscatter diffraction characterization of blind hole fillings by electrolytic Cu deposition

Blind hole (BH) filling by electrolytic Cu deposition is widely used in high density interconnection technology for printed circuit boards. In this study, we investigated Cu deposition behavior in a BH structure using optical microscopy and field-emission scanning electron microscopy in combination with electron backscatter diffraction (EBSD). According to the deposition morphology/rate, the BH filling process was divided into three distinct regimes: (1) the initial deposition regime (t=20–25min), (2) the bottom up deposition regime (t=25–35min), and (3) the final deposition regime (t=35–80min). EBSD analyses showed that the Cu grains were predominantly in the [111]||TD (TD: transverse direction) orientation in the first regime. The [111] Cu grains were predominantly oriented with a takeoff angle of ~20° in the bottom up deposition regime. In the final deposition regime, the [111]||RD (RD: rolling direction) and [101]||RD orientations became dominant in the BH fillings. In addition, we characterized the grain boundaries in the Cu deposits with respect to t. The microstructural/crystallographic information presented in this study will improve the understanding of how the electrolytic Cu filling process occurs in a BH structure.

Z-Interconnect Technology - A Reliable, Cost Efficient Solution for High Density, High Performance Electronic Packaging

Common themes across all segments of electronic packaging today are density and performance. High density interconnect (HDI) technology is one of the most commonly utilized methods for electronic package density improvement, while many different areas have been investigated for performance improvement, from low loss dielectric and conductor materials, to via design and via stub reduction. Electrical performance and density requirements are sometimes complementary, but often times, conflicting with one another. This paper will describe the design, materials, fabrication, and reliability of a new Z-Interconnect technology that addresses both high density and high performance demands simultaneously. Z-Interconnect technology uses an electrically conductive adhesive to electrically interconnect several cores (Full Z) or sub-composites (Sub Z) in a single lamination process. Z-Interconnect technology will be compared and contrasted to other commonly used solutions to the performance and density challenges. HDI or sequential build-up technology is a pervasive solution to the density demands in semiconductor packaging and consumer electronics (e.g. Smart phones), but has not caught hold in HPC or A&amp;D printed wiring board (PWB) applications. One solution for PWB electrical performance enhancement is plated through hole (PTH) stub reduction by “back drilling” the unwanted portion of the PTH. Pb-free reflow and Current Induced Thermal Cycling (CITC) test results of product coupons and specially designed test vehicles, having component pitches down to 0.4mm, will be presented. Z-Interconnect test vehicles have survived 6X Pb-free (260C) reflow cycles, followed by greater than 3000 cycles of 23C–150C CITC cycles. Test vehicle and product coupons also easily survive 10 or more 23C–260C CITC cycles.

Electron backscatter diffraction analysis on the microstructures of electrolytic Cu deposition in the through hole filling process: Butterfly deposition mode

Electrolytic Cu deposits in a through hole (TH) structure are a critical reliability issue for the high density interconnection (HDI) technologies of three-dimensional packaging. In this study, we investigated the butterfly deposition of electrolytic Cu fillings via optical microscopy (OM) and field-emission scanning electron microscopy (FE-SEM) in combination with electron backscatter diffraction (EBSD). The Cu TH filling proceeds through three distinct regimes relative to the plating time (t): (1) the conformal deposition regime (t=30–40min), (2) fast deposition regime (t=40–55min), and (3) final deposition regime (t=55–110min). The EBSD analyses showed that the Cu grains were predominantly oriented with [111]‖TD (TD: transverse direction) in the conformal and fast deposition regimes; however, the [111]‖RD (RD: rolling direction) orientation became dominant in the final deposition regime. Additionally, a large number of high angle grain boundaries (HAGBs) with strong coincidence site lattices (CSLs) existed at Σ3 (60° rotation at 〈111〉) and Σ9 (38.9° rotation at 〈101〉) in the Cu fillings. The microstructural/crystallographic evolutions of the butterfly and other deposition modes (i.e., dogbonding) were compared.

Electron backscatter diffraction analysis on the microstructures of electrolytic Cu deposition in the through hole filling process

Through hole (TH) filling by electrolytic Cu deposition has become a critical process for high density interconnection technologies associated with three-dimensional packaging. In this study, the morphological and crystallographic evolutions of the electrolytic Cu TH filling with the plating time (t) were investigated using an optical microscope and a field-emission scanning electron microscope equipped with an electron backscatter diffraction (EBSD) analysis system. The Cu deposition rate in the TH was strongly dependent on t, which was established at a moderate rate of ~0.3μm/min at t=40min–74min, then dramatically accelerated to ~4μm/min at t=74min–80min (termed “fast deposition regime”), and subsequently decelerated in the final plating regime (t=80min–100min). EBSD analyses showed that the electrolytic Cu predominantly possessed high-angle grain boundaries with strong coincidence site lattices at ∑3 (60° rotation at <111>) and ∑9 (38.9° rotation at <101>) for all t examined. Interestingly, the [111]‖TD (transverse direction) orientation displayed a relatively strong presence in the initial induction regime, while the [111]‖TD+[101]‖TD orientations with large grain sizes became dominant in the fast deposition regime (i.e., t=74min–80min), and there was a very low concentration of the [111]‖TD orientation in the final deposition regime. This research offered a better understanding of the morphological and crystallographic evolutions in each stage of the electrolytic Cu TH filling.

A PDMS-Based Integrated Stretchable Microelectrode Array (isMEA) for Neural and Muscular Surface Interfacing

Numerous applications in neuroscience research and neural prosthetics, such as electrocorticogram (ECoG) recording and retinal prosthesis, involve electrical interactions with soft excitable tissues using a surface recording and/or stimulation approach. These applications require an interface that is capable of setting up high-throughput communications between the electrical circuit and the excitable tissue and that can dynamically conform to the shape of the soft tissue. Being a compliant material with mechanical impedance close to that of soft tissues, polydimethylsiloxane (PDMS) offers excellent potential as a substrate material for such neural interfaces. This paper describes an integrated technology for fabrication of PDMS-based stretchable microelectrode arrays (MEAs). Specifically, as an integral part of the fabrication process, a stretchable MEA is directly fabricated with a rigid substrate, such as a thin printed circuit board (PCB), through an innovative bonding technology-via-bonding-for integrated packaging. This integrated strategy overcomes the conventional challenge of high-density packaging for this type of stretchable electronics. Combined with a high-density interconnect technology developed previously, this stretchable MEA technology facilitates a high-resolution, high-density integrated system solution for neural and muscular surface interfacing. In this paper, this PDMS-based integrated stretchable MEA (isMEA) technology is demonstrated by an example design that packages a stretchable MEA with a small PCB. The resulting isMEA is assessed for its biocompatibility, surface conformability, electrode impedance spectrum, and capability to record muscle fiber activity when applied epimysially.

The effect of joint size on the creep properties of microscale lead-free solder joints at elevated temperatures

Solder joints in electronic packaging systems are becoming smaller and smaller to meet the miniaturization requirements of electronic products and high density interconnect technology. Furthermore, many properties of the real solder joints at the microscale level are obviously different from that of bulk solder materials. Creep, as one of the key mechanical properties at elevated temperatures, can impair the reliability of miniature solder joints in electronic devices. However, there is a lack of knowledge about the comparative creep properties of microscale solder joints of different sizes. Most previous studies have focused on the creep properties of bulk solder materials or solder joints of the same size. In this research, to determine whether a size effect exists for creep properties of solder joints or not, we characterized the creep behaviors of Sn–3.0Ag–0.5Cu lead-free solder joints under tensile loading modes using microscale butt-joint specimens with a copper-wire/solder/copper-wire sandwich structure with two different sizes. Also, the creep failure mechanisms were investigated. Experimental results show that the creep activation energy and creep stress exponent are very similar for both sizes of solder joint. However, under the same testing conditions, the joints with a larger size exhibit a much higher steady-state creep rate and a shorter creep lifetime than the smaller joints.

Fine-Pitch UBM Pad Metallization and Flip-Chip Assembly for Plane Arrays Interconnection

We have developed and successfully obtained stable and reliable processes in our labs for metallization and pad definition of passivated Si substrates for microelectronic flip-chip assembly with solder bumps, applicable to high-density interconnection technology. Patterned samples were prepared with aluminum pads on Si/SiO2 over which the UBM multilayer metals were deposited. Pads are 90x90micron^2 with 185micron pitch. All metal layers show good stability and adherence, and the final processes have good reproducibility and stability. A flip-chip assembly using solder micro-bumps deposited over the pads was used to demonstrate stability and reliability of the process. This set of processes - metallization, pad definition and flip-chip assembly - will next be applied to functional devices.

Impact of Printed Circuit Board Via and Micro-Via Structures on Component Thermal Performances

Latest electronic component package types are pushing the need to more efficiently remove the dissipated heat using optimized thermal paths going through the printed circuit board (PCB) to reach PCB inner thermal planes. So, to optimize board cooling, the designer has more and more to deal with PCB architecture including high density interconnect (HDI) technology, which relies on small diameter laser drilled micro-vias. Compared with conventional PCB technologies, HDI creates denser interconnect substrates, containing multilevel micro-via structures that play a decisive role in the miniaturization of circuit boards but will exacerbate the component cooling design complexity. To improve the understanding of conventional and future configurations of via structure and their influence on the component thermal performances, a study was leaded on an micro lead frame package, which is now mainstream for both analog and digital functions. For still air conditions, the thermal simulation results show that via and micro-via structures allow to drain more than 90% of the component power through the PCB metallic planes and are mandatory to limit the temperature excess. Thus, the thermal modeling of the latest 3D Integrated Circuit is reinforcing the need to simulate in more thin details its board surrounding architecture as well as its packaging. However, a fine detailed modeling of board layers layout always exceeds the simulation tool capabilities and requires new modeling methodologies able to define the most significant thermal model. Based on DEvelopment of Libraries of PHysIcal models (DELPHI) methodology, the creation of a compact thermal model, compliant to a set of boundary conditions was investigated for a local board area. The thermal behavior prediction, found to be within ± 5% of error, demonstrates the feasibility of extending the boundary condition independence principle to board modeling in order to achieve a more efficient and accurate board cooling optimization.

RF‐MEMS switches on a printed circuit board platform

PurposeThe purpose of this paper is to present a new class of printed circuit board (PCB)‐based, radio frequency micro‐electro‐mechanical systems (RF‐MEMS) switches and to describe the packaging method and evaluate performance.Design/methodology/approachTraditional PCB materials and processes were combined with photolithographic high‐density interconnect (HDI) and MEMS to form 3D high‐performance RF switches.FindingsA new type of MEMS RF switch has been developed on a PCB platform. Using processes analogous to those used for silicon MEMS, PCB, and HDI technologies were utilized to fabricate these 3D structures. The PCB‐based microstructures are “mil‐scale” rather than the “micro‐scale” of silicon MEMs. A co‐fabrication packaging method for the MEMS RF switch was also developed. The PCB‐based MEMS switches have demonstrated excellent RF performance and “hot‐switching” RF power‐handling capability. PCB‐based MEMS RF switches have the advantages of low cost and amenability to scale‐up for a high degree of integration.Research limitations/implicationsFurther development on photo imageable dielectric materials will enable this technology to improve yield and processability.Originality/valueThe paper describes the development of PCB‐based MEMS RF switches. These elements will enable new applications and enhance the functionality of PCBs. They are also more amenable to system integration compared with silicon MEMS.

High Directivity Couplers using Multilayer Organics (MLO)

This paper presents the design and fabrication of a stand-alone high directivity coupler using high dielectric constant multilayer organic (MLO) technology. MLO is a low cost high density interconnect technology that allows for the realization of high Q and low loss inductor and capacitor elements that allow for the miniaturization of RF and mixed signal circuits. Q values above 300 have been measured for MLO with costs being lower than both LTCC and TFOS technologies. Low-loss lumped and distributed elements were realized using a novel multilayer build up process that supports both land grid array (LGA) and edge terminations. The couplers which support frequencies between 700 MHz and 2GHz exhibit coupling coefficients above 20db and isolation greater than 40db. The couplers can be combined with low pass harmonic filters in the same technology.

Reliability testing for microvias in printed wire boards

PurposeThe purpose of this paper is to identify and expand upon the understanding of the reliability of high density interconnect (HDI) technologies containing multi‐level microvia interconnections with 2, 3 or 4 stacked and staggered configured structures.Design/methodology/approachMicrovia testing was performed with interconnect stress testing (IST) using a modified methodology documented in the IPC test methods manual TM650, Method 2.6.26, titled DC current induced thermal cycle test. The IST coupon designs utilize mathematical modeling, in combination with prior experience in the fields of printed wiring board (PWB) processing, chemistry, materials and statistics, to improve the sensitivity of testing.FindingsSingle and 2 stack microvias are generally the most robust type of copper interconnection used in HDI applications, 3 stack and 4 stack require greater discipline to assure product reliability. Ranking the inherent reliability of 3 stack and 4 stack structures to other interconnects like plated through holes, blind, or buried vias, may need to be reconsidered in future reliability test programs.Research limitations/implicationsThis work was focused on the reliability of bare board and does not address failure modes associated with the additional stresses applied to the microvia structures created by the devices and their associated solder joints formed during surface mount assembly and rework operations.Originality/valueThis paper was written to improve the understanding of various aspects of design and their influence on reliability for stacked and staggered microvia structures. The design function must understand the physical construction as a critical influence on microvia reliability that should be taken into consideration in parallel with the electrical requirements.

The process and pastes for the via hole plugging of HDI PCBs

PurposeThe purpose of this paper is to present the materials and process considerations and solutions that enable the safe use of plugging pastes in high density interconnection (HDI) printed circuit boards (PCBs) designed to operate at higher temperatures.Design/methodology/approachThe paper introduces the concept of microvia plugging and the issues that are important in influencing HDI PCB reliability. Plugging pastes and their properties are discussed along with the various plugging processes that can be used. The advantages and disadvantages of each type of process are compared and contrasted.FindingsThe creation of via holes and the filling of these interconnection holes or buried vias and their subsequent copper plating is one of the key processes in HDI technology. In future, the importance of plugging will increase, particularly on account of the growing demand for copper plating and dimensional stability.Research limitations/implicationsThe paper highlights the importance of making the correct selection of materials and processing methodologies and details the implications of these choices.Originality/valueThe paper describes the different approaches that can be used for filling microvias and details the issues, advantages and disadvantages of the various approaches. The paper particularly focuses on the special demands on plugging pastes used in higher temperature range applications.

Optimal chip-package codesign for high-performance DSP

In high-performance DSP systems, the memory bandwidth can be improved using high-density interconnect technology and appropriate memory mapping. High-density MCM and flip-chip solder bump technology is used to achieve a system with an I/O bandwidth of 100 Gb/s/cm2 die. The use of DRAMs in these systems usually make the performance of these systems poor, and some algorithms make it difficult to fully utilize the available memory bandwidth. This paper presents the design of a fast Fourier transform (FFT) engine that gives SRAM-like performance in a DRAM-based system. It uses almost 100% of the available burst-mode memory bandwidth. This FFT engine can compute a million-point FFT in 1.31 ms at a sustained computation rate of 8.64 /spl times/ 10/sup 10/ floating-point operations per second (FLOPS). This is at least an order of magnitude better than conventional systems.