High Density Interconnect Substrate Research Articles

Effect of Ni Addtion on Electroless Cu for High Density Interconnect PCB Substrate

Introduction Nowadays, high-density interconnect (HDI) printed circuit board (PCB) substrates have been widely applied to high-end electronics to meet the increasing input and output (I/O) density and small footprint area. Micro-via, a tiny structure buried among build-up layers that provide electrical interconnection is a key component in the HDI substrate. However, the preparation of micro-via is facing new challenges. It is not only required that the size of the micro-via scales down to meet the increased interconnect density, but also that the micro-via should withstand severe operating conditions in different scenarios. Therefore, it is of great importance to improve the quality of micro-vias during processing and manufacturing. The micro-via structure is a sandwich structure that is processed by electroless Cu plating and Cu electrolyte plating sequentially, and thus the quality of the electroless Cu layer can significantly affect the reliability of micro-via. In this work, we mainly focused on the electroless Cu plating process and investigated the effect of the electroless Cu deposition speed on the quality of the micro-via structure. SIM and HR-TEM characterizations were employed to investigate the micro-structure inside the electroless Cu layer. Materials and Method In this study, we used the common alkaline ion catalyst method to prepare the electroless Cu layer. The electroless Cu plating and electrolyte Cu plating was conducted on a PCB Resin Coated Copper (RCC) substrate that was cleaned by soft etching in an acid condition. The surface is then pre-dipped in an anionic solution, and palladium ions were adsorbed using an alkaline ion catalyst. The electroless Cu processes adopted in a reaction bath that consists of Cu resource (CuSO4·5H2O), complexing agent (KNaC4H4O6·4H2O) and reductant (HCHO). The whole reaction was conducted in the alkaline condition with a PH of 12.5, and the thickness of the electroless Cu deposition was controlled at around 0.20 µm. NiSO4 is selected as the Ni precursor to alter the Ni concentration in the reation bath. The contents of Ni addition were selected as 50 %, 100 %, 200 % and 300% of a conventional process at a bath temperature of 27 ºC. The thickness of the plated Cu layer was measured by a gravimetric method. Results and discussion TEM observation was used to identify the structure at the interface. Fig. 1 shows the TEM observation of the sample with 50 % and 200 % Ni concentrate. There are some nanovoids found at the interface between the Cu substrate and electroless Cu, which is arguably due to hydrogen generated during electroless Cu plating. The sample with a higher reaction speed has more nanovoids. It can be due to that the higher reaction speed can generate more hydrogen bubbles in the bath that can attach to the electroless Cu layer, leading to nanovoids as shown in Fig. 1. The samples prepared at different bath temperatures are under investigation to illustrate that the reaction speed can significantly affect the Cu electroless layer quality. Conclusions In this work, we investigated the Ni effect in electroless Cu on the RCC substrate. It is found that the higher Ni incorporation can lead to massive nanovoids generation and fine Cu grains in the electroless layer, which is a potential risk for the reliability of the HDI substrate. By reducing the Ni incorporation content, the number of nanovoids can be effectively reduced. Figure 1

Large Scale Photodesmear for Via Residue Cleaning in High Density Interconnect substrates

Smear residue from the build-up dielectric material is left at the bottom of the microvia after laser drill process which, if not cleaned, poses risk to the electrical functionality of the device. Thus, microvia cleanliness is the key to a reliable and electrically functional device. Currently, industry employs a wet process to clean the etch residue that results in significant chemical waste. Here, we evaluated an alternative, but effective Photodesmear method that provides a low cost of ownership and almost negligible environmental impact. We have demonstrated in IMAPS 2013 that this process can achieve residue- and silica filler free via bottoms by a two-step process: i) illuminating 172 nm vacuum ultraviolet light (VUV) on the panels, resulting in a photochemical ashing, and ii) a water clean. This process does not reduce the surface energy of the build-up material, thus not impacting the downstream processes. The main technical challenge in developing Photodesmear technology will be panel level uniformity in cleaning all the microvias within the same process step. We have demonstrated that our process can achieve a highly uniform treatment over 510 mm wide panels. The process was optimized to clean microvias with a range of aspect ratios on insulating film (material N) drilled by CO2 laser. The microvia bottoms were also found to be clean when the vias were drilled by UV laser to test the desmear capability. The quality of the Photodesmear was tested by measuring the peel strength between electrolytically plated Cu and dielectric surface, and by performing the quick via pull (QVP) to verify the failing interface. We found high peel strength of 0.7 kgf/cm when sputtered Cu seed layer was used. QVP experiments confirmed that the via residue is cleaned effectively since the interface between the plated Cu and the underlying Cu pad did not fail. This study shows that Photodesmear process is capable to produce clean vias along with acceptable peel strength. Future issues are to research the reliability, productivity, and cost of the Photodesmear process to compare with the existing process.

Mechanical Reliability of Embedded Array Capacitors in Ultrahigh-Performance Microprocessors

Increasing power delivery and performance requirements for next-generation Intel microprocessors has led to the need for a high-capacitance low-inductance decoupling option very close to the die. An embedded array capacitor (EAC) is a large array capacitor embedded in the high-density interconnect (HDI) substrate core and provides a low-inductance path to the die. This paper describes technology development challenges encountered while enabling EACs on Intel's advanced microprocessors. Various package interfaces resulting from the EAC embedding showed very high stress and propensity to delaminate. These defects were addressed by tailoring suitable materials and process modifications during the manufacturing process. Expansion of the embedding material in the HDI substrate resulted in high C4 area warpage. This led to issues such as solder bump bridging, underfill voids, and reliability fails. The technology development challenges and the solution paths described in this paper are very useful to industry in understanding the integration of advanced decoupling options in ultrahigh-performance microprocessor packages.

Anti-Counterfeit, Advanced Microelectronics Packaging Solutions for Miniaturized Medical Devices

The medical industry is clearly and urgently in need of development of advanced packaging that can meet the growing demand for miniaturization, high-speed performance, and flexibility for handheld, portable, in vivo, and implantable devices. To accomplish this, new packaging structures need to be able to integrate more dies with greater function, higher I/O counts, smaller die pad pitches, and high reliability, while being pushed into smaller and smaller footprints. As a result, the microelectronics industry is moving toward alternative, innovative approaches as solutions for squeezing more function into smaller packages. This paper discusses the development of advanced packaging that can meet the growing demand for miniaturization, high-speed performance, and flexibility for miniaturized electronic devices. In particular, recent developments in high density interconnect (HDI) substrate technology are highlighted. System-in-Package (SiP), embedded passives, stacked packages, and flex substrates are utilized to achieve significant reduction in size, weight, and power (SWaP) consumption in electronic devices. The paper also describes a novel approach for the fabrication of silicone-coated flexible substrates to provide biocompatibility for implantable devices. In particular, we highlight recent developments on silicone coatings on high density, miniaturized polyimide-based flexible electronics. A variety of high density circuits ranging from 11 microns lines/space to 25 microns lines/spaces were processed on polyimide flex substrates and subsequently coated with biocompatible silicone coatings. The electrical performance of silicone coated batteries was characterized by voltage measurements. The final structure enhances the stretching capability. Fabrication of advanced medical substrates incorporating technologies for parts authentication (anticounterfeit measures) such as embedded signature circuits and use of nano or micro materials as signatures are discussed. In some instances, these measures do not add cost to package fabrication.

Thermal and Mechanical Considerations for Silicon-Resin High-Density Substrate

We examine the thermomechanical tradeoffs in a novel technology for high-density interconnect substrates. Fabricated from silicon (Si) wafers with planar cavities of highly filled composite encapsulant, the technology leverages established Si photolithography but offers improved mechanical properties. Modules are subject to thermomechanical stress during encapsulant cure, assembly reflow, module fabrication, and operation. We show that improvements in junction-to-ambient sinking offset the heat density increase in such systems and low expansion encapsulants prevent failure during cure and subsequent processing. We employ finite element modeling and materials testing to show the effect of wafer design and material selection on the in-plane and through-plane stresses in the module.

High-density interconnect board design for wafer-level packaging

The main advantage of wafer-level packaging is a smaller, thinner and lighter package with minimised electrical length and lower inductance. Presented is a printed circuit board electrical design to assemble a wafer-level package of a wireless radio core. The link impact and challenges are addressed in both time domain and frequency domain. The high-density interconnect substrate is analysed using a design of experiment technique to test the significance of structured variation. Its signal integrity and power delivery performance are compared with a similar design, but much thicker using a flip-chip package mounted on top of the conventional board. The thin board for wafer-level packaging provides better power delivery and signal performance than the traditional assembly.

System-on-package: a broad perspective from system design to technology development

In this paper, we summarize and analyze main challenges towards system-on-package (SoP) integration with a broad perspective from system design to technology development. We see that the future SoP faces a main challenge of changed system architecture that will be different from today’s personal computer or PC-based systems. It is likely that communication-network based system architectures will be interesting to future SoP platforms. Second, we find that a major paradigm shift will occur in design methodology for SoP integration that emphasizes a coherent co-design of chip, package and system in a mixed signal environment and in combination with new issues such as virtual components integration. On the technology side, the major challenges will be power dissipation and system cooling, low-cost and thermal-matched high-density interconnect substrates, as well as low-cost passive components integration. Finally, we present some research examples that aim to cope with these new challenges on a strategic basis.

Reliability assessment of microvias in HDI printed circuit boards

Accelerating adoption of CSP and flip-chip area array packaging for high performance and hand-held applications is the main driving force for high-density substrates and printed circuit boards. At the Packaging Research Center, Georgia Institute of Technology (PRC-GT), ultra-fine line high density interconnect (HDI) substrate technology is being developed as part of the system-on-a-package (SOP) research and testbed efforts to meet these emerging requirements. To be adopted by industry, this novel technology must demonstrate the critical elements of high reliability and low cost processing. The HDI and microvias structures discussed in this paper were fabricated on high Tg organic substrates using a sequential build-up process, and were subject to extensive liquid to liquid thermal shock testing. All 75 /spl mu/m microvias and above successfully passed 2000 cycles without failure, and first failure occurred at 1000 cycles for 50 /spl mu/m microvias on a 50 /spl mu/m thick dielectric layer. Microvia down to 25 /spl mu/m diameter on a 25 /spl mu/m thick dielectric layer have passed 2000 cycles with zero failures. Cross-sectioning confirmed that failures were caused by process related defects, such as thin electrolytic copper plating. This paper will discuss the reliability results of the PRC HDI microvias process and methods to improve the mechanical reliability of small photo defined microvias fabricated on similar laminate substrates.

New halogen‐free materials for PWB, HDI and advanced package substrate

Recently, the requirement of the printed wiring boards (PWBs) of environmental harmony type has risen rapidly. We have developed the core technologies of halogen‐free. They consist of resin system technology and high filler content technology. The point of the resin technology is the development of a new resin system (RO resin) which takes nitrogen into the molecule frame in a large quantity. The point of the high filler content technology is the development of a new filler interphase control system (FICS) which enables the high dispersion of fillers. A variety of halogen‐free substrates which can be applied to the diversified needs have been developed by combining these technologies. They are MCL‐RO‐67G, thin laminate for the multi‐layer PWBs, MCF‐4000G, build‐up material for high density interconnect (HDI) , and MCL‐E‐679F(G), high Tg laminate for the advanced plastic IC packages (PKGs) and PWBs. These materials have excellent heat‐resistance, and are suitable for lead‐free solder as well. The robustness towards temperature, humidity and frequency of those materials is better than that of current materials. The synthetic board design of the environmental harmony type is facilitated by combined use of these materials. We are also developing several multi‐layer and build‐up materials, HDI for high frequency, high speed and high reliability application to meet the requirement of PWBs and advanced PKGs for the near future.

HDI substrate technology for electronic automotive applications

Presents a survey of build‐up technologies based on the manufacture of microvia in thin dielectric sheets (< 100µm) deposited on PWB materials. These technologies will permit the PWB industry to manufacture high density interconnect substrates and answer the routeing requirements of high number I/Os, BGAs and new area array components. Bull Electronics Angers (BEA) has developed an HDI technology where microvias with hole diameters lower than 100µm are mechanically or laser drilled and interconnected lines at pitch down to 200µm are manufactured. In the frame of a European MEDEA project, ATEMAES, the design of an electronic subsystem manufactured by Magnetti Marelli in ceramic thick film technology has been adapted to the design rules of the HDI technology developed by Bull. This is part of an evaluation program for the use of HDI technology for automotive applications.

Probabilistic prediction of wiring demand and routing requirements for high density interconnect substrates

Estimation of wiring and routability requirements for high density substrates is crucial for the development of new technologies, design, CAD tools, and optimization. This paper describes a new approach to wireability estimation that goes beyond Rent's rule. This approach depends on data flow and placement information available at early stages of the design process. Bus and random wiring are modeled explicitly. Excellent overall agreement is demonstrated between our predictions and published wiring data for two MCM systems. The relationship between placement and wireability will be presented through an optimization study by taking wiring parameters and their distributions as metrics. The application of this approach to the estimation of the required signal layers will be demonstrated.

Low temperature co-fired glass ceramic high density interconnect substrate with improved thermal management

A hybrid integrated regulator/modulator with a digital and analog signal bus system for power conditioning of a transmit/receive module having a density figure of merit of 69 W/in/sup 3/ and 845 W/lb is described. High-density multichip power conditioning modules were designed using a low-temperature cofired ceramic as the base substrate. The design was fabricated, tested, and delivered. Design considerations, guidelines, and fabrication concerns are discussed. Aspects discussed include high-density computer aided design and packaging concepts, the regulator/modulator approach to power conditioning, design guidelines and substrate characteristics of the glass-ceramic material system, thermal management solutions for high-powered chips, and reliability and performance data on the finished substrate and module. Emphasis is on the improved processing of blind thermal slots and cofired top metallization. An appreciable improvement of thermal conductivity with thermal vias was achieved.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>