High-density Ferroelectric Random Access Memories Research Articles

High density stand alone-fram

Ferroelectric random access memory (FRAM) has been pursed as a new standalone memory due to its ideal memory properties such as fast random access in read/write mode and non-volatility with unlimited usage. However, FRAM has only achieved a limited success in limited applications because current FRAM is far behind its inherently outstanding properties. Recently, mega-bit density scaled FRAMs have been developed for creating big market. Many essential technologies have been built with the mega-bit density devices. Among those technologies, 1T1C COB (capacitor over bit line) cell structure is the most important because it can greatly reduce the cell size of FRAM compared to previous and current 2T2C FRAM. Although the recent demonstration gives a promising future for stand-alone FRAM application, current 1T1C COB FRAM still has incomparably large cell size factor compared to DRAM and Flash. This is one of the most challenging issues that FRAM faces for developing high-density stand-alone memory. Besides, there are still several design issues to be optimized for better performance and better reliability such as longer endurance and better retention. In this paper, the present status of high density FRAM technology will be firstly reviewed and the issues of current high density FRAM will be discussed with the possible solutions. Finally future technology will be projected.

The origin and elimination of random single-bit failure in high density 1t1c fram

The COB (capacitor-over-bit line) structure is essential for integrating high density FRAM (ferroelectric random access memory) device. It is very difficult in the COB cell structure to maintain low contact resistance between plug material and bottom electrode during the integration processes. We have used CoSix/poly-Si and Pt/IrO2/Ir as plug materials and bottom electrode stack, respectively. However, random single-bit failure was observed due to the high contact resistance, which was caused by the formation of amorphous oxide layer, especially, during high temperature anneal for PZT (Pb[Tix,Zr1-x]O3) crystallization. It was observed that silicon atoms diffuse even into Ir oxygen barrier, thus leading to the oxide formation between the plug and Ir oxygen barrier. The approach we have taken to prevent contact resistance failure is to optimize the plug material that has high endurance against oxidation reaction. In this study, we developed tungsten plug technology to eliminate the random single-bit failure. It is expected that this tungsten plug technology can provide highly reliable COB structure for 32Mb FRAM device and beyond.

Low temperature processed 0.7SrBi2Ta2O9–0.3Bi3TaTiO9 thin films fabricated on multilayer electrode-barrier structure for high-density ferroelectric memories

Thin films of solid-solution material 0.7SrBi2Ta2O9–0.3Bi3TaTiO9 (0.7SBT–0.3BTT) were fabricated on n+-polycrystalline (n+-poly) Si substrates by a metalorganic solution deposition technique at a low processing temperature of 650 °C using a Pt–Rh/Pt–Rh–Ox electrode-barrier structure. The Pt–Rh/Pt–Rh–Ox structure was deposited using an in situ reactive radio frequency sputtering process. The electrodes had a smooth and fine-grained microstructure and were excellent diffusion barriers between the 0.7SBT–0.3BTT thin film and Si substrate. The ferroelectric (0.7SBT–0.3BTT) test capacitors using these electrode-barrier grown directly on Si showed good ferroelectric hysteresis properties, measured through n+-poly Si substrate, with 2Pr and Ec values of 11.5 μC/cm2 and 80 kV/cm, respectively, at an applied electric field of 200 kV/cm. The films exhibited good fatigue characteristics (<10% decay) under bipolar stressing up to 1011 switching cycles and the leakage current density was lower 10−7 A/cm2 at an applied electric field of 200 kV/cm. The good ferroelectric properties of 0.7SBT–0.3BTT solid-solution thin films at a low processing temperature of 650 °C and excellent electrode-diffusion barrier properties of a Pt–Rh/Pt–Rh–Ox structure are encouraging for the realization of high-density nonvolatile ferroelectric random access memories on silicon substrates.

High-density chain ferroelectric random access memory (chain FRAM)

A new chain ferroelectric random access memory-a chain FRAM-has been proposed. A memory cell consists of parallel connection of one transistor and one ferroelectric capacitor, and one memory cell block consists of plural memory cells connected in series and a block selecting transistor. This configuration realizes the smallest 4 F/sup 2/ size memory cell using the planar transistor so far reported, and random access. The chip size of the proposed chain FRAM can be reduced to 63% of that of the conventional FRAM when 16 cells are connected in series. The fast nondriven half-V/sub dd/ cell-plate scheme, as well as the driven cell-plate scheme, are applicable to the chain FRAM without polarization switching during the standby cycle thanks to short-circuiting ferroelectric capacitors. It results in fast access time of 45 ns and cycle time of 70 ns without refresh operation.