Higher Critical Charge Research Articles

An SEU-hardened ternary SRAM design based on efficient ternary C-elements using CNTFET technology

Ternary logic has been investigated for several years as it can provide substantial advantages in reducing the complexity of operations and the number of interconnects. On the other hand, with the advancement of technology and the reduction of the feature size and supply voltage, the sensitivity of memory elements to radiation effects has increased. In this paper, a robust ternary SRAM (TSRAM) cell is designed using a novel ternary C-element based on carbon nanotube field-effect transistors (CNTFETs). Besides, a 2m×2n ternary memory array architecture is designed and simulated based on the proposed TSRAM cell. Unlike the previous TSRAM cells, our proposed cell is hardened against radiation effects caused by high-energy particle strikes, which is a significant achievement in ternary memory design. Our extensive simulations demonstrate that the proposed radiation-hardened TSRAM offers up to 77× higher critical charge and up to 98 % higher SNM at the cost of 47 % to 65 % area overhead. It is also noteworthy that the proposed design only needs only two threshold voltages. Moreover, the proposed TSRAM is robust against the process and temperature variations. Our results emphasize that the proposed design is a milestone for designing high-performance, radiation-hardened, and robust ternary memory chips.

A highly reliable radiation tolerant 13T SRAM cell for deep space applications

This paper proposes a highly reliable radiation-tolerant 13T (HRRT 13T) SRAM cell for deep-space applications. The proposed SRAM cell design can effectively tolerate radiation events. The design metrics of the proposed SRAM cell are compared with conventionally used SRAM cells like QUCCE 10T, QUCCE 12T and standard 6T SRAM cells. The proposed SRAM cell consumes 9.4% and 14% lesser hold power (HPWR) compared to QUCCE 10T and QUCCE 12T SRAM cells, respectively. The proposed SRAM cell exhibits 12.7%, 3.63% and 11.7% shorter read access time (TRA) compared to QUCCE 10T, QUCCE 12T and 6T SRAM cells, respectively at a nominal supply voltage (VDD) of 0.7 V. The proposed HRRT 13T SRAM cell exhibits higher read stability compared to other conventionally used SRAM cells. This has been validated by 2.92×, 2.33× and 2.06× higher read static noise margin (RSNM) exhibited by the proposed cell compared to the 6T, QUCCE 10T and QUCCE 12T SRAM cells, respectively at VDD = 0.7 V. The proposed SRAM cell exhibits high radiation tolerance capability compared to the conventionally used SRAM cells. This has been proved by 94.1%, 17.8% and 10.0% higher critical charge (QC) of the proposed cell compared to 6T, QUCCE 10T and QUCCE 12T SRAM cells, respectively at VDD = 0.7 V. The proposed cell achieves all these improvements at the expense of 1.05×, 1.38× and 1.36× longer write delay (TWA) compared to QUCCE 10T, QUCCE 12T and 6T SRAM cells, respectively at VDD = 0.7 V. Extensive simulations on SPICE using 16-nm CMOS technology are performed to validate the theoretical design of the proposed SRAM cell.

Soft error hardened voltage bootstrapped Schmitt trigger design for reliable circuits

Bias Temperature Instability and soft error rate are the major reliability issue with the technology scaling. BTI leads to an increase in the threshold voltage of the MOS transistors, which reduces the drain current. The threshold voltage of the PMOS transistor increases due to NBTI with stress time, which degrades the circuit performance. In this paper, we propose a novel reliable voltage bootstrapped Schmitt trigger circuit with soft error hardening enhancement and lower effect of BTI. We investigate all the circuit simulations which impact on the soft error rate of inverter circuits using HSPICE 65 nm CMOS technology. The results show that the proposed inverter circuit has a higher critical charge and lower soft error rate (SER) when compared to other reference inverter circuits. To better assess, we introduced Vth sensitivity and observed that the degradation of the proposed inverter circuit is 30% higher as compared to conventional CMOS inverter. The proposed inverter offers lower dynamic power, leakage power, and circuit delay of 91.11%, 93.47%, and 38.17%, respectively, as compared to CMOS inverter at 3 years of the stress time. Finally, the overall circuit performance is evaluated using the figure of merits and observes that the proposed inverter has the highest FOM correspond to other inverter circuits, which reveal that the proposed circuit is useful for the applications where the effect of radiations are higher.

On-Chip Adaptive VDD Scaled Architecture of Reliable SRAM Cell With Improved Soft Error Tolerance

Negative bias temperature instability (NBTI) is the major reliability issue which affects many parameters such as threshold voltage, mobility, and leakage current. The threshold voltage of the PMOS transistor increases due to NBTI with stress time, which degrades the circuit performance. In this article, we have proposed a novel reliable data-dependent low power 10T SRAM cell, which is highly stable and free from half select issues. We investigated all the circuit simulations using 65nm CMOS technology. The proposed 10T cell has a higher critical charge and lower soft error rate (SER) as compared to other SRAM cells. To better assess, we introduced a bit read failure (BRF) at read operation and observed that the BRF of the proposed 10T cell is significantly reduced as compared to the other considered SRAM cells at 0.15V supply. The leakage power, write power-delay-product, and read power-delay-product of the proposed 10T cell is $0.1\times $ , $0.21\times $ , and $3.13\times $ , respectively as compared to the conventional 6T cell at 0.4V supply. The proposed cell offers $4\times $ , $1.15\times $ and $1.66\times $ higher read, hold and write margin, respectively, as compared to 6T cell at 0.4V supply voltage. The simulation result shows that the HSNM, WSNM, and RSNM are decreased by 0.31%, 0.13%, and 0.08%, respectively, with the proposed 10T cell while 6T cell reduces 3.21%, 0.43%, and 8.62%, respectively, after 10 years of stress time. We have also introduced an on-chip adaptive VDD scaled reconfigurable architecture compared to the conventional array architecture design to reduce 97.04% and 92.17% hold power of unselected cells during read and write operation of the selected cell, respectively for the proposed 10T cell.

Soft error hardening enhancement analysis of NBTI tolerant Schmitt trigger circuit

Bias temperature instability (BTI) and soft errors are major reliability concerns for deep submicron technologies. Negative BTI leads to an increase of the threshold voltage of PMOS transistors and is thus considered a serious challenge for improving circuit performance. In this paper, we concentrate on a design-time solution, i.e., more reliable NMOS only Schmitt Trigger with Voltage Booster (NST-VB). For this we analyzed the impact of BTI on the soft-error susceptibility of different CMOS circuits using HSPICE and performed critical charge simulations considering different supply voltages and stress time. From our results, we conclude that the NST-VB circuit has a higher critical charge when compared to CMOS inverters and Schmitt trigger (ST) based counterparts. NST-VB has improved the sensitivity of 62.48% and 55.10%, as compared to CMOS inverter and ST circuits, respectively, after three years of operation. To better assess soft error resilience, we introduce a soft error rate ratio (SERR) as a performance metric. Our analysis indicates that NST-VB has 12.62%, and 12.39% less SERR compared to ST and CMOS inverters. The effect of process variation on CMOS inverter, ST inverter and NST-VB circuit are analyzed using 5000 Monte Carlo simulations for critical voltages and we observe that the deviation of NST-VB is 6.06× and 6.89× less as compared to the CMOS and ST based inverters, respectively.

Soft Error Hardened Asymmetric 10T SRAM Cell for Aerospace Applications

Soft error in SRAM cell is one of the major reliability concern under aerospace radiation environment. A soft error occurs in SRAM cell due to charged particle strikes on sensitive nodes. In this paper a radiation hardened asymmetric 10T (AS10T) SRAM cell is presented to enhance the soft error hardening. The proposed cell uses read decoupled path to improve read static noise margin (RSNM) and voltage booster connected between storage nodes to improve node capacitance and hence enhanced radiation hardening. The proposed AS10T cell has a 75.83% higher critical charge as compared to 6T SRAM cell. For validation of soft error hardening of the proposed cell soft error rate ratio with supply voltage and temperature change is calculated and it is found that the AS10T has 6.41× and 3.2× less soft error rate ratio compared to 6T SRAM cell respectively. To better assess soft-error resilience and performance of the cell we introduce reliability stability to energy area product (RSEAP) ratio as a performance metric. Our analysis indicates that AS10T cell has 2.83× 1.6× and 1.36× higher RSEAP as compared to 6T RD8T and AS8T SRAM cells respectively.

Design and Evaluation of an Efficient Schmitt Trigger-Based Hardened Latch in CNTFET Technology

This paper presents a Schmitt trigger (ST) buffer using carbon nanotube FET (CNTFET) for reliable low-power applications. Nanoscale circuits are more susceptible to transient faults or soft errors due to the reduction of the stored charge in their sensitive nodes. Hereupon, low-cost and tolerant circuits design is a significant challenge, especially in the nanoscale storage cells. In addition, the proposed ST is utilized for designing a low-power hardened latch. In the proposed design, instead of up-sizing and increasing the input capacitance, the determined hysteresis mechanism of the proposed ST buffer is utilized to improve the single event upset hardness. The simulations are conducted based on the Stanford CNTFET model at 16-nm technology node. According to the results, the proposed ST has on average 90% lower power-delay product and higher robustness to PVT variations as compared to its most efficient CNTFET-based counterparts. Moreover, the simulations confirm the considerable tolerance of the proposed hardened latch to the multiple node upset as compared to the state-of-the-art designs. The proposed hardened latch has on average 68% higher critical charge, which considerably enhances its reliability and on average 16% smaller area as compared to its counterparts.

An SEU-Resilient SRAM Bitcell in 65-nm CMOS Technology

This paper presents an SEU-resilient 12 T SRAM bitcell. Simulation results demonstrate that it has higher critical charge than the traditional 6 T cell. Alpha and proton testing results validate that it has a lower soft error rate compared to the reference designs for all data patterns and supply voltage levels. The improvement in SEU tolerance is achieved at the expense of 2X area penalty.

A Novel Scheme for Tolerating Single Event/Multiple Bit Upsets (SEU/MBU) in Non-Volatile Memories

This paper proposes a novel scheme for a low-power non-volatile (NV) memory that exploits a two-level arrangement for attaining single event/multiple bit upsets (SEU/MBU) tolerance. Low-power hardened NVSRAM cell designs are initially utilized at the first level; these designs increase the critical charge and decrease power consumption by providing a positive (virtual) ground level voltage. A soft error rate (SER) analysis is also pursued to confirm the findings of the critical charge-based analysis. Simulation of these cells shows that their operation has a very high SEU tolerance, the charges in the nodes of the circuits for non-volatile storage and gate leakage current reduction have very high values, thus ensuring that a SEU will highly unlike affect the correct functions. A novel memory scheme with the proposed NVSRAM cells is proposed for tolerating MBU; in this scheme, only the error detection circuitry is required, because error correction is provided by the non-volatile elements of the NVSRAM cells. Simulation results show that the proposed scheme is very efficient in terms of delay and number of transistors (as measure of complexity). Moreover, the very high critical charge of some of the proposed cell designs reduces the number of MBU appearing as errors at the outputs of the memory, thus further reducing the error detection hardware required by the proposed scheme. An extensive evaluation and comparison of different schemes are presented.

The Effects of Neutron Energy and High-Z Materials on Single Event Upsets and Multiple Cell Upsets

Neutron-induced charge collection data and computer simulations presented here show that the presence of high-Z materials, like tungsten, can increase the single event upset (SEU) and multiple cell upset (MCU)cross sections of high critical charge (Q <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">crit</sub> ) devices exposed to the terrestrial neutron environment because of interactions with high energy ( >; 100 MeV) neutrons. Time-of-flight data and computer simulations presented here demonstrate that 14 MeV neutrons do not produce highly ionizing secondary particles. Thus, 14 MeV neutrons can only simulate the SEU response of 65 nm SRAM devices in the terrestrial neutron environment for devices with a Q <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">crit</sub> <; 27fC, and can simulate the 2-bit MCU response to within a factor of two only for very low Q <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">crit</sub> devices, <; 1.2 fC.Additionally, it is shown that 14 MeV neutrons cannot adequately simulate the 3 or more bit MCU response for typical 65 nm SRAM devices.

Design and Performance Evaluation of Radiation Hardened Latches for Nanoscale CMOS

Deep sub-micrometer/nano CMOS circuits are more sensitive to externally induced radiation phenomena that are likely to cause the occurrence of so-called soft errors. Therefore, the tolerance of the circuit to the soft errors is a strict requirement in nanoscale circuit designs. Since the traditional error tolerant methods result in significant cost penalties in terms of power, area, and performance, the development of low-cost hardened designs for storage cells (such as latches and memories) is of increasing importance. This paper proposes three new hardened designs for CMOS latches at 32 nm feature size; these circuits are Schmitt trigger based, while the third one utilizes a cascode configuration in the feedback loop. The Cascode ST latch has 112% higher critical charge than the conventional reference latch with only 10% area increase. A novel design metric (QPAR) for latches is introduced to assess the overall design effectiveness such as area, performance, power, and soft error tolerance. The novel metric (QPAR) shows the proposed cascode ST latch achieves up to 36% improvement in terms of QPAR compared with the existing hardening designs. Monte Carlo analysis has confirmed the robustness of the proposed hardened latches to process, voltage, and temperature (PVT) variations.

Theoretical Correlation of Broad Spectrum Neutron Sources for Accelerated Soft Error Testing

Several broad spectrum, high energy neutron source facilities exist throughout the world for accelerated soft error testing. However, none accurately replicate the terrestrial neutron spectra across the range of 1 MeV to 1 GeV. The objective of this study is to quantify the errors introduced in accelerated soft error measurements from these facilities using a range of theoretical soft error cross-sections for both high and low critical charge events.

Evidence of High Critical Temperature Charge Density Wave Transitions in the (PO2)4(WO3)2m Family of Low Dimensional Conductors for m ${\bf\geq}$ 8

The monophosphate tungsten bronzes with pentagonal tunnels (MPTBp) of general formula (PO 2 ) 4 (WO 3 ) 2m form a family of layered conductors where the average number of conduction electrons per tungsten atom 2/m can be changed while keeping the same structural array. Previous investigation of the low m = 4, 6 and 7 members of this family have shown that this series is subject to several successive incommensurate charge density wave (CDW) long range orders below room temperature (RT). Here we present an X-ray scattering study of the m = 8, 9, 10, 11, 12, 13 and 14 members of this family. A very rich and diverse structural phase diagram is observed. The m = 8 member shows only short range order below RT at two different incommensurate wave vectors while commensurate and/or incommensurate long range order is observed above RT for m ≥ 9. Incommensurate modulations are observed for the m = 11 and 13 members and commensurate ones for the other members. In most of the 7 ≥ m ≥ 13 members the observation of several harmonics suggests that the CDW modulation is non-sinusoidal, which could be the fingerprint of electron localization phenomena due either to strong electron-phonon or electron-electron interactions. These CDW instabilities have been tentatively attributed to chains a and a ± b of WO 6 octahedra into which the ReO3 type layers of (PO 2 ) 4 (WO 3 ) 2m can be decomposed. In addition, the observation for m ≥ 9 of a commensurate (1/2,0,0) or (1/2, 0, 1/2) modulation or (1/2, 0, l) diffuse scattering suggests the occurrence of an incipient WO 3 type antiferroelectric instability which interacts with the CDW for m ≤ 13. We further discuss the division between high m value and low m value members in relation to the z dependence of the physical properties of some M x WO 3 tungsten bronzes families and finally propose a dielectric to magnetic duality between CDW tungsten oxides and superconducting copper oxides.

Charge collection in HI/sup 2/L bipolar transistors

Charge-collection measurements were carried out on HI/sup 2/L transistors in GaAs in order to determine the thickness of the equivalent sensitive volume to be used in calculating single-event-upset (SEU) rates for this technology and to set a lower limit to the critical charge. The measurements were in the form of pulse-height spectra measured between the base-emitter and collector-emitter contacts upon exposure to energetic protons, alpha particles, and sulfur ions. The sulfur data are consistent with the SEU-sensitive junction being the base-emitter junction with an equivalent sensitive volume of thickness 0.1 mu m for high-linear-energy-transfer (LET) particles. This value is a factor of two less than the thickness value previously used to estimate error rates in space and is a factor of three less than estimates based on alpha particles, which have lower LET. Comparison of the proton charge-collection data with earlier SEU measurements results in a revision of the estimate of the lower limit to the critical charge for HI/sup 2/L gate arrays to a value that is higher than previous estimates by more than a factor of two. The combination of reduced charge collection and higher critical charge implies that this technology will be considerably harder to SEUs than previously believed. >