High Common Mode Voltage Research Articles

A Scalar Decoupled PWM Technique for a Three-Level Symmetrical Dual Inverter Fed OEWIM Drive for Electric Vehicle

Induction motor is employed in electric vehicle to control the speed. Dual inverter fed drives are used for this purpose. Even though it finds application in many applications, high common-mode voltage (CMV) becomes a major problem and it results in EMI problems. Hence, to overcome this problem, this work introduced a novel PWM generation technique named scalar decoupled PWM topology to control a three-level symmetrical DI fed OEWIM. In this proposed topology, switching signals of the inverter 1 and 2 can be generated and controlled separately. To examine the efficiency of the proposed topology, its operation is examined under both continuous and discontinuous modes of operation and is carried out in both simulation and experimental set up. From the acquired results, it is concluded that this proposed topology exhibits reduced CMV and harmonics when compared to traditional PWM topology.

Common-Mode Voltage Reduction Method for Three-Level Inverter With Unbalanced Neutral-Point Voltage Conditions

The three-level inverter has been widely researched and adopted in industry. This article further proposes a carrier-based modulation method to reduce the common-mode voltage (CMV) and obtain high-quality output currents for three-level inverter with unbalanced neutral-point voltage conditions. In this method, the zero-sequence voltage is calculated by three-phase modulation waves, three-phase output currents, and voltages across the dc-link capacitors. The limitations of the zero-sequence component are carefully considered in order not to generate the basic voltage vector with high CMV magnitudes. In addition, a deadbeat control scheme for controlling the dc-link voltages asymmetrically with the proposed pulsewidth modulation method is presented, and asymmetrical control of dc-link voltages can be realized with fast response. Compared with the conventional space vector modulation (SVM) and the virtual SVM methods, the proposed scheme can reduce the CMV by half. Simulated and experimental results validate the effectiveness of the proposed method.

A Direct Carried-Based PWM Scheme With Reduced Switching Harmonics and Common-Mode Voltage for Current Source Converter

The performance of a current source converter (CSC) is greatly affected by its adopted modulation schemes. Among various modulation schemes, the carrier-based pulsewidth modulation (CB-PWM) has gained increasing attention owing to its inherent autosequencing process. However, existing CB-PWM schemes suffer from either high switching harmonics in ac current or high low-order common-mode voltage (CMV), and sometimes, both, which restrains the application of this promising scheme. To address this issue, this article explores the modulation mechanism of CB-PWM for a CSC. Based on that, this article proposes a direct CB-PWM scheme. Its implementation, mechanism, and characteristics have been developed and presented in detail. It is shown that the proposed scheme enjoys inherent low switching frequency, easy implementation, as well as high dc current utilization. More importantly, compared with existing CB-PWMs, the proposed scheme can simultaneously reduce the switching harmonics of ac current and the low-order CMV for a CSC. These superior performances can bring potential benefits to scale down the ac filter and common-mode choke for practical CSC applications. Effectiveness of the proposed scheme is verified experimentally with a CSC operating as an inverter.

Double Vector Model Predictive Control to Reduce Common-Mode Voltage Without Weighting Factors for Three-Level Inverters

The conventional model predictive control (MPC) suffers from high common-mode voltage (CMV) magnitude and large current ripples. In this article, the reduced CMV MPC strategy with double vector (RCMV-MPCDV) is proposed for three-level inverters, which adopts double vector to reduce the CMV and current ripples simultaneously in per-sampling period. First, based on geometric relationship of median, a novel cost function that evaluates median line distance is proposed to reduce the computational complexity, rather than evaluating the closest distance. Second, in order to reduce the computational burden, the double vector preselection algorithm is presented with fewer evaluation times. Third, the candidate vectors are reclassified and regrouped from partial basic vectors, which restricts CMV magnitude within one-sixth of dc-link voltage. In addition, to select more satisfactory double vectors for RCMV-MPCDV scheme, two improved methods are proposed to compensate the losing candidate vectors. The simulation and experimental results with steady-state performance and dynamic response validate the effectiveness of the proposed method.

Eliminating Common-Mode Voltage Spikes Caused by Dead-Time Effect in Three-Phase Inverters Through Symmetrical Rotation Reverse Carriers

In the three-phase inverters, high common-mode voltage (CMV) will produce some serious negative effects. Compared with the conventional pulse width modulation, the use of reverse carrier scheme (RCS) is a simple way to reduce the CMV peaks to one third of the original peaks in theory. However, in practice, some CMV spikes will appear in the inverter when using the RCS. The CMV spikes are caused by the switching dead-time effect. This article presents an improved RCS, which is called the scheme of symmetrical rotation reverse carriers (SRRCs). In this scheme, three-phase carriers are reversed periodically in turn. This ensures that only one phase carrier is reversed at any time, which eliminates the generation mechanism of the CMV spikes. The SRRC scheme is not only suitable for the three-phase inverters with a fixed-frequency carrier but also suitable for the inverters with the carrier frequency modulation. The feasibility and effectiveness of the proposed SRRC scheme are verified by the simulations and experimental results in a three-phase inverter.

Modified Synchronized SVPWM Strategies to Reduce CMV for Three-Phase VSIs at Low Switching Frequency

The high common-mode voltage (CMV) generated by conventional synchronized space vector pulsewidth modulation (SVPWM) strategies may lead to bearing failure and electromagnetic interference problems. However, existing CMV reduction methods are based on asynchronized SVPWM, which will cause unacceptable harmonic distortion at low switching frequency. In this article, four modified synchronized SVPWM (MS-SVPWM) strategies are presented to reduce the CMV and improve the output performance of three-phase voltage source inverters (VSIs) at low switching frequency. In the proposed methods, only nonzero vectors are employed to reduce CMV, and the constraint conditions of preserving three-phase, half-wave, and quarter-wave symmetries of PWM waveforms in terms of active vectors are established. A precorrection scheme is proposed and applied to the presented MS-SVPWM strategies to achieve an accurate output voltage of inverters. Moreover, the linearity characteristics of the output voltage, the harmonic performance of line-line voltage and CMV, and the stator flux trajectories of the proposed strategies are investigated and compared. Experimental results for a 2.2-kW induction motor fed by a two-level VSI are presented to illustrate the effectiveness of the proposed MS-SVPWM strategies.

A capacitor-splitting DAC switching scheme with high power-efficiency and low common-mode voltage variation

In this letter, a capacitor-splitting switching algorithm for successive approximation register (SAR) analog-to-digital converters is proposed. To achieve low power, the hybrid switching scheme is involved. The monotonic switching technique is used during the last bit cycle; for other bit cycles except the first one, the switching is based on MSB and the former determined bit. Besides, the common-mode voltage remains constant during the entire bit cycles except the last one. In addition, the proposed capacitor-splitting switching process is easily performed, relaxing the design complexity of the SAR control logic. As a result, the proposed switching scheme is a better trade-off among energy-efficiency, common-mode voltage variation, and logic complexity.

A Modular Switching Position With Voltage-Balancing and Self-Powering for Series Device Connection

Medium-voltage converters, especially those making use of SiC devices, require high common-mode voltage immunity and resilience against associated high dv/dt across multiple isolation barriers. A truly modular and common-mode immune switching position could be beneficial for these applications. The design of a modular switching position is presented here for a series connection of power semiconductors with voltage-balancing and self-powered-gate capabilities. The designs of the voltage-balancing and self-powered circuits are described, followed by simulations and testing of a 3.3-kV switching position formed by two 1.7-kV SiC MOSFETs in series. Testing results demonstrate the ability of the proposed switching position to balance the voltage across series-connected MOSFETs even if the gate signals of the series-connected devices are not perfectly synchronized while powering themselves directly from the OFF-state voltage across them. In addition, a startup circuit for the switching position is proposed and experimentally confirmed.

Model predictive control method with common-mode voltage suppression for dual three-phase permanent magnet synchronous motor

Recently, the interest in model predictive control (MPC) and dual three-phase drives has been growing rapidly. Due to the high redundancy of voltage vector in the system composed of dual three-phase permanent magnetic synchronous motor (PMSM) and six-phase inverter, the computational complexity and current harmonics of MPC are high. In addition, the zero vector has been used by traditional MPC, which will cause higher common-mode voltage. In this paper, a novel MPC method with twice predictions and synthetic vectors is proposed which can not only suppress common-mode voltage, but also reduce computational complexity and current harmonics. The mathematical model of a dual three-phase PMSM are verified by the experimental results under the common-mode voltage suppression.

Modulation Techniques for a Modified Three-Phase Quasi-Switched Boost Inverter With Common-Mode Voltage Reduction

In a single-stage buck-boost quasi-switched boost inverter (qSBI), the shoot-through state insertion causes high amplitude common-mode voltage. Consequently, the qSBI becomes less attractive in transformerless photovoltaic (PV) systems. In this paper, a novel space vector pulse-width modulation for a modified qSBI is introduced to reduce the magnitude of common-mode voltage and push the modulation index up to 1. By properly choosing the shoot-through interval time, shoot-through states are considered to be inserted for boosting voltage and also reducing the THD value of the output voltage. The mathematical analysis and operating principles of the converter are discussed and verified through PSIM simulations. Finally, an experimental prototype is validated based on a TMS320F28335 DSP microcontroller and a DE0-Nano FPGA digital control platform.

Provision of Balanced Voltages Under Severe Unbalanced Load Currents in a Microgrid Using a 3D-SVM Technique

The current source inverter (CSI) is more suitable for use in photovoltaic applications than the voltage source inverter (VSI), but this structure has two main constrains: inability to feed unbalanced load and high common mode voltage (CMV). Despite the merits, use of CSI is limited due to these constrains. A three-phase CSI with a neutral-leg is presented in this paper, compared to the conventional three-phase CSI to overcome mentioned limitations, in which load unbalance under a PV system is dealt in a microgrid. An innovative three-dimensional space vector modulation (3D-SVM) is suggested for the four-leg CSI inverter. This novel 3D-SVM technique is very simple compared to the existing methods and computational complexity is too low. Operating principles, equivalent circuit and SVM is discussed for the four-leg inverter. Then, a balancing technique is applied to the four-leg inverter using the developed 3D-SVM, where simulations validate the capability of the inverter in supplying balanced load voltages; 4-leg inverter generates balanced sinusoidal voltages even under severe unbalanced load current.

Improved Transformerless Grid-Tied PV Inverter Effectively Operating at Twice the Switching Frequency With Constant CMV and Reactive Power Capability

In this article, an improved single-phase transformerless inverter is presented, which obviates the leakage current issue to a great extent. The proposed solution uses the dc-bypass (H6 type) topology with a diode clamp circuit, operated by a modified unipolar pulse-width modulation (PWM) scheme. An advantage of reduced switching losses comes with the use of the modified unipolar PWM, which produces effective double switching frequency at the inverter output. Due to the PWM strategy and diode clamp circuit, the common-mode voltage (CMV) of the inverter is constant throughout the operation. Consequently, the ground leakage current is negligible even in the presence of high parasitic capacitance of photovoltaic (PV) panels. Further, the other desirable features of the grid-tied inverters, such as reactive power injection for grid stability and low-voltage ride through (LVRT) are not compromised with the proposed scheme. A combination of high efficiency, constant CMV (and hence, negligible leakage current) and reactive power feeding capability with low component count stand the proposed system out among the existing transformerless grid-tied systems. The design and working principle of the proposed system are discussed and analyzed in detail. Simulation and experiment results are included to validate the proposed solution and its merits.

A Non-Invasive DC-10-MHz Wideband Current Sensor for Ultra-Fast Current Sensing in High-Frequency Power Electronic Converters

To enhance the performance of the converters along with improving their efficiency and miniaturization in many power electronics applications, a need for higher switching frequency is highly demanded. In high switching frequency converters, due to high common mode voltage issue, wideband, isolated, and low loss current sensor is required for the robust control design and ultra-fast protection. In this paper, we propose a non-invasive hybrid, isolated, and loss-less wideband current sensing method applicable for high-frequency power converters (dc-10 MHz). The proposed hybrid current sensing scheme combines two different isolated sensing technologies—a magnetoresistor sensor and a differential Rogowski coil sensor, which have complementary characteristics to achieve a wide sensing bandwidth. The proposed hybrid current sensor also utilizes planar magnetic field concentrators (MCON) using conductive materials to normalize the non-uniform magnetic field distributions generated by the current over a wide frequency range. We demonstrate through hardware prototypes and experiments that the proposed hybrid sensor yields to a very high sensing bandwidth of dc to 10 MHz. The performance of the proposed hybrid sensor is also evaluated in a 1-MHz dc–dc converter as well as a high-frequency H-bridge inverter module.

Enhanced direct torque control and predictive torque control strategies of an open‐End winding induction motor drive to eliminate common‐mode voltage and weighting factors

Direct torque control (DTC) and predictive torque control (PTC) strategies emerged as powerful tools for speed control of variable frequency drives (VFD). The limitations in classical DTC and PTC are: higher ripple in torque, flux, variable switching frequency, and higher common-mode voltage (CMV). High dv/dt and CMV results in shaft voltages, bearing currents, malfunction of power electronic devices and electromagnetic interference (EMI). To eliminate the CMVs and also to reduce the switching frequency, voltage vector selection-based DTC and PTC strategies are introduced to an open-end winding induction motor (OEWIM) drive. Another limitation of classical PTC is cumbersome tuning of weighting factors. To address this limitation, modified cost function-based PTC strategy has been developed to eliminate weighting factors. OEWIM drive operates with dual inverter configuration and the two inverters are operated with equal DC-link voltages; therefore, it delivers three-level output voltage. This article introduces various DTC and PTC strategies to an OEWIM drive to reduce torque, flux ripples, switching frequency, elimination of CMV, and weighting factors. The effectiveness of proposed DTC and PTC strategies is tested by dspace-1104 real-time interface controller and comparing the obtained results with classical DTC and PTC.

PLL-Based Feed-Forward Control to Attenuate Low-Frequency Common-Mode Voltages in Transformerless LVDC Systems

Low-voltage dc distribution systems have gained significant attention over the last years, since they provide simpler and more efficient integration of distributed generators and storage devices, establishing a pathway to net zero energy buildings. In low-power units, transformerless utility interface is preferred to reduce footprint and losses. However, the lack of galvanic isolation introduces a common-mode (CM) path between the dc distribution bus and the utility service grounding, leading to the presence of high CM voltages at the dc bus feeders. The attenuation of the CM voltage reduces the touch voltage amplitude and leakage current, contributing to a safer environment. In this paper, a feed-forward active compensation of the CM voltage is proposed. It relies on utility voltage parameters, estimated by a phase locked loop, to generate a counter CM voltage; hence, it does not require previous knowledge of the system CM path model or the addition of voltage sensors. Experimental results show that this technique can attenuate the CM voltage to non-dangerous magnitudes without interfering with the microgrid differential mode behavior.

Hybrid modular multilevel converter with cascaded full bridges for medium-voltage motor drives

Modular multilevel converter (MMC) is especially appropriate in high-voltage constant-frequency systems due to its modularity and scalability. But, so far MMC has not been widely used in motor drives applications. Since the capacitor voltage fluctuation is proportional to the output current amplitude and inversely proportional to the output frequency under constant torque load, at the low-speed, the excessive sub-module (SM) capacitor voltage fluctuation is one of the major obstacles for MMC applied in motor drives. To suppress the SM capacitor voltage fluctuation, an effective solution is to inject a high frequency zero sequence voltage to the three-phase output voltages of MMC and control the circulating current per phase reasonably. However, the introduced high frequency and high amplitude common voltage at the motor side is harmful. In this paper, a hybrid MMC with cascaded full-bridge SMs (HMMC-CFB) topology is used in the medium-voltage motor drives. The high frequency and high amplitude common mode voltage is absorbed by the cascaded full-bridge SMs. Besides, the capacitor voltage fluctuations of each arm and the cascaded full-bridge SMs is easily limited within a reasonable range. Finally, the state space model of HMMC-CFB system is established and a stable state-error feedback control law is given. By the passive theory, the necessary and sufficient condition for the globally uniformly asymptotical stability of the HMMC-CFB closed-loop system is deduced. Simulation results confirm the superiority of this novel topology and the validity of the proposed control strategy.

A Novel Model Predictive Control via Optimized Vector Selection Method for Common-Mode Voltage Reduction of Three-Phase Inverters

In this paper, a novel model predictive control (MPC) via a double vector optimized selection method is proposed. The main idea of this method is for decreasing the high common-mode voltage of two-level inverter under balance situation, improve the tracking performance of the output current and decrease the high output current harmonic distortion rate. To solve the problem of increasing the value of total harmonic distortion (THD) due to the reduction of the available voltage vector, this method controls two voltage vectors in each sampling period for getting a better tracking performance of the output current. Simultaneously, compared with the adding virtual vector MPC method, which results in excessive switching losses, the proposed method defining the selection range of the second voltage vector. Only two voltage vectors adjacent to the first voltage vector can be selected so that the switching frequency can be greatly reduced. An experimental control platform based on Simulink-Real-Time system is presented for the further verification of the effectiveness of the proposed control method. The simulation and experimental results showed that the proposed method could effectively reduce the output common-mode voltage of the inverter. Simultaneously, the THD value and the switching loss are greatly reduced.

A three-dimensional active zero state PWM for common-mode voltage reduction of a three-phase four-leg voltage-source inverter

PurposeThis paper aims to investigate the common-mode voltage (CMV) issue of a three-phase four-leg voltage-source inverter. A new space vector modulation method, named as three-dimensional active zero state Pulse-width modulation (PWM) (3-D AZSPWM), is proposed to reduce the CMV level.Design/methodology/approachPWM is a general method to generate the switching signals of the power converters in order to obtain high-quality output voltages. However, the CMV produced by PWM methods has become a serious problem. 3-D AZSPWM is proposed to solve this issue. In 3-D AZSPWM, instead of using zero voltage vectors with high CMV level, appropriate complementary non-zero vectors are introduced to synthesize reference vector. The proposed method is classified into four types of AZSPWM1(a), AZSPWM1(b), AZSPWM2(a) and AZSPWM2(b) based on different complementary vectors chosen for each type. An extend software simulation using MATLAB/Simulink is performed to verify the superior performance of the proposed methods.FindingsCompared to other reduced CMV methods, the proposed method not only reduces the CMV but also retains the positive characteristics of the three-dimensional classical space vector PWM (3-D CSVPWM).Originality/valueThe proposed method does not suffer from linear modulation region limitation and also does not impose additional switching loss. Furthermore, calculated output voltage harmonic distortion factor illuminates acceptable quality of output voltage produced by the proposed method.

High-Precision Electrical Impedance Tomography Data Acquisition System for Brain Imaging

In electrical impedance tomography (EIT), it is difficult to obtain the intracranial impedance due to the highly resistive skull enclosing the brain. Therefore, a high-precision data acquisition system is required for brain EIT. In this paper, we used a high-precision digital synthesis method and a digital demodulation technique with high noise immunity to eliminate random errors. Moreover, we focused on two problems encountered during EIT data acquisition: 1) the shunt effect on the excitation current due to the distributed capacitance between electrodes and ground and 2) high common-mode voltages in the boundary measurements. We designed a new electrode interface to reduce the influence of the distributed capacitance and a programmable current source to accurately compensate for the excited current. We also proposed a new voltmeter circuit with improved CMRR. Overall, this EIT data acquisition system can produce a programmable current with SNR greater than 89 dB. It can also measure the voltage difference precisely with CMRR higher than 75 dB with a 1- $\text{k}\Omega $ impedance imbalance. The results on a calibration model show that this system has a high SNR of 83 dB and a low reciprocity error of 0.125%. In addition, EIT imaging results were acquired using a brain physical phantom. The system can detect small disturbances of 0.35% in volume (1.99% of the cross-sectional area) and 17% in resistivity. Experiments on healthy volunteers also suggest that small intracranial impedance variations due to temporary occlusion and reperfusion of the unilateral carotid artery may be monitored by the system.

Application Analysis of AD8479 in the Acquisition Unit of Electronic Current Transformer

Electronic current transformer acquisition unit was installed outdoors and near the circuit breaker. The poor environments, including high common mode voltage, electromagnetic interference and other factors were a serious of disadvantages impacts on the acquisition unit. The paper introduced the parameter characteristics and functions of Rogowski coil, the differential amplifier chip AD8479, and filter circuit in detail. The application circuit was designed based on proper parameters. Lastly, the interference was inhibited effectively, and the electronic current transformer acquisition unit run more reliably resulted from theoretical analysis and field test.