High-bandwidth Connectivity Research Articles

Architectural issues related to the optical implementation of an EGS network based on embedded control

Free-space optical implementations of switching networks have been proposed to circumvent many of the system-level problems that may be encountered in systems that require many high-density, high-bandwidth connections. The details of a new class of switching network (the EGS network), that is well-suited to free-space implementations, is described. The common control injection problem that plagues most free-space photonic networks, i.e. how can control information from an electronic source be injected into the network for applications that require relatively high network reconfiguration rates, is examined. A new technique for control injection, called embedded control, which permits network operation even with relatively high network reconfiguration rates is also proposed.

A display system for the Stellar graphics supercomputer model GS1000

This paper describes a high performance display system that has been incorporated into the overall architecture of the Stellar Graphics Supercomputer Model GS1000. The display system is tightly coupled to the CPU, memory system and vector processing unit of this supercomputer, and is capable of rendering 150,000 shaded triangles/sec, and 600,000 short vectors/sec. The goal of the architecture is to share hardware resources between the CPU and display system and achieve a high bandwidth connection between them. This coupling of the display system and the processor, the architecture of the rendering processor, and the two ASICs that are used to implement the rendering processor are described.In addition, the display system architecture is contrasted to other approaches to high performance graphics, and design trade-offs and possible extensions are described. The implementation of popular display algorithms on the architecture is discussed, and their performance specified. The reader is advised that Stellar Computer Inc. is seeking patent protection for work described in this paper.

Multiple Bus Architectures

A recent study noted that for shared memory multiprocessors the single system bus typically used to connect the processor to the memory is by far the most limiting resource, and system performance can be increased considerably by increasing the capacity of the bus. One way of increasing the bus capacity, and also the system's reliability and fault tolerance, is to increase the number of buses. In this article the authors discuss using multiple buses to provide highbandwidth connections between the processors and the shared memory, thereby allowing the construction of larger and more powerful systems than currently possible.