Hierarchical Test Generation Research Articles

Identifying Untestable Faults in Sequential Circuits Using Test Path Constraints

The paper proposes a hierarchical untestable stuck-at fault identification method for non-scan synchronous sequential circuits. The method is based on deriving, minimizing and solving test path constraints for modules embedded into Register-Transfer Level (RTL) designs. First, an RTL test pattern generator is applied in order to extract the set of all possible test path constraints for a module under test. Then, the constraints are minimized using an SMT solver Z3 and a logic minimization tool ESPRESSO. Finally, a constraint-driven deterministic test pattern generator is run providing hierarchical test generation and untestability proof in sequential circuits. We show by experiments that the method is capable of quickly proving a large number of untestable faults obtaining higher fault efficiency than achievable by a state-of-the-art commercial ATPG. As a side effect, our study shows that traditional bottom-up test generation based on symbolic test environment generation at RTL is too optimistic due to the fact that propagation constraints are ignored.

High-Level Test Synthesis With Hierarchical Test Generation for Delay-Fault Testability

A high-level test synthesis (HLTS) method targeted for delay-fault testability is presented in this paper. The proposed method, when combined with hierarchical test-pattern generation for embedded modules, guarantees a 100% delay test coverage for detectable faults in modules. A study on the delay testability problem in behavior level shows that low delay-fault coverage is usually attributed to the fact that a two-pattern test for delay testing cannot be delivered to modules under test in two consecutive cycles. To solve the problem, we propose an HLTS method that ensures that valid test pairs can be sent to each module through synthesized circuit hierarchy. Experimental results show that this method achieves 100% fault coverage for transition faults in modules; in contrast, the fault coverage in circuits synthesized by a left-edge-algorithm-based allocation algorithm is rather poor. The area overhead due to this method ranges from 1% to 10% for 16-b datapath circuits. On the other hand, hierarchical test patterns cannot provide good delay-fault coverage for faults in interconnection structure and registers. The reason is that some control sequences required for delay-fault detection cannot be provided by the controller. We propose two design-for-testability insertion methods to deal with this problem. Experimental results show that, on the average, at least 11% higher delay-fault coverage is achieved by these methods.

Non-scan Design for Single-Port-Change Delay Fault Testability

We propose a non-scan design-for-testability (DFT) method at register-transfer level (RTL) based on hierarchical test generation: the DFT method makes paths in a data path single-port-change (SPC) two-pattern testable. For combinational logic in an RTL circuit, an SPC two-pattern test launches transitions at the starting points of paths corresponding to only one input port (an input, which has some bits, of an RTL module) and sets the other ports stable. Hence, during test application, the original hold function of a register can be used for stable inputs if the hold function exists. Our DFT method can reduce area overhead compared to methods that support arbitrary two-pattern tests without losing the quality of robust test and non-robust test. Experimental results show that our method can reduce area overhead without losing the quality of test. Furthermore, we propose a method of reducing over-test by removing a subset of sequentially untestable paths from the target of test.

A nonscan DFT method for RTL circuits based on fixed‐control testability

AbstractIn this paper, we will newly define the fixed‐control testability as the property of the data paths for which the hierarchical test generation is easy; and based on it we will propose a design for testability (DFT) method for register transfer level (RTL) circuits. In the proposed method, since it is based on the hierarchical test generation using combinational test generation method and nonscan design, the test generation time and test execution time can be shortened drastically compared to the full‐scan design method, and the test at real operation speed (at‐speed test) is possible; and the complete fault detection efficiency can be guaranteed. Moreover, the effectiveness of the proposed method will be shown by experiments using benchmark circuits. © 2003 Wiley Periodicals, Inc. Electron Comm Jpn Pt 3, 86(10): 43–55, 2003; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecjc.10119

A Hierarchical Test Generation Approach Using Program Slicing Techniques on Hardware Description Languages

Sequential Automatic Test Pattern Generation is extremely computation intensive and produces acceptable results only on relatively small designs. Hierarchical approaches that target one module at a time and use ad-hoc abstractions for the rest of the design, have shown promising results in reducing the test generation complexity. This paper develops an elegant theoretical basis, based on program slicing, for hierarchical test generation. The technique to systematically obtain a “constraint slice” for each embedded module under test within a design, is described in detail. The technique has been incorporated in an automated tool for Verilog designs, and results on large benchmark circuits show the significant benefits of the approach.

Statistical Tolerance Analysis for Assured Analog Test Coverage

Increasing numbers of analog components in today's systems necessitate system level test composition methods that utilize on-chip capabilities rather than solely relying on costly DFT approaches. We outline a tolerance analysis methodology for test signal propagation to be utilized in hierarchical test generation for analog circuits. A detailed justification of this proposed novel tolerance analysis methodology is undertaken by comparing our results with detailed SPICE Monte-Carlo simulation data on several combinations of analog modules. The results of our experiments confirm the high accuracy and efficiency of the proposed tolerance analysis methodology.

Hierarchical test generation for combinational circuits with real defects coverage

This paper deals with the automatic test pattern generation (ATPG) technique at the higher level using a functional fault model and defect-fault relationship in the form of a defect coverage table at the lower level. The paper contributes to test pattern generation (TPG) techniques taking into account physical defect localisation. A new parameter––probabilistic effectiveness of input patterns––has been used in the TPG technique with the goal of increasing real defect coverage. This parameter is based on probabilities of physical defects in digital cells which may occur in real integrated circuits. This improvement has been implemented into the existing DefGen ATPG system for combinational circuits.

Fast Hierarchical Test Path Construction for Circuits with DFT-Free Controller-Datapath Interface

Hierarchical approaches address the complexity of test generation through symbolic reachability paths that provide access to the I/Os of each module in a design. However, while transparency behavior suitable for symbolic design traversal can be utilized for constructing reachability paths for datapath modules, control modules do not exhibit transparency. Therefore, incorporating such modules in reachability path construction requires exhaustive search algorithms or expensive DFT hardware. In this paper, we discuss a fast hierarchical test path construction method for circuits with DFT-free controller-datapath interface. A transparency-based RT-Level hierarchical test generation scheme is devised for the datapath, wherein locally generated vectors are translated into global design test. Additionally, the controller is examined through the introduced concept of influence tables, which are used to generate valid control state sequences for testing each module through hierarchical test paths. Fault coverage and vector count levels thus attained match closely those of traditional test generation methods, while sharply reducing the corresponding computational cost and test generation time.

A hierarchical test generation approach for large controllers

A testing approach targeted at Hardware Description Language (HDL)-based specifications of complex control devices is proposed. For such architectures, gate-level test pattern generators require insertion of scan paths to enable the flat gate-level representations to be efficiently handled. In contrast, we present a testing methodology based on the hierarchical finite state machine model. Our approach allows the generation of compact test sets with very high stuck-at fault coverages, without any design-for-testability logic other than hardware reset. This method can be used any time the functional information is available together with the gate-level structural description. High fault coverages are achieved with smaller test lengths and execution times with respect to state-of-the-art gate-level test pattern generators.

Hierarchical test generation and design for testability methods for ASPPs and ASIPs

In this paper, we present design for testability (DFT) and hierarchical test generation techniques for facilitating the testing of application-specific programmable processors (ASPPs) and application-specific instruction processors (ASIPs). The method utilizes the register-transfer level (RTL) circuit description of an ASPP or ASIP to come up with a set of test microcode patterns which can be written into the instruction read-only memory (ROM) of the processor. These lines of microcode dictate a new control/data flow in the circuit and can be used to test modules which are not easily testable. The new control/data flow is used to justify precomputed test sets of a module from the system primary inputs to the module inputs and propagate output responses from the module output to the system primary outputs. The testability analysis, which is based on the relevant control/data flow extracted from the RTL circuit, is symbolic. Thus, it is independent of the bit-width of the data path and is extremely fast. The test microcode patterns are a by-product of this analysis. If the derived test microcode cannot test all untested modules in the circuit, then test multiplexers are added (usually to the off-critical paths of the data path) to test these modules. This is done to guarantee the testability of all modules in the circuit. If the control microcode memory of the processor is erasable, then the test microcode lines can be erased once the testing of the chip is over. In that case, the DFT scheme has very little overhead (typically less than 1%). Otherwise, the test microcode lines remain as an overhead in the control memory. The method requires the addition of only one external test pin. Application of this technique to several examples has resulted in a very high fault coverage (above 99.6%) for all of them. The test generation time is about three orders of magnitude smaller compared to an efficient gate-level sequential test generator. The average area overhead (without assuming an erasable ROM) is 3.1% while the delay overheads are negligible. This method does not require any scan in the controller or data path. It is also amenable to at-speed testing.

Integration of hierarchical test generation with behavioral synthesis of controller and data path circuits

This paper describes the first behavioral synthesis system that incorporates a hierarchical test generation approach to synthesize area-efficient and highly testable controller/data path circuits. Functional information of circuit modules is used during the synthesis process to facilitate complete and easy testability of the data path. The controller behavior is taken into account while targeting data path testability. No direct controllability of the controller outputs through scan or otherwise is assumed. The test set for the combined controller/data path is generated during synthesis in a very short time. Near 100% testability of combined controller and data path is achieved. The synthesis system easily handles large bit-width data path circuits with sequential loops and conditional branches in their behavioral specification, and scheduling constructs like multicycling, chaining and structural pipelining. An improvement of about three to four orders of magnitude was usually obtained in the test generation time for the synthesized benchmarks as compared to an efficient gate-level sequential test generator. The testability overheads are almost zero. Furthermore, in many cases at-speed testing is also possible.

Hierarchical robust test generation for CMOS circuit stuck-open faults

As VLSI circuits become very large the complexity of test derivation becomes tremendous. The performance of test derivation can be improved significantly by exploiting the hierarchical structure found in most realistic circuits and supported by current computer-aided design systems. In this direction, a new hierarchical test generation methodology for transistor stuck-open (TSOP) faults in combinational CMOS circuits, is presented. The contribution of this work is twofold. For the designer of the CMOS cells we give a method, based on the Karnaugh map, to generate the sufficient test information for the CMOS cells, and for the designer of a VLSI circuit consisting of these CMOS cells we give a method to generate robust two-pattern tests for the whole VLSI circuit exploiting the test information given for any one of the used CMOS cells.

Hierarchical test generation under architectural level functional constraints

In hierarchical test generation, the test vectors for the low level structure of the module under test are computed and then justified at a high level. In the module test computation procedure, a low level ATPG tool is conventionally applied to the complete structure of that particular module without adding extra information. Due to the architectural level functional constraints applied to the inputs of that module, many of the test vectors being computed are not justifiable at the high level. Therefore, high efficiency cannot be achieved without managing the functional constraint problem in the hierarchical ATPG process. In this paper, both top-down and bottom-up approaches are addressed. It is shown that the valid control code abstraction and test cube justification techniques are very effective to overcome the architectural level functional constraint problem and to achieve high efficiency in test computation. The proposed algorithms have been implemented in our hierarchical ATPG package and promising experimental results have been derived. We conclude that architectural level functional constraints can be efficiently avoided through these techniques.

Hierarchical test pattern generation: a cost model and implementation

A cost model for and implementation of a hierarchical test generation technique are presented. The cost model is based on fundamental test generation activities such as implication, justification, and backtracking. The model shows that the cost of hierarchical test generation grows as G log G under some realistic assumptions, while the cost of gate-level test generation may grow as fast as G/sup 2/, where G is the number of gates in a circuit under test. This implies that hierarchical test generators should be much faster than flat test generators on large circuits. The implementation of the hierarchical test generation is fan-out-oriented and uses a minimal hierarchical representation of the circuit and functional level heuristics to perform implication, propagation, and backtracing with high-level functional models. Experiments with three hierarchically described circuits show that hierarchical test generation is 1.5 to 8.9 faster than flat gate-level generation.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Temporal Logic Based Hierarchical Test Generationfor Sequential VLSI Circuits

Test generation for sequential VLSI circuits has remained a difficult problem to solve. The difficulty arises because of reasoning about temporal behavior of sequential circuits. We use temporal logic to model digital circuits. Temporal Logic can model circuits hierarchically. A set of heuristics is given to aid during test generation. A hierarchical test generation algorithm is proposed.

A framework and method for hierarchical test generation

The authors present an algorithm for hierarchical test generation based on module-oriented decision making (MODEM). The algorithm deals with combinational logic modules and the traditional single-stuck-at model. Modules and faults are captured at the function as well as the gate level. The benefits of hierarchy are realized by introducing a generic module representation and the concepts of a dynamic netlist and a dynamic calculus. The authors present the key elements of MODEM: the framework and fault targeting strategy, the module characterization, and a notation and calculus for module-oriented decision making. They conclude with a high-level view of MODEM implementation and experimental results on a variety of hierarchical benchmarks.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Designing for high-level test generation

Recent work has shown that test generation complexity and test set size can be reduced by high-level analysis that exploits the natural design hierarchy found in digital circuits. A design modification approach aimed at facilitating high-level testing by enhancing circuit regularity is proposed. This approach can improve the testability of a broad class of useful array- and tree-like circuits, including counters, decoders, and arithmetic logic units (ALUs). This is demonstrated for the specific case of decoders and decoding trees, where the test set size is reduced from O(2/sup n/) to O(n). A systematic design technique called level separation (LS) is presented for generalized tree circuits, which are useful for fast implementation of arithmetic functions like addition and multiplication. Design for testability (DFT) and hierarchical test generation are shown to reduce the test size from O(n) to O(log/sub 2/ n) for such circuits. A case study of a 16-b four-function ALU is presented to illustrate the utility of the LS method. >

A hierarchical test generation methodology for digital circuits

A new hierarchical modeling and test generation technique for digital circuits is presented. First, a high-level circuit model and a bus fault model are introduced—these generalize the classical gate-level circuit model and the single-stuck-line (SSL) fault model. Faults are represented by vectors allowing many faults to be implicitly tested in parallel. This is illustrated in detail for the special case of array circuits using a new high-level representation, called the modified pseudo-sequential model, which allows simultaneous test generation for faults on individual lines of a multiline bus. A test generation algorithm called VPODEM is then developed to generate tests for bus faults in high-level models of arbitrary combinational circuits. VPODEM reduces to standard PODEM if gate-level circuit and fault models are used. This method can be used to generate tests for general circuits in a hierarchical fashion, with both high- and low-level fault types, yielding 100 percent SSL fault coverage with significantly fewer test patterns and less test generation effort than conventional one-level approaches. Experimental results are presented for representative circuits to compare VPODEM to standard PODEM and to random test generation techniques, demonstrating the advantages of the proposed hierarchical approach.