Hierarchical Interconnection Network Research Articles

Reliable and fast reconfigurable hierarchical interconnection networks for linear WSI arrays

A self-pruning binary tree (SPBT) interconnection network architecture that tolerate faults in a wafer scale integration (WSI) environment is proposed. The goal of the SPBT network is to provide a reliable and a quickly reconfigured interconnection network architecture for linear WSI arrays. The proposed architecture uses a bottom-up approach to reconfigure a linear pipelined array on a potentially defective WSI array using a binary tree interconnection scheme. The binary tree is generated by successive formation of hierarchical modules. For N processing elements (PEs) on the wafer, reconfiguration time is O(log N). The propagation delay is bounded by Theta (log N) and is independent of the number of faulty PEs. Faults in the switching network as well as faulty processing elements are tolerated. >

Analysis of hierarchial bus-based multicomputer architectures

Hierarchical interconnection networks with cluster structure have been proposed for use in multicomputer systems for parallel and distributed processing. However, little attention has been paid to the study of the underline communication network at the message passing level. The main contribution of this paper is to present a performance model which relates the performance criteria with the architecture design and implementation, and to derive a method for optimizing the hierarchy in such systems. The proposed methodology can be easily augmented to include additional objectives and/or decision variables.

Hot-spot contention in binary hypercube networks

Consideration is given to the impact of hot-spot contention in distributed-memory multicomputer systems. Since the binary hypercube network offers a reasonable compromise between network cost and performance, two hypercube-based static interconnection networks are considered. One is a standard binary hypercube and the other is a binary hypercube-based hierarchical interconnection network. The impact of hot-spot contention in both these networks is studied. >

Performance analysis of a class of hierarchical hypercube multicomputer networks

Hierarchical interconnection networks (HINs) have been proposed to interconnect large numbers of processors in a multicomputer system. It has been shown that HINs provide better cost-benefit ratios than the corresponding nonhierarchical interconnection networks. This article discusses performance of two schemes that improve fault-tolerance of binary hypercube-based HINs. Both these schemes use hardware redundancy. In one, a standby-spare node is provided to reduce the impact of key node failures on the network reliability; in the other, a part of the network is duplicated. Both these schemes improve the network reliability substantially. The analysis presented here shows that, from a performance point of view. neither of the two schemes dominates the other for all parameter values and system characteristics. If the system supports applications that have varying degrees of communication locality and/or different computation-communication ratios, the duplication scheme is to be recommended. On the other hand, when applications exhibit high degrees of communication locality and high computation-communication ratios, the standby-spare node scheme provides better performance. The impact of three routing algorithms is also considered. We derive bounds on message delay and saturation message generation rate and compare the performance of these routing algorithms in achieving these bounds. It is shown by means of analytical and simulation models that performance of the replication scheme is less sensitive to the routing algorithm used.

On hypercube-based hierarchical interconnection network design

Hierarchical interconnection networks (HINs) have been proposed as a cost-effective way to interconnect large numbers of processors in a multicomputer system. This paper considers two issues concerning the design of binary hypercube-based HINs—the optimum cluster size and the optimum number of levels in the hierarchy. The network cost is measured in terms of the total link cost L and the performance of the network is measured by the average internode distance P. The goal is to minimize the cost-benefit ratio as represented by the LP product. The optimum cluster size is dependent on the underlying degree of locality in communication. For all of the various locality characterizations that we consider, the optimum cluster size in a two-level binary hypercube-based HIN, obtained numerically, is shown to be either 4 or 8, over a wide range of network sizes. It is shown that increasing the number of levels to 3 yields at most a moderate improvement in the cost-benefit ratio, depending on the type of locality characterization considered. For some locality characterizations, the cost-benefit ratio deteriorates. Thus, an appropriate design for a binary hypercube-based HIN appears to be a two-level hierarchy, with a cluster size of either 4 or 8.

Hierarchical interconnection networks for multicomputer systems

A performance analysis of a class of hierarchical interconnection networks is presented. The analysis includes both static analysis (i.e. queueing delays are neglected) and queueing analysis. In both cases, the hierarchical networks are shown to have better cost-benefit ratios. The queueing analysis is also validated by several simulation experiments. The impact of two performance enhancement schemes-replication of links and improved routing algorithms-on hierarchical interconnection network performance is also presented. >

High-Speed Packet Switching Systems for Multimedia Communications

High-speed packet switching (HPS) systems can Provide flexible, economical, high-quaiity services for integrated voice, video, and data communications. To realize such HPS systems, methods have been developed to bring about high-speed protocol processing as well as a system architecture for facilitating high-throughput switching. Adopting the parallel processing algorithm into protocol processing allows us to achieve high-speed packet protocol processing of about 100 times faster than conventional processing. Furthermore, a fully distributed system architecture in addition to hierarchical interconnection networks can achieve high-capacity packet switching systems. The proposed HPS system is thus capable of accommodating lines of up to 10-50 Mbits/s, of providing high-throughput switching capability of 1 000 000 packets/s, and of having an average delay of less than 2 ms. Furthermore, an evaluation of network delay performances of video conferencing and voice communications indicate that HPS systems are quite suitable for handling such multimedia communications.