Hierarchical Finite State Machine Research Articles

Acceleration of Recursive Data Sorting over Tree-based Structures

The main objective of this paper is to evaluate and improve FPGA-based digital circuits, which implement recursive specifications.Recursive sorting algorithms over binary trees are considered as a case study to evaluate and demonstrate new techniques and theiradvantages. Since recursive calls are not directly supported by hardware description languages, they are implemented using the model ofa hierarchical finite state machine (HFSM). The paper presents analysis and comparison of alternative and competitive techniques fordescribing recursive algorithms in hardware. The experimental results demonstrate that the proposed innovations allow to achieve betterperformance. Obviously, the results of this paper are not limited to recursive sorting alone. They have a wider scope and can be appliedeffectively to numerous systems that implement recursive algorithms over tree-based data structures. Ill. 8, bibl. 10, tabl. 2 (in English;abstracts in English and Lithuanian).http://dx.doi.org/10.5755/j01.eee.113.7.612

LHCb Silicon Tracker DAQ and ECS Online Systems

The LHCb experiment at CERN is designed to perform precision measurements of b quark decays. The Silicon Tracker plays a crucial role in reconstructing particle trajectories and consists of two silicon micro-strip detectors, the Tracker Turicensis and the Inner Tracker. The radiation environment and the magnetic field represent new challenges for the implementation of the Experiment Control System (ECS) and the data acquisition (DAQ). The DAQ has to deal with ~272 000 analog read-out channels and real-time DAQ at a rate of ~ 1.1 MHz with data processing at the Trigger Electronics and L1 (TELL1) board level. The TELL1 real-time algorithms for clustering thresholds and other computations run on dedicated FPGAs. After data processing the total throughput amounts to about 6.4 GB from an input data rate of ~ 337 GB per second. The ECS is based on the hierarchical finite state machine paradigm and allows distributed control access and multi-platform use. The ECS is able to control and monitor the detector hardware infrastructure (power supplies, DAQ electronics ...) as well as monitor the environmental parameters. It can also take automated actions on warnings or alarms. Finally a completely independent, hardware based safety system ensures the detector safe operation.

Low-Power Bitstream-Residual Decoder for H.264/AVC Baseline Profile Decoding

We present the design and VLSI implementation of a novel low-power bitstream-residual decoder for H.264/AVC baseline profile. It comprises a syntax parser, a parameter decoder, and an Inverse Quantization Inverse Transform (IQIT) decoder. The syntax parser detects and decodes each incoming codeword in the bitstream under the control of a hierarchical Finite State Machine (FSM); the IQIT decoder performs inverse transform and quantization with pipelining and parallelism. Various power reduction techniques, such as data-driven based on statistic results, nonuniform partition, precomputation, guarded evaluation, hierarchical FSM decomposition, TAG method, zero-block skipping, and clock gating, are adopted and integrated throughout the bitstream-residual decoder. With innovative architecture, the proposed design is able to decode QCIF video sequences of 30 fps at a clock rate as low as 1.5 MHz. A prototype H.264/AVC baseline decoding chip utilizing the proposed decoder is fabricated in UMC 0.18µm 1P6M CMOS technology. The proposed design is measured under 1 V ∼ 1.8 V supply with 0.1 V step. It dissipates 76µW at 1 V and 253µW at 1.8 V.

Diagnosability Analysis of a Class of Hierarchical State Machines

This paper addresses the problem of fault detection and isolation for a particular class of discrete event dynamical systems called hierarchical finite state machines (HFSMs). A new version of the property of diagnosability for discrete event systems tailored to HFSMs is introduced. This notion, called L1-diagnosability, captures the possibility of detecting an unobservable fault event using only high level observations of the behavior of an HFSM. Algorithms for testing L1-diagnosability are presented. In addition, new methodologies are presented for studying the diagnosability properties of HFSMs that are not L1-diagnosable. These methodologies avoid the complete expansion of an HFSM into its corresponding flat automaton by focusing the expansion on problematic indeterminate cycles only in the associated extended diagnoser.

Hierarchical Fault Diagnosis: Application to an Ozone Plant

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> A framework for diagnosis in hierarchical finite-state machines is presented and applied to an ozone plant. In this approach, the model of the system is broken into simpler substructures called D-holons. At any instant, instead of the complete system model, only the D-holons associated with the ongoing phase of operation are used for diagnosis, which reduces memory requirement. Furthermore, within the above setup, a semimodular diagnosis method is presented and used to reduce design computations. Following the proposed framework, a diagnosis system is designed for the ozone plant. It is shown that the proposed approach significantly reduces the complexity of constructing and storing the diagnosis system. </para>

ON THE DIAGNOSABILITY OF A CLASS OF HIERARCHICAL STATE MACHINES

This paper addresses the problem of Fault Detection and Isolation for a particular class of discrete event dynamic systems named Hierarchical Finite State Machines (HFSMs). A new version of the property of diagnosability for discrete event systems tailored to HFSMs is introduced. This notion, called L1-diagnosability, captures the possibility of detecting an unobservable fault event using only high level observations of HFSMs. Algorithms for testing L1-diagnosability are presented. In addition, guidelines are presented for studying the diagnosability of HFSMs that are not L1-diagnosable.

A NEW MODEL FOR HETEROGENEOUS EMBEDDED SYSTEMS — What Esterel and SyncCharts Need to Become a Suitable Specification Platform

Specification of embedded systems based on formal models of computation is gaining importance. The behavior of an increasing number of embedded systems is heterogeneous, consisting of a mixture of control-dominated and data-dominated parts. While models of computations suitable to control-dominated systems and data-dominated systems are well developed, there are only a limited number of models catering to both systems. In this paper, we present informally a new model for heterogeneous embedded systems, called HEMOC, which combines three common models of computation, synchronous reactive, hierarchical finite state machines and synchronous data flow. Then, the languages Esterel and SyncCharts are used for system specification following the new model in order to determine what they need to become suitable specification platform.

Komponento specifikacijos formalizavimas

This paper deals with the component specification and formalisation problems. It defines the notion of component model, gives the formalised concept of a component, compound component, and proposes to use hierarchical finite state machines as the formalism to specify component's life cycle.

FPGA-based implementation of recursive algorithms

The paper suggests a novel method for implementing recursive algorithms in hardware. The required support for recursion has been provided through a modular and a hierarchical specification of a control unit that can be translated to an implementation of the respective hardware circuit on the basis of a recursive hierarchical finite state machine and through a mechanism that permits the contents of an execution unit to be stored/restored between hierarchical calls/returns. The paper describes all the details that are required to implement recursive algorithms in hardware. It begins with software (C++) models and finishes with synthesizable VHDL codes. Two practical applications of recursive algorithms in the data sorting and compression area have been studied in detail.

FPGA-based implementation of recursive algorithms

The paper suggests a novel method for implementing recursive algorithms in hardware. The required support for recursion has been provided through a modular and a hierarchical specification of a control unit that can be translated to an implementation of the respective hardware circuit on the basis of a recursive hierarchical finite state machine and through a mechanism that permits the contents of an execution unit to be stored/restored between hierarchical calls/returns. The paper describes all the details that are required to implement recursive algorithms in hardware. It begins with software (C++) models and finishes with synthesizable VHDL codes. Two practical applications of recursive algorithms in the data sorting and compression area have been studied in detail.

Supervisory Control of Product and Hierarchical Discrete Event Systems

In this paper, the supervisory control of a class of discrete event systems (DES) is investigated. DES are modeled either by a collection of finite state machines (FSMs) that behave asynchronously or by a hierarchical finite state machine. The basic problem of interest is to ensure the invariance of a set of particular configurations in the system. When the system is modeled as asynchronous FSMs, we provide algorithms that, based on a particular decomposition of the set of forbidden configurations, solve the control problem locally (i.e. on each component without computing the whole system) and produce a global supervisor ensuring the desired property. We then provide sufficient conditions under which the obtained controlled system is non-blocking. This kind of objectives may be useful to perform dynamic interactions between different parts of a system. Finally, we apply these results to the case of hierarchical FSMs.

Formalisation of the knowledge used in design of software, information and business systems

This paper is devoted to the formalisation problems of design knowledge used in business sys­tems, information systems, and software design. It discusses the notions of knowledge and informa­tion, introduces the concept of ``know-how'' knowledge, and proposes to use hierarchical finite state machines as the unified formalism to specify business systems, information systems, and software design strategies.

Specifying requirements of real-time system with rules and templates

This paper presents a model specifying requirements of real-time systems. Different from existing researches, this model mainly uses rules and templates to represent hierarchical FSMs (Finite State Machine). In this model, one rule corresponds to one state transition of FSM and one template corresponds to one FSM. Rules and information with respect to a FSM can be written in a template. So templates include not only state diagrams, but also information that can not be described by FSM, such as performance requirements. The specification using this model consists of a collection of templates and it is easy for users to understand and to review. After introduced the related researches and principles of the model, this paper specifies requirements of a real-time system with this model, and discusses characters of this model in the end.

A hierarchical test generation approach for large controllers

A testing approach targeted at Hardware Description Language (HDL)-based specifications of complex control devices is proposed. For such architectures, gate-level test pattern generators require insertion of scan paths to enable the flat gate-level representations to be efficiently handled. In contrast, we present a testing methodology based on the hierarchical finite state machine model. Our approach allows the generation of compact test sets with very high stuck-at fault coverages, without any design-for-testability logic other than hardware reset. This method can be used any time the functional information is available together with the gate-level structural description. High fault coverages are achieved with smaller test lengths and execution times with respect to state-of-the-art gate-level test pattern generators.

Hierarchical finite-state machines and their use for digital control

This paper discusses the behavioral description, logic synthesis, and practical use of control units modeled as hierarchical finite-state machines with virtual states. The technique considered here provides a natural mechanism for top-down decomposition and enables us to develop any complex control algorithm step-by-step, where, at each stage, we are only dealing with a particular level of abstraction. Within any level, the specification encapsulates the control data and functions and allows recursive calls. Finally, the approach enables control units to be designed such that they incorporate new properties such as flexibility and extensibility. The primary functional components of a control algorithm can be reused in future applications.

Hierarchical finite state machines with multiple concurrency models

This paper studies the semantics of hierarchical finite state machines (FSM's) that are composed using various concurrency models, particularly dataflow, discrete-events, and synchronous/reactive modeling. It is argued that all three combinations are useful, and that the concurrency model can be selected independently of the decision to use hierarchical FSM's. In contrast, most formalisms that combine FSM's with concurrency models, such as statecharts (and its variants) and hybrid systems, tightly integrate the FSM semantics with the concurrency semantics. An implementation that supports three combinations is described.

Synthesis for testability of highly complex controllers by functional redundancy removal

This paper presents a testable synthesis methodology applicable to any top-down design method based on hardware-description-language descriptions, or graphical representations. The methodology is targeted on control-dominated applications and it is based on the identification and removal of a new class of redundant faults, called functionally redundant faults. The formal relation between functionally redundant faults and sequentially redundant faults is introduced. Moreover, the relation between functionally redundant faults and logic synthesis algorithms based on local don't cares is shown. Functionally redundant faults are identified and removed by comparing the implemented synchronous sequential circuit, which can be technology dependent, to its specification. The specification can be a single finite state machine (FSM), a set of interacting FSMs, or a hierarchical FSM that allows the description of highly complex controllers. The proposed methodology produces testable circuits, with area reduction, still mapped on the same technology library, and it manages circuits which cannot be handled by other methods presented in the literature.

Content-based visualization for intelligent problem-solving environments

Mechanisms are proposed to allow visualization to become an active agent in the problem-solving environment. Two main problems are addressed: dealing with too much data and allowing simulation steering. The agent solves these problems by extracting semantically interesting data for spatial and temporal understanding, enabling a dynamic and flexible behavior for simulation-integrated control, and intelligently creating visualizations that intuitively display the selected data. A significant event language is proposed to capture the semantically interesting data through event expressions which can then be parsed and monitored. Behavior is achieved through programmable, hierarchical finite-state machines with events mapped to the arcs and interactions with the visualization and simulation mapped to the nodes. A knowledge-based data mapping process has been designed which uses visual perceptual knowledge and problem-specific knowledge represented in cognitive maps to create visualizations. This architecture has been applied within a watershed simulation application and a prototype has been developed.