Hierarchical Fault Simulation Research Articles

MODULE LEVEL DEFECT SIMULATION IN DIGITAL CIRCUITS

A new method for parametric defect modelling is developed for calculating the conditions for activating physical defects in the modules (for example, in library components) of digital circuits. The method affords for the first time the possibility to handle the defects which increase the number of states in the circuit. By using the concept of functional faults, the new method of defect modelling by logic conditions is generalized for hierarchical fault simulation. A method is proposed to find the types of faults that may occur in a real circuit, to determine their probabilities, and to find the input test patterns that detect these faults. A new hierarchical defect- oriented fault simulation method is presented. At the higher (module) level simulation we use the functional fault model, at the lower level the defect/fault relationships in the form of defect coverage table and conditional defect probabilities. Experimental data of the hierarchical defect- oriented simulation for ISCAS'85 benchmarks are presented, which show that classical stuck-at fault based simulation and the test coverage calculation, based on counting defects without considering defect probabilities, may lead to considerable overestimation of results.

Concurrent Hierarchical Fault Simulation: A Performance Model and Two Optimizations

This paper presents the technique of concurrent hierarchical fault simulation, a performance model, and two hierarchical optimization techniques to enhance fault simulator performance. The mechanisms for these enhancements are demonstrated with a performance model and are validated experimentally via CHIEFS, the Concurrent Hierarchical and Extensible Fault Simulator, and WRAP, an offline hierarchy compressor. Hieararchy-based fault partitioning and circuit reconfiguration are shown to improve simulator performance to O(n log n) under appropriate conditions. A decoupled fault modeling technique permits further performance improvements via a bottom-up hierarchy compression technique where macros of primitives are converted to single primitives. When combined, these techniques have produced a factor of 180 speedup on a mantissa multiplier. The performance model indicates that the speedup should increase with circuit size.