HfO2 Charge Trapping Layer Research Articles

The Reliability Impact of Bi Doping on the HfO2 Charge-Trapping Layer: A First-Principles Study

The Reliability Impact of Bi Doping on the HfO2 Charge-Trapping Layer: A First-Principles Study

Electrical characterization of memory capacitors for nonvolatile memory applications based on nanolaminated HfO2/Al2O3 and Al-doped HfO2 stacks

Memory capacitors with atomic-layer-deposited HfO2/Al2O3 nanolaminated layers and Al-doped HfO2 charge trapping layers were investigated through capacitance-voltage (C-V) and current-voltage (I-V) measurements. The dielectric constant of the multi-dielectric stack comprising 20-nm Al2O3 blocking oxide, a HfO2-based layer and 2.4-nm tunnel SiO2 does not depend on the manner of Al-introduction in HfO2.The stacks exhibit a negative oxide charge of about -5.1×1011 cm−2 and -2.5×1011 cm−2 for the structures with nanolaminated and doped layers, respectively. The Al-doping of HfO2 is found to produce lower leakage currents. A sublinear behavior of the current-voltage curves is observed in the range of -20 ÷ +10 V for both HfO2-based stacks. Memory windows of ∼ 1 V when charging with ±27-V voltage pulses are obtained; the data suggests that electron trapping is better pronounced in the HfO2/Al2O3 nanolaminate, while positive charge accumulation prevails in the Al-doped HfO2 layers.

Analysis of HfO2 Charge Trapping Layer Characteristics After UV Treatment

The improvement in the charge storage characteristics in a non-volatile memory (NVM) device employing an ultraviolet (UV)-treated hafnium oxide (HfO2) layer as the charge-trapping layer is reported. X-ray photoelectron spectroscopy analysis was performed to characterize the Hf 4f and O 1s peaks. The defect densities corresponding to Hf and O after short-term UV treatment are 24.74% and 14.16%, respectively. The electrical characteristics, such as the interface trap density (Dit), dielectric constant, and flat band voltage (VFB), of single HfO2 thin films were determined via capacitance vs voltage (C–V) measurements of the fabricated metal–oxide–semiconductor (MOS) capacitors. Notably, this memory device has a maximum ΔVth of 4.10 V at 15 V, which corresponds to a 33.4% improvement in memory storage characteristics compared to those of an as-deposited HfO2 thin film-based memory. In addition, the charge retention after 10 years is 80.22%, which is superior to that of the as-deposited case. These results demonstrate the possibility of realizing high-efficiency TFT NVM devices using high-K materials, and are expected to enable further research on semiconductor devices using high-K materials as well as next-generation memory semiconductors using UV treatment.

Improving the Performance of Charge Trapping Memtransistor as Synaptic Device by Ti-Doped HfO2

In this work, we improved the performance of germanium (Ge) channel Charge Trapping MemTransistors (CTMTs) as synaptic device by using Ti-doped HfO2 as charge trapping layer (CTL). We manipulated the amount of Ti dopant within the HfO2 CTL to perform the band engineering by varying the Hf/Ti cycle ratio in atomic layer deposition (ALD). The content of Ti was quantified and the energy band structures of the gate stack was constructed with the aid of transmission electron microscope (TEM) images and X-ray photoelectron spectroscopy (XPS) analysis. We then fabricated the charge trapping capacitors and characterized their memory characteristics such as memory windows. By the implementation of amphoteric trap model, thermal activated electron retention model and advanced charge decay model, the trap distribution of the CTL was extracted. Finally, we fabricated the CTMTs with Ti-doped HfO2 as the CTL and characterized their performance as synaptic device such as nonlinearity of depression and potentiation and also conductance on/off ratio. We used NeuroSim simulator with multilayer perceptron and convolutional neural network models to evaluate the pattern recognition accuracy of neural network hardware accelerator using CTMTs as synaptic devices and benchmarked the performance of our CTMT with those of other types of synaptic devices.

Fabrication and Characterization of p-Channel Charge Trapping Type FOI-FinFET Memory with MAHAS Structure

A type of p-channel fin-on-insulator (FOI) FinFET charge trapping memory devices with HfO2 charge trapping layer, Al2O3 tunneling layer and blocking layers along with [TiN/W] metal gate (Metal/Al2O3/HfO2/Al2O3/Si, named as MAHAS in short) have been successfully fabricated. It is found that the new non-volatile memory, named in FOI-MAHAS memory shows better performance as compared with counterparts reported earlier owing to the adoption of p-type FOI channel and specific high-κ dielectrics. The static DC electrical characteristics of the fabricated memory devices including threshold voltage, subthreshold slope, gate breakdown voltage (BVg), source-drain breakdown voltage (BVDS) and memory characteristics such as program/erase (P/E) speed, memory window, endurance, and data retention at room temperature with different P/E approaches have been systematically investigated. A larger memory window, lower P/E voltages, improved P/E speed, as well as good data retention and endurance characteristics with band-to-band hot-electron (BBHE) programming are experimentally obtained. The developed p-channel FOI-MAHAS charge trapping memory is promising for the future nano-scaled NOR-type flash memory applications.

Effects of Composition on the Memory Characteristics of (HfO2)x(Al2O3)1-xBased Charge Trap Nonvolatile Memory

According to the 2012 International Technology Roadmap for Semiconductors (ITRS) [1], the conventional floating gate nonvolatile semiconductor memories (FG-NVSM) are approaching their scaling limitation; moreover, new materials and technology are required in order to explore the novel solid state nonvolatile memory device with the desired characteristics, such as the low-cost, high-density and a fast program/erase (P/E) speed for use in mobile electronics [2-5]. For conventional FG-NVSM devices, the charges are stored in a conducting poly-silicon gate, and a single defect in the tunneling layer can discharge the whole memory due to the scaling thickness of the tunneling layer. Based on the concept, that charges are stored in discrete traps within the charge trapping layer, silicon-oxide-nitrideoxide-silicon (SONOS) charge trap flash (CTF) memories with nitride (Si3N4), as the charge trapping layer, have attracted much attention for commercial applications in order to replace the conventional FG-NVSM devices due to lower operating voltage, excellent endurance, smaller size and compatibility with standard CMOS technology [6]. However, one problem in the SONOS memory device is the small conduction band offset between the Si3N4 and the tunneling layer [7], which leads to poor retention characteristics. In order to solve the problem, employing high-k dielectrics, as the charge trapping layer in the SONOS structure, has been reported by many researchers [8-14]. The charge memory structure with a pure HfO2 charge trapping layer demonCharge trap flash memory capacitors incorporating (HfO2)x(Al2O3)1-x film, as the charge trapping layer, were fabricated. The effects of the charge trapping layer composition on the memory characteristics were investigated. It is found that the memory window and charge retention performance can be improved by adding Al atoms into pure HfO2; further, the memory capacitor with a (HfO2)0.9(Al2O3)0.1 charge trapping layer exhibits optimized memory characteristics even at high temperatures. The results should be attributed to the large band offsets and minimum trap energy levels. Therefore, the (HfO2)0.9(Al2O3)0.1 charge trapping layer may be useful in future nonvolatile flash memory device application.

Normally‐off AlGaN/GaN MOSHFET using ALD SiO2 tunnel dielectric and ALD HfO2 charge storage layer for power device application

AbstractIn this work, we have demonstrated a normally‐off AlGaN/GaN metal‐oxide semiconductor heterojunction field effect transistor (MOSHFET) wherein the enhancement mode operation is enabled by charge storage characteristics within a high‐k layer. By combining ALD SiO2 tunnel dielectric and HfO2 charge trapping layer, up to 7 V of threshold voltage (VT) shift depending on the applied gate pulse amplitude (corresponding ∼ 1.2 × 1013 charges/cm2 stored within the charge storage layer) is obtained. Electrical characteristics such as gate leakage current, transconductance, and off‐state breakdown after programming are similar to the initial device. Retention characteristics show about 20% of charge loss after 20000 s. (© 2012 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Nonvolatile Poly-Si TFT Charge-Trap Flash Memory With Engineered Tunnel Barrier

Tunnel-barrier-engineered thin-film transistor (TFT) memory (TBE-TFT memory) devices on glass substrates were fabricated using low-temperature processes. An amorphous silicon film on the glass substrate was crystallized using excimer laser annealing for system-on-panel applications. The engineered tunnel barrier of VARIOT type (SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> /SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ) with a high- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> charge-trapping layer and an Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> blocking layer was applied to TBE-TFT memory devices in order to enhance the memory performance of TBE-TFT memory devices. As a result, the poly-Si TFT charge-trap Flash memory with an engineered tunnel barrier exhibited excellent memory characteristics, such as large memory window (9.5 V), long retention time, and endurance.

Fabrication, characterization and simulation of high performance Si nanowire-basednon-volatile memory cells

We report the fabrication, characterization and simulation of Si nanowire SONOS-like non-volatile memorywith HfO2 charge trapping layers of varying thicknesses. The memory cells, which arefabricated by self-aligning in situ grown Si nanowires, exhibit high performance,i.e. fast program/erase operations, long retention time and good endurance.The effect of the trapping layer thickness of the nanowire memory cells hasbeen experimentally measured and studied by simulation. As the thickness ofHfO2 increases from 5 to 30 nm, the charge trap density increases as expected,while the program/erase speed and retention remain the same. These dataindicate that the electric field across the tunneling oxide is not affected byHfO2 thickness, which is in good agreement with simulation results. Our work also shows thatthe Omega gate structure improves the program speed and retention time for memoryapplications.

Comprehensive Study of Pi-Gate Nanowires Poly-Si TFT Nonvolatile Memory With an HfO $_2$ Charge Trapping Layer

This work demonstrates the feasibility of a polycrystalline silicon thin-film transistor (poly-Si TFTs) nonvolatile memory (NVM) that utilizes a Pi-shaped gate (Pi-gate) and multiple nanowire channels with a HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> charge-trapping layer. The TFT NVM with the Pi-gate nanowires (NWs) structure has a higher program/erase (P/E) efficiency than that of the conventional single-channel TFT NVM; the memory window can achieve 2.3 V, only needs a programming time of 1 μs. This high P/E efficiency follows from the improved gate control of the Pi-gate structure. A Pi-gate NWs poly-Si TFT NVM with a Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> charge-trapping layer was also fabricated. Since HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> has a deeper conduction band than Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> , the device with the HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> charge-trapping layer has a higher programming efficiency and the better retention characteristics than that with the Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> charge-trapping layer. Additionally, the high programming efficiency allows the device with the HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> charge-trapping layer to undergo more P/E cycles than that with the Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> charge-trapping layer.

Polycrystalline Silicon Thin-Film Flash Memory with Pi-Gate Structure and HfO2 Charge Trapping Layer

This work demonstrates a polycrystalline silicon (poly-Si) thin-film flash nonvolatile memory (NVM) that utilized Pi-shaped gate (Pi-gate) multiple nanowire channels with an HfO2 charge trapping layer. The Pi-gate nanowires (NWs) flash NVM has higher program/erase (P/E) efficiency than the conventional memory with single-channel (SC) structure. This high P/E efficiency is due to the better gate control of the Pi-gate structure. As a result of the high P/E speed, up to 105 P/E cycles can be realized. The HfO2 charge trapping layer has a deep conduction band and spatial isolated traps. These characteristics result in good data retention, only 10% charge loss after 109 s.

Multistacked Al2O3∕HfO2∕SiO2 tunnel layer for high-density nonvolatile memory application

A memory capacitor with a multistacked tunnel layer of Al2O3∕HfO2∕SiO2 (AHO) has been fabricated together with HfO2 charge trapping layer and Al2O3 control oxide layer. The resulting capacitor exhibits a memory window as large as 7.6V for ±12V sweep voltage range, a significant flatband voltage shift of 2.1V after 10V∕100μs programing as well as improved charge retention compared with a single SiO2 tunnel layer. The different memory effects in various sweep voltage ranges and enhanced retention characteristics have been explained based on the variable electrical thickness of the AHO stack under different electric fields.

SONOS-type flash memory using an HfO/sub 2/ as a charge trapping layer deposited by the sol-gel spin-coating method

In this letter, the authors fabricate the silicon-oxide-nitride-oxide-silicon (SONOS)-like memory using an HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> as charge trapping layer deposited by a very simple sol-gel spin-coating method and 900 degC 1-min rapid thermal annealing. They examine the quality of sol-gel HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> charge trapping layer by X-ray photoemission spectroscopy, Id-Vg, charge retention, and endurance. The threshold voltage shift is 1.2 V for the sol-gel HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> trapping layer. The sol-gel HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> film can form a deep trap layer to trap electrons for the SONOS-like memory. Therefore, the sol-gel device exhibits the long charge retention time and good endurance performance. The charge retention time is 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4 </sup> s with only 6% charge loss and long endurance program/erase cycles up to 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sup>