HfO2-based Ferroelectric Field-effect Transistors Research Articles

Coupling effects of interface charge trapping and polarization switching in HfO2-based ferroelectric field effect transistors

HfO2-based ferroelectric field-effect transistors (FeFETs) are regarded as one of the most promising non-volatile memory technologies in the future. However, the charge trapping phenomenon during the program/erase operation is still a challenge. In this work, we comprehensively investigate the behaviors of semiconductor/insulator interface charge trapping in HfO2-based FeFETs. Through analyzing the effects of the spatial distribution of interface traps and the polarization switching speed, the coupling effects of semiconductor/insulator interface charge trapping and polarization switching are recognized. We also find that the band tail state traps have much less influence on the electrical characteristics of the FeFETs than the deep level state traps. Through engineering the devices with band tail state traps with concentrations as small as possible, the influences of charge trapping could be effectively suppressed. Moreover, the gate voltage (VG) scanning rate has a significant influence on the interface charge trapping process due to the time dependent change of ferroelectric polarization. The largest memory window could be obtained by carefully choosing the VG scanning rate of the FeFETs based on the polarization switching speed. This work represents a key step for realizing highly reliable HfO2-based FeFETs.

Impact of multi-domain effect on the effective carrier mobility of ferroelectric field-effect transistor

HfO2-based ferroelectric field-effect transistors (FeFETs) are a promising candidate for multilevel memory manipulation and brain-like computing due to the multi-domain properties of the HfO2 FE films based polycrystalline structure. Although there have been many reports on the working mechanism of the HfO2-based FeFET and improving its reliability, the impact of multi-domain effect on the effective carrier mobility (μ channel) has not been carried out yet. The effective μ channel determines the level of readout current and affects the accuracy of the precision of peripheral circuit. In this work, FeFETs with HfZrO x FE gate dielectric were fabricated, and the effect of write (or erase) pulses with linear gradient variation on the effective μ channel was studied. For the multiple downward polarization under write pulses, the μ channel degrades as the domains gradually switch to downward. This is mainly due to the enhancement of the scattering effect induced by the positive charges (e.g. oxygen vacancies ) trapping and the increase of channel carrier density. For the erase pulses, the μ channel increases as the domains gradually reverse to upward, which is mainly due to the reduction of the scattering effect induced by the detrapping of positive charges and the decrease of channel carrier density. In addition, the modulation effect of multilevel polarization states on μ channel is verified by numerical simulation. This effect provides a new idea and solution for the development of low power HfO2-based FeFETs in neuromorphic computing.

Ultralow Subthreshold Swing of a MOSFET Caused by Ferroelectric Polarization Reversal of Hf0.5Zr0.5O2 Thin Films.

The emergence of complementary metal-oxide semiconductor (CMOS)-compatible HfO2-based ferroelectric materials provides a promising way to achieve ferroelectric field-effect transistors (FeFETs) with a steep subthreshold swing (SS) reduced to below the Boltzmann thermodynamics limit (∼60 mV/dec at room temperature), which has important implications for lowering power consumption. In this work, a metal-oxide-semiconductor field-effect transistor (MOSFET) is connected with Hf0.5Zr0.5O2 (HZO)-based ferroelectric capacitors with different capacitances. By adjusting the capacitance of ferroelectric capacitors, an ultralow SS of ∼0.34 mV/dec in HfO2-based FeFETs can be achieved. More interestingly, by designing the sweeping voltage sequences, the SS can be adjusted to be 0 mV/dec with the drain current ranging over six orders of magnitude, and the threshold voltage for turning on the MOSFET can be further reduced. The manipulated SS could be attributed to the evolution of ferroelectric switching. Our work contributes to understanding the origin of ultralow SS in ferroelectric MOSFETs and the realization of low-power devices.

Effects of Charge Trapping on Memory Characteristics for HfO2-Based Ferroelectric Field Effect Transistors.

A full understanding of the impact of charge trapping on the memory window (MW) of HfO2-based ferroelectric field effect transistors (FeFETs) will permit the design of program and erase protocols, which will guide the application of these devices and maximize their useful life. The effects of charge trapping have been studied by changing the parameters of the applied program and erase pulses in a test sequence. With increasing the pulse amplitude and pulse width, the MW increases first and then decreases, a result attributed to the competition between charge trapping (CT) and ferroelectric switching (FS). This interaction between CT and FS is analyzed in detail using a single-pulse technique. In addition, the experimental data show that the conductance modulation characteristics are affected by the CT in the analog synaptic behavior of the FeFET. Finally, a theoretical investigation is performed in Sentaurus TCAD, providing a plausible explanation of the CT effect on the memory characteristics of the FeFET. This work is helpful to the study of the endurance fatigue process caused by the CT effect and to optimizing the analog synaptic behavior of the FeFET.

Robustly Stable Ferroelectric Polarization States Enable Long-Term Nonvolatile Storage against Radiation in HfO2-Based Ferroelectric Field-Effect Transistors.

The ferroelectric field-effect transistors (FeFETs) with HfO2-based ferroelectric layers in the gate stacks are emerging as one of the most promising candidates for the next-generation nonvolatile memory devices due to their scalability and compatibility with conventional Si technology. Moreover, owing to the high radiation hardness of the HfO2-based ferroelectric thin films, HfO2-based FeFETs have attracted great interest in the fields of radiation-hard (rad-hard) memory. However, the reliability of their memory states under irradiation, which represents the validity of the stored information, has not been investigated. Here, we focus on the impact of the total ionizing dose (TID) on erased and programmed states of HfO2-based FeFETs. The TID radiation (X-ray) characteristics of erased and programmed HfO2-based FeFETs are characterized using an on-site read operation. Both the erased and programmed states show robust stability under irradiation at a dose rate of 90 rad(Si)/s, and even at 230 rad(Si)/s, only the erased state shows a slight variation. The possible factors contributing to memory state degradation are discussed. Through the analysis of the threshold voltage shift and subthreshold swing evolution, as well as studies of ferroelectric polarization stability under radiation, it is revealed that the erased state degradation is caused by oxide-trapped charges rather than interface degradation or polarization switching. The physical mechanism of the difference in radiation-induced oxide-trapped charges buildup in programmed and erased FeFETs is analyzed to explain different TID radiation characteristics between them. Our work suggests that the HfO2-based FeFETs have great potential in radiation environment applications.

Synergistic Approach of Interfacial Layer Engineering and READ-Voltage Optimization in HfO2-Based FeFETs for In-Memory-Computing Applications.

This article reports an improvement in the performance of the hafnium oxide-based (HfO2) ferroelectric field-effect transistors (FeFET) achieved by a synergistic approach of interfacial layer (IL) engineering and READ-voltage optimization. FeFET devices with silicon dioxide (SiO2) and silicon oxynitride (SiON) as IL were fabricated and characterized. Although the FeFETs with SiO2 interfaces demonstrated better low-frequency characteristics compared to the FeFETs with SiON interfaces, the latter demonstrated better WRITE endurance and retention. Finally, the neuromorphic simulation was conducted to evaluate the performance of FeFETs with SiO2 and SiON IL as synaptic devices. We observed that the WRITE endurance in both types of FeFETs was insufficient to carry out online neural network training. Therefore, we consider an inference-only operation with offline neural network training. The system-level simulation reveals that the impact of systematic degradation via retention degradation is much more significant for inference-only operation than low-frequency noise. The neural network with FeFETs based on SiON IL in the synaptic core shows 96% accuracy for the inference operation on the handwritten digit from the Modified National Institute of Standards and Technology (MNIST) data set in the presence of flicker noise and retention degradation, which is only a 2.5% deviation from the software baseline.

Investigation of time domain characteristics of negative capacitance FinFET by pulse-train approaches

The HfO2-based ferroelectric field effect transistors (FeFET) have been widely studied for their ability in breaking the Boltzmann limit and the potential to be applied to low-power circuits. This article systematically investigates the transient response of negative capacitance (NC) fin field-effect transistors (FinFETs) through two kinds of self-built test schemes. By comparing the results with those of conventional FinFETs, we experimentally demonstrate that the on-current of the NC FinFET is not degraded in the MHz frequency domain. Further test results in the higher frequency domain show that the on-state current of the prepared NC FinFET increases with the decreasing gate pulse width at pulse widths below 100 ns and is consistently greater (about 80% with NC NMOS) than the on-state current of the conventional transistor, indicating the great potential of the NC FET for future high-frequency applications.

Interplay Between Switching and Retention in HfO2-Based Ferroelectric FETs

Long data retention is a critical requirement for many of the potential applications of HfO2-based ferroelectric field-effect transistors (FeFETs). However, methods for its rapid assessment are still missing. In this article, we report a detailed investigation of the retention and switching properties of FeFETs fabricated in the 28-nm high- ${k}$ metal gate technology. We identify a clear correlation between the two properties and propose a method for fast prediction of the device retention behavior, which can be easily adopted to judge different fabrication processes. Finally, we extend the validity of the method to a direct assessment of disturb-free operating conditions, which may be particularly valuable for FeFET array operation.

Impact of Series-Connected Ferroelectric Capacitor in HfO₂-Based Ferroelectric Field-Effect Transistors for Memory Application

In this work, we demonstrated a HfO2-based ferroelectric field-effect transistor (FeFET) in series with a HfAlO ferroelectric capacitor for memory application and further investigated the impact of the ferroelectric capacitor with different thicknesses and areas. It was revealed that the memory window of the FeFET has a significant correlation with the ferroelectric capacitor from the transfer curves of the transistor after the series connection. By decreasing the thickness and area of the ferroelectric capacitor, the memory window of the FeFET was improved, which could be verified through the TCAD simulation tool and capacitance matching model. With the series-connected ferroelectric capacitor, in addition to optimizing the characteristics of ferroelectric memory, we can effectively avoid the interface-caused undesirable effects in conventional ferroelectric memory during film stacking. These results provide a solution for future low-power embedded memory application.

A Study of Endurance Issues in HfO2-Based Ferroelectric Field Effect Transistors: Charge Trapping and Trap Generation

Recent demonstration of aggressively scaled HfO2-based ferroelectric field effect transistors (FE-HfO2-FETs) has illustrated a pathway to fabricate FeFETs that enjoy COMS-compatibility, low power, fast switching speed, scalability, and long retention. One potential issue of this promising technology is its limited endurance, which has been attributed to the degradation of gate stack before the fatigue of polarization in the ferroelectric HfO2 layer. Some associated work has identified charge trapping and trap generation as key villains, but a clear understanding of two aforementioned underlining mechanisms is still missing. In this letter, we initiated this letter to investigate the roles of charge trapping and trap generation in causing endurance failure of FE-HfO2 FETs.

Charge-Trapping Phenomena in HfO2-Based FeFET-Type Nonvolatile Memories

Ferroelectric field effect transistors (FeFETs) based on ferroelectric hafnium oxide (HfO2) thin films show high potential for future embedded nonvolatile memory applications. However, HfO2 films besides their recently discovered ferroelectric behavior are also prone to undesired charge trapping effects. Therefore, the scope of this paper is to verify the possibility of the charge trapping during standard operation of the HfO2-based FeFET memories. The kinetics of the charge trapping and its interplay with the ferroelectric polarization switching are analyzed in detail using the single-pulse $I_{D}$ – $V_{G}$ technique. Furthermore, the impact of the charge trapping on the important memory characteristics such as retention and endurance is investigated.