Heterostructure Transistors Research Articles

ScAlN/GaN High Electron Mobility Transistor Heterostructures Grown by Ammonia Source Molecular Beam Epitaxy on Silicon Substrate

In this work, ammonia source molecular beam epitaxy is explored as an alternative technique to grow ScAlN/GaN high electron mobility transistor heterostructures on a silicon substrate with thin buffer layers. The effect of ScAlN barrier thickness is investigated. A transistor with a maximum drain current superior to 1 A mm−1 has been fabricated on a silicon substrate despite the ohmic contacts having a resistance around 1 ohm.mm, and functional transistors with barriers as thin as 10 nm have been demonstrated.

Wafer-Scale Atomic Layer-Deposited TeOx/Te Heterostructure P-Type Thin-Film Transistors.

There is an increasing demand for p-type semiconductors with scalable growth, excellent device performance, and back-end-of-line (BEOL) compatibility. Recently, tellurium (Te) has emerged as a promising candidate due to its appealing electrical properties and potential low-temperature production. So far, nearly all of the scalable production and integration of Te with complementary metal oxide semiconductor (CMOS) technology have been based on physical vapor deposition. Here we demonstrate wafer-scale atomic layer-deposited (ALD) TeOx/Te heterostructure thin-film transistors with high uniformity and integration compatibility. The wafer-scale uniformity of the film is evidenced by spatial Raman mappings and statistical electrical analysis. Furthermore, surface accumulation-induced good ohmic contact has been observed and explained by the unique band alignment of the charge neutrality level inside the Te valence band. These results demonstrate ALD TeOx/Te as a promising p-type semiconductor for monolithic three-dimensional integration in BEOL CMOS applications incorporated with well-established n-type ALD oxide semiconductors.

Device‐Level in‐Sensor Olfactory Perception System Based on Array of PCBM‐MAPbI3 Heterostructure Transistors

AbstractAlthough there are significant advancements in device‐level artificial tactile and visual perception systems based on in‐sensor computing paradigms, the development of hardware‐implemented neuromorphic olfactory system is still in its early stages. One of the primary challenges in this field is that most of the gas sensors lack the capability to fuse the sensing and computing functions in a single sensor. Through surface passivation and interface engineering, this work introduces a device‐level artificial olfactory system utilizing array of PCBM‐MAPbI3 heterostructure transistors. Noteworthly, the formation of metastable intermediate phase NH3PbI3•MA can occur at room temperature and can be used to store gas sensory information. Both gas pulse and electrical pulse can dynamically modulate the amount of this intermediate phase, and then change the channel conductance (weight), realizing the fusion of the sensing and synaptic functions in single device. Based on these excellent properties, the spatiotemporal information of gas diffusion can be encoded and processed simultaneously. As a result, an in‐sensor olfactory perception system is successfully demonstrated based on 5 × 5 PCBM‐MAPbI3 heterostructure transistor array, which can be used for detecting the distance and direction of the hazardous gas. This work paves the way for future application of real‐time and data‐intensive machine‐olfactory system.

Low contact resistance and high breakdown voltage of AlGaN/GaN HEMT grown on silicon using both AlN/GaN superlattice and Al0.07Ga0.93N back barrier layer

In this study, the growth of a high-quality AlGaN/GaN high electron mobility transistor (HEMT) heterostructure on silicon (Si) by metal–organic chemical vapor deposition was investigated by utilizing both the AlN/GaN superlattice (SL) and Al0.07Ga0.93N back barrier (BB) techniques. An atomic force microscope and high-resolution x-ray diffractometer confirm a low surface roughness of 0.26–0.34 nm and the formation of a high-quality AlN/GaN SL and GaN channel. The AlGaN/GaN heterostructures exhibit a high electron mobility of up to 1700 cm2 V−1∙s and a high carrier concentration density of (1.02–1.06 × 1013 cm−2) for both heterostructures. The AlGaN/GaN HEMT devices demonstrate a low specific contact resistivity (ρ c) of 2.7 × 10−6 Ω·cm2 and a low contact resistance (RC ) of 0.3 Ω·mm for the heterostructure with a BB layer. Furthermore, the DC characteristics demonstrate that incorporating Al0.07Ga0.93N BB in the heterostructure results in a 19.2% increase in lateral breakdown voltage (with a 10 µm spacing) and a 27.5% increase in vertical breakdown voltage (at 1 mA cm−2) compared to heterostructures without Al0.07Ga0.93N BB within the AlN/GaN SL structure. Moreover, an improvement of 10.6% in the maximum saturation current (I DS) and 15.2% in on-resistance (R ON) has been achieved for the device fabricated on an Al0.07Ga0.93N BB structure. The insertion loss of the buffer layer improves to −1.40 dB mm−1 at 40 GHz. Consequently, the proposed heterostructure investigated in this study demonstrates suitability for electronic device applications.

Tunable Band‐to‐Band Tunneling and Conducting Path Transition in Local‐Control‐Gate Heterostructure Transistor

AbstractTransition metal dichalcogenide (TMD) material‐based heterostructures have exhibited great potential for building advanced architectures in novel logic devices. A local‐control‐gate (LCG) transistor based on MoTe2/MoS2 heterostructure is fabricated and analyzed, illustrating its tunable electrical characteristics and achieving band‐to‐band tunneling (BTBT) enhancement with an improved peak‐to‐valley current ratio (PVCR) value of 3.04. Compared to the basic dual‐gate tunnel field‐effect transistor (TFET) structure, adding LCG at the bottom not only isolates defect‐induced doping effects from the deposition of top gate dielectrics, but also paves the way for broader applications in multivalued logic and artificial intelligence. Aiming to further verify the operating mechanism of conducting path transition and electrical characteristic trends, commercial technology computer‐aided design (TCAD) is systematically employed assisted by density functional theory (DFT). So that the transition of conducting paths in the heterostructure channel including interlayer quantum effects can be visibly demonstrated while applying various voltages to the LCG. In summary, this work highlights the feasibility of a new LCG structure with tunable electrical characteristics and presents DFT‐assisted TCAD simulations for effective verifications.

Verifying the physical role of upper-active-layer on charge transport together with bias stability in bilayer-channel oxide thin-film transistors

In this work, we report the fabrication of solution-processed bilayer-structure oxide thin-film transistors (TFTs) exhibiting superior electrical characteristics and enhanced positive/negative bias stabilities. This was achieved by tuning the carrier concentration and bandgap of the top active layer in the bilayer semiconductor. The characteristics of the top layer were modulated through aluminum (Al) doping in indium oxide semiconductors. Bilayer-channel TFTs with an optimized indium-aluminum-oxide top layer (In:Al ratio of 8:2) demonstrated effective electron transport via percolation conduction and exhibited high mobility. Furthermore, the optimized bilayer TFTs displayed small threshold voltage shifts under positive and negative bias stress, attributed to the effective formation of a quasi-two-dimensional electron gas and the suppression of oxygen vacancies. An in-depth study on engineering the carrier concentration and bandgap of the bilayer structure provides insights into material design and fabrication strategies for high-performance and stable heterostructure transistors.

A synapse with low power consumption based on MoTe2/SnS2 heterostructure

The use of two-dimensional materials and van der Waals heterostructures holds great potential for improving the performance of memristors Here, we present SnS2/MoTe2 heterostructure synaptic transistors. Benefiting from the ultra-low dark current of the heterojunction, the power consumption of the synapse is only 19 pJ per switching under 0.1 V bias, comparable to that of biological synapses. The synaptic device based on the SnS2/MoTe2 demonstrates various synaptic functionalities, including short-term plasticity, long-term plasticity, and paired-pulse facilitation. In particular, the synaptic weight of the excitatory postsynaptic current can reach 109.8%. In addition, the controllability of the long-term potentiation and long-term depression are discussed. The dynamic range (G max/G min) and the symmetricity values of the synaptic devices are approximately 16.22 and 6.37, and the non-linearity is 1.79. Our study provides the possibility for the application of 2D material synaptic devices in the field of low-power information storage.

CVD graphene contacts for lateral heterostructure MoS2 field effect transistors

Intensive research has been carried out on two-dimensional materials, in particular molybdenum disulfide, towards high-performance field effect transistors for integrated circuits1. Fabricating transistors with ohmic contacts is a challenging task due to the formation of a high Schottky barrier that severely limits the performance of the transistors for real-world applications. Graphene-based heterostructures can be used in addition to, or as a substitute for unsuitable metals. In this paper, we present lateral heterostructure transistors made of scalable chemical vapor-deposited molybdenum disulfide and chemical vapor-deposited graphene achieving a low contact resistances of about 9 kΩ·µm and high on/off current ratios of 108. Furthermore, we also present a theoretical model calibrated on our experiments showing further potential for scaling transistors and contact areas into the few nanometers range and the possibility of a substantial performance enhancement by means of layer optimizations that would make transistors promising for use in future logic integrated circuits.

Heterostructure transistor for an energy-efficient low-noise radiothermograph amplifier based on monolithic integrated circuits

Currently, there is a growing interest in medical practice in such a method of diagnostic human internal organs as microwave radiothermometry. However, a number of strict requirements are imposed on the parameters of radiometric receivers, which are the main elements of a radiothermograph, including the amplification path. The problem lies in the fact that the amplifying path of the radiothermograph consumes, with transistors available on the market, an unacceptably large amount of energy, which leads to an increase in heat generation and, as a result, to the introduction of additional errors in measurements. Therefore, in order to increase the reliability of the radiothermograph, it is necessary to develop a basic transistor for MIC amplifier with reduced power consumption. Using numerical modeling methods, the parameters of an energy-efficient transistor on the proposed heterostructure were researched. As a result of optimizing the transistor design based on the presented strict requirements for the parameters, a calculated steepness characteristic was obtained, clearly showing the increased amplifying properties of the proposed transistor in the low-current region, which directly leads to the possibility of a significant reduction in current consumption of the entire chip. A significant increase in transconductance of the proposed transistor design indicates the possibility of using this promising element base as part of microwave radiometers, which will allow combining the principles of multi-channel, multi-frequency and miniaturization in one radiometric complex and will lead to an expansion of its functionality and a significant reduction in size. The research was carried out with the financial support of the Russian science Foundation in the framework of agreement No. 19-19-00349-П in the theme: “A method and a multichannel multifrequency microwave radiothermography on the basis of monolithic integrated circuits for finding the 3D distribution and dynamics of brightness temperature in the depths of the human body”.

Source of two-dimensional electron gas in unintentionally doped AlGaN/GaN multichannel high-electron-mobility transistor heterostructures—Experimental evidence of the hole trap state

Multichannel high electron mobility transistor (MC-HEMT) heterostructures are one of the choices for improved power performance of GaN HEMTs. By comparing the experimentally obtained two-dimensional electron gas (2DEG) concentration of unintentionally doped (UID) AlGaN/GaN MC-HEMTs with simulated 2DEG concentration, we hypothesized that hole trap(s) exist at the buried GaN/AlGaN interfaces, which act as sources of 2DEG in UID MC-HEMT heterostructures. Furthermore, these hole traps stop the Fermi level from cutting the valence band at GaN/AlGaN interfaces, which in turn precludes the generation of parallel two-dimensional hole gas (2DHG) in the MC-HEMT. However, no experimental report is present as a proof for the existence of such a hole trap in MC-HEMT heterostructures. In this study, a capacitance–conductance method on single and dual channel HEMTs revealed traps with higher time constant of 19–28.7 μs exclusively for the dual channel HEMT heterostructure. These traps are observed at the buried GaN/AlGaN interface of the dual channel HEMT; hence, they are attributed to possible hole traps at this interface. By conducting systematic deep level transient spectroscopy measurements, the existence of hole traps is confirmed at the buried GaN/AlGaN interface with an activation energy of 717 meV and a capture cross section of 1.3 × 10−14 cm2. This experimental evidence of the existence of hole traps at the GaN channel/AlGaN interface further supports our claim that these hole traps act as the source of 2DEG in UID MC-HEMTs and that buried parallel 2DHG channels do not exist in MC-HEMTs.

Impact of surface preparation on the epitaxial growth of SrTiO3 on ScAlN/GaN heterostructures

Heterogeneous integration of functional oxides with ultra-wide bandgap (UWBG) semiconductors is desired for the realization of novel hybrid systems applicable to a wide array of commercial electronics and defense applications. In this work, we demonstrate the growth of crystalline SrTiO3 (STO) thin films on high-electron-mobility transistor (HEMT) heterostructures based on an emergent UWBG semiconductor ScAlN, used as the barrier layer on a GaN channel, and determine the effects of the pre-growth chemical treatments of the ScAlN surface on resultant heterostructure properties. We investigate wet chemical cleans of ScAlN with solvents, piranha solution, UV ozone and hydrofluoric acid, and a sulfuric-phosphoric acid mix prior to STO growth, and show that the commonly used piranha solution degrades the ScAlN surface, thereby reducing the crystal quality of the deposited STO layers and lowering the channel mobility. We determine that among the treatments studied, the solvent and sulfuric-phosphoric acid cleans were the least disruptive to the electrical properties of the GaN channel as evidenced from Hall effect measurements, but the sulfuric-phosphoric acid clean results in best oxide crystallinity, as determined from structural characterizations. We perform transmission electron microscopy imaging on the piranha-treated and sulfuric-phosphoric-treated samples to compare the microstructure and find that while intermixing occurs at the oxide-nitride interfaces for both samples, the interface roughness is lower and the STO grain size is larger in the sample with sulfuric-phosphoric acid treatment. This work demonstrates the first epitaxial growth of STO on an UWBG semiconductor and motivates STO/ScAlN/GaN as material platforms for high-frequency, high-power-density HEMTs.

Surface morphology evolution of N-polar GaN on SiC for HEMT heterostructures grown by plasma-assisted molecular beam epitaxy

The surface morphology evolution of N-polar GaN with growth time was investigated and compared with Ga-polar GaN. N-polar GaN directly grown on SiC substrates was found to have slower 3D-to-2D growth transformation and less coalescence than the Ga-polar counterpart, resulting in rougher surface morphology, whereas the AlN nucleation layer accelerated 3D-to-2D transformation, resulting in smoother surface morphology. N-polar GaN was found to have mound-type surface morphology with clustered atomic steps, unlike the regular screw-type dislocation-mediated step-flow growth observed for Ga-polar GaN. This was explained by the lower diffusion of adatoms on the N-polar surface due to its higher surface energy and higher Ehrlich–Schwoebel barrier. In addition, the increased III/V ratio in N-polar GaN growth was found to reduce the surface roughness from 2.4 nm to 1 nm. Without Si doping, the N-polar GaN high electron mobility transistor (HEMT) heterostructures grown under optimized conditions with smoother surface morphologies exhibited a sheet carrier density of 0.91 × 1013 cm−2 and a mobility of 1220 cm2 (V s)−1. With Si δ-doping, the sheet carrier density was increased to 1.28 × 1013 cm−2 while the mobility was reduced to 1030 cm2 (V s)−1. These results are comparable to the state-of-the-art data of plasma-assisted molecular beam epitaxy-grown N-polar GaN HEMT heterostructures on SiC substrates.

Enhanced quantum oscillations and scattering effect in quaternary InAlGaN/GaN two-dimensional electron gas

Quantum transport properties of a large bandgap In0.15Al0.79Ga0.06N/GaN quaternary GaN high electron mobility transistor (HEMT) heterostructure are studied at low temperatures up to 2 K. Herein, we report the first evidence of weak localization in a quaternary GaN two-dimensional electron gas (2DEG) system. We observe negative magnetoresistance behavior and extracted dephasing time (τΦ) using a Hikami–Larkin–Nagaoka model at 2.2 K. Linear dependency of dephasing rate with temperature (τΦ−1∝T) is established below 20 K. Furthermore, Shubnikov–de Haas quantum oscillation induced by 2DEG is observed using perpendicular magnetic (B⊥) field strengths up to 14 T. From the temperature-dependent oscillation amplitude, we extracted an effective mass m*≈0.237me. The dominance of small-angle scattering in the 2DEG channel is identified from less than unit ratio (τq/τt≪1) of quantum lifetime (τq) to the Hall transport lifetime (τt). In our study, we have demonstrated that the In0.15Al0.79Ga0.06N/GaN quaternary heterostructure possesses high dephasing time (τΦ=5.4 ps) and larger quantum lifetime (τq=0.102 ps) indicating better suitability and a way forward to high-power–high-frequency GaN HEMT development.

Effects of GaN channel downscaling in AlGaN–GaN high electron mobility transistor structures grown on AlN bulk substrate

In this work, two series of AlGaN/GaN/AlN high electron mobility transistor (HEMT) heterostructures have been grown by molecular beam epitaxy on AlN bulk substrates. The effects of reduction in the GaN channel thickness as well as the AlGaN barrier thickness and composition on structural and electrical properties of the heterostructures have been studied. The material analysis involved high-resolution x-ray diffraction, atomic force microscopy, and cross-sectional transmission electron microscopy. In a first series of HEMT structures grown with an aluminum content of 30% in the AlGaN barrier, the channel downscaling results in a reduction in the GaN strain relaxation rate but at the expense of degradation in the mean crystal quality and in the electron mobility with a noticeable increase in the sheet resistance. An opposite trend is noticed for the three-terminal breakdown voltage of transistors, so that a trade-off is obtained for a 50 nm width GaN channel HEMT, which exhibits a sheet resistance of 1700 Ω/sq. with transistors demonstrating three-terminal breakdown voltage up to 1400 V for 40 μm gate to drain spacing with static on resistance Ron = 32 mΩ cm2. On the other hand, a second series of HEMT structures with high aluminum content AlGaN barriers and sub-10 nm GaN channels have been grown perfectly strained with high sheet carrier densities allowing to preserve sheet resistances in the range of 880–1050 Ω/sq.

Influence of the temperature on growth by ammonia source molecular beam epitaxy of wurtzite phase ScAlN alloy on GaN

Due to its large piezoelectric and spontaneous polarization coefficients combined with the possibility of being grown lattice-matched with GaN, wide bandgap ScAlN is becoming a promising material in III-nitride semiconductor technology. In this work, and for the first time, ScAlN growth has been performed by molecular beam epitaxy with ammonia source as nitrogen precursor. High electron mobility transistor heterostructures with a 26 nm thick Sc0.15Al0.85N barrier have been grown on GaN-on-sapphire substrates. The effect of growth temperature, ranging between 620 and 800 °C, was carefully investigated. A smooth surface morphology with a mean roughness below 0.5 nm is obtained whatever the temperature while for 670 °C the (0002) and (101̄3) x-ray diffraction rocking curves show minimum full-width at half-maximum of 620 and 720 arc sec, respectively. Furthermore, two-dimensional electron gases with a high density of 3-3.5 × 1013/cm2 were evidenced in the heterostructures grown below 720 °C.

Quantum transport of sub-5 nm InSe and In2SSe monolayers and their heterostructure transistors.

The emerging two-dimensional (2D) semiconductors hold a promising prospect for sustaining Moore's law benefitting from the excellent device electrostatics with narrowed channel length. Here, the performance limits of sub-5 nm InSe and In2SSe metal-oxide-semiconductor field-effect transistors (MOSFETs) are explored by ab initio quantum transport simulations. The van der Waals heterostructures prepared by assembling different two-dimensional materials have emerged as a new design of artificial materials with promising physical properties. In this study, device performance was investigated utilizing InSe/In2SSe van der Waals heterostructure as the channel material. Both the monolayer and heterostructure devices can scale Moore's law down to 5 nm. A heterostructure transistor exhibits a higher on-state current and faster switching speed compared with isolated monolayer transistors. This work proves that the sub-5 nm InSe/In2SSe MOSFET can satisfy both the low power and high-performance requirements for the international technology roadmap for semiconductors in the next decade and can provide a feasible approach for enhancing device performance.

Effects of AlN/GaN superlattice buffer layer on performances of AlGaN/GaN HEMT grown on silicon for sub-6 GHz applications

In this study, the effects of AlN/GaN superlattice (SL) thickness on performances of AlGaN/GaN high electron mobility transistor (HEMT) heterostructure grown by metal-organic chemical vapor deposition on silicon is investigated. Stress in GaN is controlled by varying the total thickness of the AlN/GaN SL. Improved crystal quality and surface roughness accomplished with 2200 nm-thick AlN/GaN SL, leads to an increase in high electron mobility (1760 cm2 (V s)−1) as well as two-dimensional electron gas concentration (1.04 × 1013 cm−2). AlGaN/GaN metal–insulator-semiconductor HEMT (MIS-HEMT) fabricated on the heterostructure with SL buffer layer exhibits a significant improvement in maximum saturation current of 1100 ± 29 mA mm−1 at V GS = 0 V and a low on-resistance of 4.3 ± 0.15 Ω mm for the optimized AlN/GaN SL. The 2200 nm-thick AlN/GaN SL supports the growth of stress-free GaN heterostructure, which can reduce the insertion loss for sub-6 GHz radio frequency (RF) applications. This GaN HEMT structure based on SL buffer layer is suitable for low-frequency RF power applications.

Study of electrical transport properties of GaN-based side-gate heterostructure transistors

In this study, GaN-based side-gate heterostructure transistors (SGHTs) with two electrical operating modes were fabricated. In the first operating mode, the SGHT was utilized as a common-source voltage amplifier with low power consumption and a broad input signal range. Analysis of the main scattering mechanisms affecting the electrical transport of two-dimensional electron gas (2DEG) in the channel revealed that polar optical phonon scattering and polarization Coulomb field (PCF) scattering play dominant roles under different side-gate voltages. In addition, channel current modulation of 2DEG electron mobility is primarily attributed to PCF scattering. Due to PCF scattering, the channel width also modulates the threshold voltage in this mode of operation. Moreover, in the second operating mode, the SGHT functioned as a traditional GaN high electron mobility transistor, allowing for electrically modulated threshold voltage and transconductance.

Overcoming metal-rich surface chemistry limitations of ScAlN for high electrical performance heterostructures

While metal-rich ScAlN epitaxy has traditionally led to mixed phase films by controlling the surface chemistry with transient metal doses utilizing a pulsed method of molecular beam epitaxy, phase-pure, metal-rich epitaxy of ScAlN was demonstrated, showing improved structural and electrical characteristics. The effects of substrate temperature and III/V ratio were studied, and an x-ray diffraction figure of merit and surface roughness as low as 225 arcsec and 0.68 nm, respectively, were demonstrated. A significant catalytic effect is observed with the use of Sc in metal-rich conditions, resulting in varied growth rates with substrate temperature and Sc surface coverage. This catalytic effect results in complications when selecting synthesis conditions and for in situ monitoring and can be accounted for improved phase purity. The variation of growth rates with Sc surface coverage introduces non-linearities to the transient initiation stage of growth but also introduces a feedback stabilization of the surface chemistry. Accounting for these complexities, a Sc0.2Al0.8N high electron mobility transistor (HEMT) heterostructure is demonstrated with a sheet resistance of 152 Ω/□, a mobility of 700 cm2/Vs, and a sheet charge of 5.9 × 1013 cm−2.

Impact of the Channel Thickness on Electron Confinement in MOCVD‐Grown High Breakdown Buffer‐Free AlGaN/GaN Heterostructures

The 2D electron gas (2DEG) confinement on high electron mobility transistor (HEMT) heterostructures with a thin undoped GaN channel layer on the top of a grain‐boundary‐free AlN nucleation layer is studied. This is the first time demonstration of a buffer‐free epi‐structure grown with metal–organic chemical vapor deposition with thin GaN channel thicknesses, ranging from 250 to 150 nm, without any degradation of the structural quality and 2DEG properties. The HEMTs with a gate length of 70 nm exhibit good DC characteristics with peak transconductances of 500 mS mm−1and maximum saturated drain currents above 1 A mm−1. A thinner GaN channel layer improves 2DEG confinement because of the enhanced effectiveness of the AlN nucleation layer acting as a back‐barrier. An excellent drain‐induced barrier lowering of only 20 mV V−1at aVDSof 25 V and an outstanding critical electric field of 0.95 MV cm−1are demonstrated. Good large‐signal performance at 28 GHz with output power levels of 2.0 and 3.2 W mm−1and associated power‐added efficiencies of 56% and 40% are obtained at aVDSof 15 and 25 V, respectively. These results demonstrate the potential of sub‐100 nm gate length HEMTs on a buffer‐free GaN‐on‐SiC heterostructure.