Heterojunction Tunnel FET Research Articles

Dielectric Modulated TFET on SELBOX Substrate as a Label-Free Biosensor Applications: Analytical Modeling Study and Sensitivity Analysis

Abstract The manuscript proposes a ferroelectric heterojunction TFET (BG-FE-HJ-STFET) on SELBOX substrates with a back gate to create an ultra-sensitive label-free biosensor with dielectric modulation for the detection of neutral and charged biomolecules. Within the proposed device, four cavities have been carved out for the biomolecules' immobilization under the front and rear gate dielectrics. By using a ferroelectric (FE) material as a gate stack, the low gate voltage is increased to be more effective by causing a negative capacitance phenomenon. The response of the proposed biosensor to four impartial biomolecules with different dielectric constants Protein (k=8), Biotin (k=2.63), 3-Aminopropyl-triethoxysilane (APTES) (k=3.57), and Streptavidin (k=0.1) has been investigated. Deoxyribonucleic acid (DNA), a charged biomolecule, is also examined for dielectric constant of k=6 with respect to both charges (Negative and Positive)) densities. The device is simulated with the commercially available SILVACO ATLASTM TCAD tool. The performance analysis relies on several figures of merit (FOMs) such as DC/RF and sensitivity (including drain current, ION/IOFF ratio, and subthreshold swing) for both neutral and charged biomolecules. The optimized cavity structure demonstrates a notable sensitivity in drain current (2.7x108) and a significant ION/IOFF sensitivity (1.42x1011). One of the main problems with current biosensors is the difficulty and expense of production in the nanoscale realm.

GaAs-on-insulator based vertical heterojunction tunnel FET: proposal and analysis for VLSI circuit applications

This work analyses the Gallium Arsenide (GaAs)-on-insulator based vertical heterojunction tunnel FET with Gallium Antimonide (GaSb) as source material and GaAs as channel/drain material (GaSb/GaAs VTFET) to enhance the performance of the device and is compared with the Silicon-based VTFET. Silvaco Atlas TCAD tool is employed to perform numerical calculations. Tentative fabrication process flow of GaSb/GaAs VTFET is presented. GaSb is a low bandgap material that enhances the tunneling of charge carriers at source-channel heterojunction. GaSb/GaAs VTFET device outperforms Si-based VTFET in terms of electrical performance metrics such as ON-state current (ION), and ION/IOFF increases by a factor of 11 and 270 respectively; whereas OFF-state current (IOFF), subthreshold swing (SS), threshold voltage (VT) and drain-induced barrier lowering (DIBL) reduce by 95.98%, 39.36%, 17.14% and 29.17% respectively. Further, analog/RF and linearity/distortion performance analysis is carried out. GaSb/GaAs VTFET has improved analog/RF performances in terms of cut-off frequency (fT), gain-bandwidth product (GBP), transit time (τ), device efficiency (DE), transconductance frequency product (TFP) and suppressed distortions in compare to Si-based VTFET. Finally, GaSb/GaAs VTFET is evaluated for process variations and designing digital inverter and common source amplifier circuits. The Look-up-table (LUT) based Verilog-A model within the CADENCE tool has been employed to scrutinize the transient responses of inverter and common source amplifier circuits. Unity gain frequency and 3-dB bandwidth obtained for GaSb/GaAs VTFET amplifier are 15 GHz and 5.97 GHz. Therefore, this work presents GaSb/GaAs VTFET’s strong candidature for analog and digital VLSI circuit designing.

Proposal and evaluation of Mg2Si-based vertical tunnel field effect transistor for enhanced performance

This work investigates the performance of silicon-on-insulator (SOI) based vertical heterojunction tunnel FET with magnesium silicide (Mg2Si) as source material (Mg2Si-VTFET) with silicon-based counterpart (Si-VTFET). The investigation utilizes SILVACO TCAD tool to analyse various metrics including electrical characteristics, radio-frequency performance, linearity, and distortion. Incorporation of low bandgap material at source forms hetero-junction at source-channel interface, thereby reducing the tunneling path and enhancing the tunneling rate of charge carriers. ON-state current (ION) and current switching ratio (ION/IOFF) for Mg2Si-VTFET improves by factor of approximately ∼ 105 and 102 times. Mg2Si-VTFET outperforms Si-VTFET in terms of ION current for low biasing voltages, transconductance (gm), gain-bandwidth-product (GBP), cut-off frequency (fT) and transit-time. However, Mg2Si-VTFET has better linearity and reduced distortions in terms of VIP2 and HD2 metrics. HD2 suppresses by 53.8 % for Mg2Si-VTFET over Si-VTFET. This suggests that Mg2Si-VTFET is better suited for applications requiring low distortion, such as in audio amplifiers or communication systems. Therefore, Mg2Si-VTFET shows strong candidacy over Si based counterpart for low power circuits.

Analysis of III–V Heterojunction TFET for High-Frequency Analog Applications

Analysis of III–V Heterojunction TFET for High-Frequency Analog Applications

Inner Doping of Carbon Nanotubes with Perovskites for Ultralow Power Transistors.

Semiconducting carbon nanotubes (CNTs) are considered as the most promising channel material to construct ultrascaled field-effect transistors, but the perfect sp2 C─C structure makes stable doping difficult, which limits the electrical designability of CNT devices. Here, an inner doping method is developed by filling CNTs with 1D halide perovskites to form a coaxial heterojunction, which enables a stable n-type field-effect transistor for constructing complementary metal-oxide-semiconductor electronics. Most importantly, a quasi-broken-gap (BG) heterojunction tunnel field-effect transistor (TFET) is first demonstrated based on an individual partial-filling CsPbBr3/CNT and exhibits a subthreshold swing of 35mV dec-1 with a high on-state current of up to 4.9µA per tube and an on/off current ratio of up to 105 at room temperature. The quasi-BG TFET based on the CsPbBr3/CNT coaxial heterojunction paves the way for constructing high-performance and ultralow power consumption integrated circuits.

A Study on the Performance of Gate-All-Around Heterojunction Tunnel Field-Effect Transistors Based on Polarization Effect

A Study on the Performance of Gate-All-Around Heterojunction Tunnel Field-Effect Transistors Based on Polarization Effect

GaSb/Si Heterojunction Based Pocket Engineered Vertical Non-Uniform Channel Double Gate TFETs for Low Power Applications

This article compares the performance of two Vertical Non-Uniform Channel Double Gate Tunnel Field Effect Transistors (VNUCDGTFETs), a normal all-Silicon Tunnel Field-Effect Transistor (TFET) having a pocket and another one a Gallium Antimonide/Silicon heterojunction TFET with pocket. GaSb is a III-V narrow energy band gap material, employed in the source area of the TFET structure to decrease the tunneling width and thus to make more number of carriers capable enough to tunnel through the heterojunction. The proposed source pocket heterojunction non uniform channel TFET presents superior performance as compared to the conventional non uniform channel vertical TFET with a pocket, regarding a larger ION/IOFF ratio, a reduced sub-threshold swing, and a smaller threshold voltage at VDS = 0.5 V. Furthermore, the proposed TFET device undergoes a comprehensive analysis of both DC parameters and various analog/RF parameters.

Dielectric Modulated Negative Capacitance Heterojunction TFET as Biosensor: Proposal and Analysis

Dielectric Modulated Negative Capacitance Heterojunction TFET as Biosensor: Proposal and Analysis

A comparative study of work function variations in III-V heterojunction and homojunction tunnel field-effect transistors

In this paper, we present a comparative study on the impact of work function variations (WFV) between the III-V heterojunction and homojunction tunnel field-effect transistors (TFETs) vis TCAD simulation. It reveals that, in general, the current variation of both devices decrease as the gate voltage increases, and the threshold voltage variations generally increase with the increase of threshold current. However, in comparison to homojunction TFET, heterojunction TFET exhibits the following two differences. 1) The current fluctuation is stronger near the device's OFF-state and weaker near the ON-state, and thus it has a stronger dependence on bias. 2) Both the threshold voltage fluctuations and its dependence on the threshold current are weaker. On the other hand, with an increase in grain size, both homojunction and heterojunction devices manifest more prominent performance fluctuations. Moreover, the dependence of these fluctuations on grain size is roughly comparable for these two device types. Finally, it is observed that 1) the significant current fluctuation at the OFF-state can be mitigated when the device's OFF-state is designed within a region with weaker gate control, and 2) the current normalized coefficient of variation parameter may be unreliable to assess the fluctuation for the case with a few “abnormal” high current values.

An inverted T-shaped vertical tunneling InN/InxGa1-xN heterojunction TFET with high current ratio

An inverted T-shaped vertical InN/InGaN tunneling field effect transistor (TFET) with polarization-induced doping and high current ratio is proposed and investigated. An optimal structure of the proposed device is given by comparing on-state current, subthreshold voltage, and on-state/off-state current ratio. The polarization effect in III-N material induces electrons and holes in the source and drain regions, and non-physical doping can avoid random dopant fluctuations (RDFs) and high thermal budget. The InN/InGaN heterojunction TFET shows significant improvement over the homojunction TFET. The inverted T-shaped structure involves line and point tunneling simultaneously, so the proposed device can achieve higher on-state current than the conventional device. In addition, the proposed device shows the suppression of ambipolar current. The simulations reveal that the ION/IOFF of the proposed structure is about 6.91 × 1012. These results indicate that the line tunneling structure is still available in the polarization-induced InN/InGaN TFET.

Accurate Analytical Modeling of Drain Current of Heterojunction Tunneling Field Effect Transistor

Accurate Analytical Modeling of Drain Current of Heterojunction Tunneling Field Effect Transistor

Investigation of In0.7Ga0.3As/Ga0.5As0.5Sb-Based Heterojunction TFET with Ferroelectric Gate Dielectric for Performance and Reliability

This paper investigates In[Formula: see text]Ga[Formula: see text]As/Ga[Formula: see text]As[Formula: see text]Sb-based Heterojunction Tunnel Field Effect Transistor with ferroelectric dielectric as stack layer, namely Ferroelectric Dual Material Stacked Double Gate Heterojunction TFET (FDMSDG-HJTFET) for the first time for performance and reliability. Ferroelectric gate dielectric has been inculcated in the device design in addition to the doping of Ga[Formula: see text]As[Formula: see text]Sb in the source region and In[Formula: see text]Ga[Formula: see text]As in the drain region, respectively. The performance of the proposed device is quantified in terms of DC electrical parameters and short channel parameters. The reliability analysis of the proposed device has been carried out in terms of influence of variations of interface trap charges, gate-source overlap length and temperature on the device transfer characteristics. From the simulation results, it can be manifested that the proposed device presents superior DC electrical characteristic and reduced short channel effects as compared to the GaSb/Si Dual Material Stacked Double Gate Heterojunction TFET (GaSb/Si DMSDG-HJTFET), under the influence of group III–V materials and ferroelectric gate dielectric. In addition to this, the proposed device depicts elevated immunity to presence of interface trap charges at the interface, variations in gate-source overlap length and temperature variations as well. The implication of TiO2 as dielectric stack over SiO2 provides exceptional capacitive coupling at the interface and thus assists in the improvement of electrical characteristics of the device by enhancing the electric field. The outcome of the simulation results presents that Ga[Formula: see text]As[Formula: see text]Sb/In[Formula: see text]Ga[Formula: see text]As-based Ferroelectric Dual Material Stacked Double Gate Heterojunction TFET (FDMSDG-HJTFET) can prove to be a competitive alternative for high performance applications with improved reliability. The design and simulation of the proposed device structure has been executed using technology computer-aided design (TCAD) tool.

Simulation study of multi-source hetero-junction TFET-based capacitor less 1T DRAM for low power applications

A capacitorless one-transistor dynamic random access memory (1T DRAM) based on multi-source hetero-junction tunnel field-effect transistor (TFET) is presented in this work. The analysis of the three memory functions: Write, Hold and Read of 1T DRAM has been carried out using Synopsys TCAD simulations. A storage region of Ge material is used for the accumulation of holes/to store the charge carriers. The variation in length of Ge-storage region, under lap length (Lunder), and temperature is performed to analyse the DRAM performance. In the Write operation, the tunneling window reduces to 15 nm and holes can be easily stored in the Ge-storage region. In case of Hold1 and Read1 operations, the potential barriers are reduced by 0.24 eV, and 0.1 eV respectively. In the proposed multi-source TFET with 14 nm gate length, read current ratio i.e. IR1/IR0 of 4.4, retention time (RT) greater than 10 sec, and sense margin (SM) of 1.27 × 10−6 A/µm is achieved at room temperature. The proposed multi-source TFET based 1T DRAM is operating at very low gate voltages. Therefore, this device is well suited for low power applications.

An Accurate and Full-Range Analytical Current Model for Nanowire Heterojunction TFET

An Accurate and Full-Range Analytical Current Model for Nanowire Heterojunction TFET

Investigation of temperature for the stacked Ferroelectric Heterojunction TFET(Fe-HTFET) on box substrate

Investigation of temperature for the stacked Ferroelectric Heterojunction TFET(Fe-HTFET) on box substrate

Performance investigation of an InAs-based dielectric-modulated heterojunction TFET as a label-free biosensor

Performance investigation of an InAs-based dielectric-modulated heterojunction TFET as a label-free biosensor

An accurate analytical surface potential model of heterojunction tunnel FET

Based on the accurate and efficient thermal injection method, we develop a fully analytical surface potential model for the heterojunction tunnel field-effect transistor (H-TFET). This model accounts for both the effects of source depletion and inversion charge, which are the key factors influencing the charge, capacitance and current in H-TFET. The accuracy of the model is validated against TCAD simulation and is greatly improved in comparison with the conventional model based on Maxwell–Boltzmann approximation. Furthermore, the dependences of the surface potential and electric field on biases are well predicted and thoroughly analyzed.

Investigation of Si 1−X GeX source dual material stacked gate oxide pocket doped hetero-junction TFET for low power and RF applications

ABSTRACT In this paper, the applicability of dual material stacked gate-oxide-Pocket doped-hetero-junction tunnel field effect transistor (DMSGO-PD-HTFET) for low power switching and radio frequency (RF) applications is investigated. In this context, gate workfunction engineering, the stacked-gate-oxide (+) approach, and asymmetrical doping at the P+ source () and N+ drain regions are considered. N+ pocket at source-channel interface implements DMSGO-PD-HTFET and improves interband tunnelling rate. This research aims to improve the device’s switching ratio (/), average subthreshold swing (), and radio frequency (RF) performance. For this, the control gate work function, mole fraction (X), pocket thickness, and doping concentration are optimised. Next, the DC, analog/RF and linearity figure of merits of the proposed device is analysed and the performance is compared with conventional all-silicon dual-material stack gate oxide tunnel field effect transistor (DMSGO-TFET) and dual-material stacked gate oxide-hetero-junction tunnel field effect transistor (DMSGO-HTFET) with source using technology computer-aided design (TCAD) device simulator. Based on the comparative analysis, the optimised design with exhibits an average subthreshold swing () of 28.8 mV/decade, switching ratio (/) of 2 × 1012, cut-off frequency () of 216 (GHz), and other significant improvements in analog/RF and linearity performance parameters. The proposed device is therefore suitable for switching and RF applications.

OFF Current Reduction in Negative Capacitance Heterojunction TFET

OFF Current Reduction in Negative Capacitance Heterojunction TFET

A Study of Stepped Hetero Channel MOSFET and Hetero Junction Tunnel Fets

A Study of Stepped Hetero Channel MOSFET and Hetero Junction Tunnel Fets