Heterogeneous Multicore Systems Research Articles

Thermal Safe Power Constrained Dynamic Mapping for Heterogeneous Multicore System

Heterogeneous multicore system could provide high flexibility for applications through integrating different types of cores. As the number of cores increases, more and more transistors are integrated which could lead to the rise of chip temperature, thus have a negative impact on the system performance. At present, the typical method to tackle this problem is dynamic voltage and frequency scaling (DVFS) which reduces the voltage and frequency to achieve cooling. However, DVFS will make the heterogeneous multicore system unable to take full advantage of its performance. This paper proposes a dynamic mapping method called TspDM which maximizes the system performance target under the premise of satisfying the temperature safety power. TspDM exploits the runtime performance counters of running threads to dynamically adjust thread mapping. Specifically, a lightweight Artificial Neural Network (ANN) model is proposed to obtain the thread-to-core type mapping when a remapping process is activated. Subsequently, TspDM determines the specific core locations of threads according to the number of threads mapped to a certain core type and the thermal safety power computation. The experimental results show that the proposed method is 21% better than that of PCMig while ensuring the thermal safety of heterogeneous platform. In addition, TspDM outperforms recent performance constrained and power constrained literature in terms of system throughput.

Homogeneous and Heterogeneous Multicore Systems

Multicore systems have gained significant importance in the Automotive industry due to data- intensive applications, such as image processing, high- speed process, and GPS application. It enables manufacturers to build smaller chips, simplifying board architecture and routing, reducing power consumption and cost and increasing programmability. Multicore platforms are segregated into two categories namely Homogeneous (symmetric) and Heterogeneous (asymmetric) multicore systems. In Homogeneous systems, all cores are the same, including frequencies, cache sizes and functions. In Heterogeneous systems, different cores operate with different frequencies, cache sizes and functions. In this paper, we are going to discuss various aspects of homogeneous and heterogeneous multicore architectures like number and level of caches, interconnection of the cores, Physical and Temporal isolation, Energy Efficiency, Concurrency, Performance, Reliability and Robustness along with the evaluation of these two architectures for applications based on the above-mentioned aspects.

Power-Efficient and Aging-Aware Primary/Backup Technique for Heterogeneous Embedded Systems

One of the essential requirements of embedded systems is a guaranteed level of reliability. In this regard, fault-tolerance techniques are broadly applied to these systems to enhance reliability. However, fault-tolerance techniques may increase power consumption due to their inherent redundancy. For this purpose, power management techniques are applied, along with fault-tolerance techniques, which generally prolong the system lifespan by decreasing the temperature and leading to an aging rate reduction. Yet, some power management techniques, such as Dynamic Voltage and Frequency Scaling (DVFS), increase the transient fault rate and timing error. For this reason, heterogeneous multicore platforms have received much attention due to their ability to make a trade-off between power consumption and performance. Still, it is more complicated to map and schedule tasks in a heterogeneous multicore system. In this paper, for the first time, we propose a power management method for a heterogeneous multicore system that reduces power consumption and tolerates both transient and permanent faults through primary/backup technique while considering core-level power constraint, real-time constraint, and aging effect. Experimental evaluations demonstrate the efficiency of our proposed method in terms of reducing power consumption compared to the state-of-the-art schemes, together with guaranteeing reliability and considering the aging effect.

ENF-S: An Evolutionary-Neuro-Fuzzy Multi-Objective Task Scheduler for Heterogeneous Multi-Core Processors

In this paper, an evolutionary-neuro-fuzzy-based task scheduling approach (ENF-S) to jointly optimize the main critical parameters of heterogeneous multi-core systems is proposed. This approach has two phases: first, the fuzzy neural network (FNN) is trained using a non-dominated sorting genetic algorithm (NSGA-II), considering the critical parameters of heterogeneous multi-core systems on a training data set consisting of different application graphs. These critical parameters are execution time, temperature, failure rate, and power consumption. The output of the trained FNN determines the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">criticality degree</i> for various processing cores based on the system's current state. Next, the trained FNN is employed as an online scheduler to jointly optimize the critical objectives of multi-core systems at runtime. Due to the uncertainty in sensor measurements and the difference between computational models and reality, applying the fuzzy neural network is advantageous. The efficiency of ENF-S is investigated in various aspects including its joint optimization capability, appropriateness of generated fuzzy rules, comparison with related research, and its overhead analysis through several experiments on real-world and synthetic application graphs. Based on these experiments, our ENF-S outperforms the related studies in optimizing all design criteria. Its improvements over related methods are estimated <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$19.21\%$</tex-math></inline-formula> in execution time, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$13.07\%$</tex-math></inline-formula> in temperature, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$25.09\%$</tex-math></inline-formula> in failure rate, and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$13.16\%$</tex-math></inline-formula> in power consumption, averagely.

A prefetch control strategy based on improved hill-climbing method in asymmetric multi-core architecture

Cache prefetching is a traditional way to reduce memory access latency. In multi-core systems, aggressive prefetching may harm the system. In the past, prefetching throttling strategies usually set thresholds through certain factors. When the threshold is exceeded, prefetch throttling strategies will control the aggressive prefetcher. However, these strategies usually work well in homogeneous multi-core systems and do not work well in heterogeneous multi-core systems. This paper considers the performance difference between cores under the asymmetric multi-core architecture. Through the improved hill-climbing method, the aggressiveness of prefetching for different cores is controlled, and the IPC of the core is improved. Through experiments, it is found that compared with the previous strategy, the average performance of big core is improved by more than 3%, and the average performance of little cores is improved by more than 24%.

Passive Primary/Backup-Based Scheduling for Simultaneous Power and Reliability Management on Heterogeneous Embedded Systems

In addition to meeting the real-time constraint, power&#x002F;energy efficiency and high reliability are two vital objectives for real-time embedded systems. Recently, heterogeneous multicore systems have been considered an appropriate solution for achieving joint power&#x002F;energy efficiency and high reliability. However, power&#x002F;energy and reliability are two conflict requirements due to the inherent redundancy of fault-tolerance techniques. Also, because of the heterogeneity of the system, the execution of the tasks, especially real-time tasks, in the heterogeneous system is more complicated than the homogeneous system. The proposed method in this paper employs a passive primary&#x002F;backup technique to preserve the reliability requirement of the system at a satisfactory level and reduces power&#x002F;energy consumption in heterogeneous multicore systems by considering real-time and peak power constraints. The proposed method attempts to map the primary and backup tasks in a mixed manner to benefit from the execution of the tasks in different core types and schedules the backup tasks after finishing the primary tasks to remove the overlap between the execution of the primary and backup tasks. Compared to the existing state-of-the-art methods, experimental results demonstrate our proposed method&#x0027;s power efficiency and effectiveness in terms of schedulability.

RT-SEAT: A hybrid approach based real-time scheduler for energy and temperature efficient heterogeneous multicore platforms

The demand for heterogeneous multicore platforms is growing at a rapid pace in modern gadgets. Such platforms help cater to various types of applications and thus provide high resource utilization. As each task has a different execution time on different types of cores, it is very challenging to schedule tasks on such platforms. With the advancement in technology, it has become imperative to manage energy consumption and temperatures of cores in multicore platforms. Hence, in this work, we propose RT-SEAT, a hybrid real-time scheduler for energy and temperature-efficient heterogeneous multicore systems. Through extensive experimental analysis, we have found that RT-SEAT is able to schedule more tasks (up to 46.75%), save more energy (up to 6.89%), and reduce the average temperature of the cores by 20.45%, when the system workload varies from 50% to 100%, with respect to the state-of-the-art.

Energy-Saving Task Scheduling Based on Hard Reliability Requirements: A Novel Approach with Low Energy Consumption and High Reliability

With the increasing complexity of application situations in multi-core processing systems, how to assure task execution reliability has become a focus of scheduling algorithm research in recent years. Most fault-tolerant algorithms achieve hard reliability requirements through task redundancy, which increases energy consumption and contradicts the concept of sustainable development. In this paper, we propose a new algorithm called HDFE (Heterogeneous-Dag-task-fault-tolerance-energy-efficiency algorithm) that combines DVFS technology and task replication technology to solve the scheduling problem of DAG applications concerning energy-saving and hard reliability requirements in heterogeneous multi-core processor systems. Our algorithm is divided into three phases: the priority calculation phase, the task replication phase, and the task assignment phase. The HDFE algorithm achieved energy savings while meeting hard reliability requirements for applications, which was based on the interrelationship between reliability and energy consumption in filtering task replicas. In the experimental part of this paper, we designed four comparison experiments between the EFSRG algorithm, the HRRM algorithm, and the HDFE algorithm. The experimental results showed that the energy consumption of task scheduling using the HDFE algorithm is lower than other algorithms under different scales, thus achieving energy savings and complying with the concept of sustainable development.

Design and Implementation of a Dynamic Task Mapping Algorithm Based on Hotspot Statistics

In a coarse-grained heterogeneous multi-core system, the task map is responsible for allocating the cores for task execution. The existing user static mapping method has low programming friendliness. As the scale and density of system tasks increase, so does the complexity of manual programming by users, resulting in programming inefficiencies. Aiming at this problem, based on the existing heterogeneous multi-core platform, this paper studies a dynamic task mapping method with hotspot statistics, and uses the preprocessing of the mapping to reduce the time spent on the actual mapping. The hardware mapper is designed and implemented in Verilog, and the verification platform is built in the HDL environment. The experimental results show that the new mapping algorithm significantly improves the performance of the system, with an average of 32.50% and a maximum of 47.16%.

PCJ - a Java Library for Heterogenous Parallel Computing

Marek Nowicki, MagdaWith the wide adoption of the multicore and multiprocessor systems the parallel programming became a very important element of the computer science. The programming of the multicore systems is still complicated and far to be easy. The difficulties are caused, amongst others, by the parallel tools, libraries and programming models which are not easy especially for a nonexperienced programmer. In this paper, we present PCJ - a Java library for parallel programming of heterogeneous multicore systems. The PCJ is adopting Partitioned Global Address Space paradigm which makes programming easy. We present basic functionality pf the PCJ library and its usage for parallelization of selected applications. The scalability of the genetic algorithm implementation is presented. The parallelization of the N-body algorithm implementation with PCJ is also described.

Core-aware combining: Accelerating critical section execution on heterogeneous multi-core systems via combining synchronization

In heterogeneous multi-core systems, performance differences of the cores can affect lock synchronization, where the high-performance cores have to wait for slower cores to complete critical section execution. To better utilize the high-performance cores, we can offload critical section execution to high-performance cores. Since combining synchronization has the potential to transfer critical section execution to the combiner, this paper presents a core-aware combining approach for heterogeneous multi-core processors to accelerate critical section execution. In combining synchronization, one competing thread will become the combiner to help complete pending requests. It typically provides better performance than conventional locks on multi-core systems. To enable transferring critical section executions to a more efficient core, we implement the ideas of core efficiency-based selective lock ownership transfer and the dynamic helping quota in four combining implementations. On an aarch64 heterogeneous machine and an x86 asymmetric machine, we ran several micro-benchmarks and workloads to evaluate the performance of our core-aware implementations. The results show that core-aware combining implementations accelerate critical section execution and achieve better throughput than the original combining implementations.

Mapping Computations in Heterogeneous Multicore Systems with Statistical Regression on Program Inputs

A hardware configuration is a set of processors and their frequency levels in a multicore heterogeneous system. This article presents a compiler-based technique to match functions with hardware configurations. Such a technique consists of using multivariate linear regression to associate function arguments with particular hardware configurations. By showing that this classification space tends to be convex in practice, this article demonstrates that linear regression is not only an efficient tool to map computations to heterogeneous hardware, but also an effective one. To demonstrate the viability of multivariate linear regression as a way to perform adaptive compilation for heterogeneous architectures, we have implemented our ideas onto the Soot Java bytecode analyzer. Code that we produce can predict the best configuration for a large class of Java and Scala benchmarks running on an Odroid XU4 big.LITTLE board; hence, outperforming prior techniques such as ARM’s GTS and CHOAMP, a recently released static program scheduler.

Affinity-Based Task Scheduling on Heterogeneous Multicore Systems Using CBS and QBICTM

This work presents the grouping of dependent tasks into a cluster using the Bayesian analysis model to solve the affinity scheduling problem in heterogeneous multicore systems. The non-affinity scheduling of tasks has a negative impact as the overall execution time for the tasks increases. Furthermore, non-affinity-based scheduling also limits the potential for data reuse in the caches so it becomes necessary to bring the same data into the caches multiple times. In heterogeneous multicore systems, it is essential to address the load balancing problem as all cores are operating at varying frequencies. We propose two techniques to solve the load balancing issue, one being designated “chunk-based scheduler” (CBS) which is applied to the heterogeneous systems while the other system is “quantum-based intra-core task migration” (QBICTM) where each task is given a fair and equal chance to run on the fastest core. Results show 30–55% improvement in the average execution time of the tasks by applying our CBS or QBICTM scheduler compare to other traditional schedulers when compared using the same operating system.

Task Scheduling Strategy for Heterogeneous Multicore Systems

For heterogeneous computing systems, various types of processor cores cause system performance degradation due to uneven load. In addition, the inability of multitasking to match the appropriate processor core is also an urgent problem. This article proposes a swarm intelligence task scheduling strategy based on the genetic algorithm (GA) for high-performance heterogeneous multicore processors. In order to avoid the falling into local optimal solutions, we employ an adaptive mutation and injection strategy in the algorithm design. This swarm intelligence solution detects the computing capacities of different cores by processing specified tasks beforehand, and then an appropriate solution will be explored by introducing an adaptive mutation GA. Our technique aims to execute various types of tasks on heterogeneous processing cores for optimal performance. Experimental results show that this scheduling strategy can reduce the additional overhead and improve parallel computing efficiency and system performance.

Task-Level Aware Scheduling of Energy-Constrained Applications on Heterogeneous Multi-Core System

Minimizing the schedule length of parallel applications, which run on a heterogeneous multi-core system and are subject to energy consumption constraints, has recently attracted much attention. The key point of this problem is the strategy to pre-allocate the energy consumption of unscheduled tasks. Previous articles used the minimum value, average value or a power consumption weight value as the pre-allocation energy consumption of tasks. However, they all ignored the different levels of tasks. The tasks in different task levels have different impact on the overall schedule length when they are allocated the same energy consumption. Considering the task levels, we designed a novel task energy consumption pre-allocation strategy that is conducive to minimizing the scheduling time and developed a novel task schedule algorithm based on it. After getting the preliminary scheduling results, we also proposed a task execution frequency re-adjustment mechanism that can re-adjust the execution frequency of tasks, to further reduce the overall schedule length. We carried out a considerable number of experiments with practical parallel application models. The results of the experiments show that our method can reach better performance compared with the existing algorithms.

RESET: A real-time scheduler for energy and temperature aware heterogeneous multi-core systems

Nowadays, multi-core processing systems have to perform complex functionalities on densely packed multi-million gate platforms, making design issues like resource usage efficiency, energy consumption, temperature management of cores, etc. more challenging to handle. Since many of these processing platforms use batteries as their primary source of energy and are prone to an uncontrolled surge in temperatures, researchers have started focusing on these criteria in great detail. In this work, we propose a three-phase hierarchical resource allocation strategy called RESET for scheduling periodic tasks with a bounded number of migrations and context-switches. The first phase divides time into distinct intervals/windows based on deadlines of tasks. The exact proportional fairness needed for the progress of task executions is maintained at all window boundaries. The second phase performs energy-aware task-to-core assignments based on task execution requirements and operating frequency levels of cores. In the last phase, it splits tasks based on an input parameter δ and prepares a temperature-aware schedule for individual cores. Our experimental analysis shows that the presented strategy improves upon the state-of-the-art in terms of resource utilisation and reduces dynamic energy consumption and the average temperature of cores in the system.

Energy-aware primary/backup scheduling of periodic real-time tasks on heterogeneous multicore systems

For real-time embedded systems, energy management and fault tolerance are both critical. However these two objectives are often at odds, because extra resources needed to tolerate faults significantly increase the energy consumption. In this paper, we consider energy-aware and fault-tolerant scheduling of periodic real-time tasks. Our target platform is a heterogeneous multicore system. We reduce the energy consumption by both applying DVFS to scale the primary tasks, and maximizing the opportunities to cancel the back-up tasks in fault-free execution scenarios. To tolerate both transient and permanent faults, primary and backup copies of tasks are scheduled on different cores. Our framework consists of offline and online phases to manage energy and fault-tolerant scheduling of periodic tasks in tandem. The latter objective is achieved through an explicit task priority assignment phase, coupled with a dual queue based back-up delaying algorithm. In particular, we propose a scheme called Reverse Preference-Oriented Priority Assignment (RPPA) which is experimentally shown to be very effective to reduce the energy consumption. RPPA, when coupled with the dual-queue based delaying algorithm, outperforms other schemes and approaches the energy performance of a theoretical lower bound. All the proposed schemes satisfy the stringent timing and fault tolerance requirements of periodic real-time tasks while managing the energy consumption dynamically.

READY: Reliability- and Deadline-Aware Power-Budgeting for Heterogeneous Multicore Systems

Tackling the dark silicon problem in a heterogeneous multicore system, the temperature constraints across the system should be addressed carefully by assigning a proper set of tasks to a pool of the heterogeneous cores during the run-time. When such a system is utilized in a reliable/real-time application, the reliability/timing constraints of the application should also be augmented to the temperature constraints and make the tasks mapping problem more and more complex. To solve the mapping problem in such a situation, we propose READY; an online reliability- and deadline-aware mapping and scheduling algorithm for heterogeneous multicore systems. READY utilizes an adaptive power constraint (as a metric for temperature measurement) that is updated according to the number and position of the active cores on the chip. READY, first, attempts to meet the reliability target of the system by improving the reliability of each task. Then, it performs the mapping and scheduling of the tasks on cores of different islands, so that the peak power and timing constraints are met. The simulation results illustrate that while READY guarantees the timing constraints and meets reliability targets, it improves the peak-power-aware system schedulability (chip performance) by 23.77% (up to 40.69%).

A Real-time Image Recognition System Based on Improved Jacintonet Convolutional Neural Network

With the emergence and development of new automation industries such as unattended supermarkets and smart picking orchards, the demand for real-time systems based on embedded platforms is increasing day by day. Heterogeneous multi-core processors are widely used in modern integrated circuit design due to their advantages of low power consumption and high parallelism. More and more real-time systems are implemented on heterogeneous multi-core platforms. Based on the heterogeneous multi-core embedded system, the network parameters and architecture of jacintonet model are improved, and a real-time system for fruit image recognition is realized by using the improved network. A small sample data set is used to train the modified network and the trained network is imported into the system for testing. The result shows that the improved jacintonet network can run well on heterogeneous multi-core system and has the same recognition performance as the original network.

CASH: correlation-aware scheduling to mitigate soft error impact on heterogeneous multicores

With the exponential increase in the number of transistors under fast-paced technology progress, the soft error induced reliability issue is becoming even more challenging in heterogeneous multicore processor design. As there are significant opportunities to mitigate the soft error impacts through heterogeneous multicore scheduling, we show in this paper that the correlation among multiple applications exhibits important reliability characteristics, by defining a new metric to measure the system-level vulnerability factor of multiple applications and an approximate estimator to evaluate the metric fast and accurately for effective scheduling decisions. To approach these issues, we propose CASH, a Correlation-Aware Scheduling strategy to optimise heterogeneous multicore system reliability. Comprehensive simulation results demonstrate that the proposed approach is promising, achieving up to 21.4% reliability improvement with only 3.6% performance degradation when compared with performance-oriented scheduling policy.