Heterogeneous Integration Technology Research Articles

(Invited) Advanced Heterogeneous Integration of InP HBT and CMOS/SiGeBiCMOS Technologies

Under the Compound Semiconductor Materials on Silicon (COSMOS) DARPA program, Northrop Grumman Aerospace Systems (NGAS) has developed an advanced heterogeneous integration technology to intimately integrate compound semiconductor (CS) devices and circuits on CMOS/SiGeBiCMOS wafers. The integration approach is based on a direct face-to-face bonding between pre-fabricated InP chiplets and Si wafers. The heterogeneous integration process is compatible with any semiconductor technology. This integration enables significant improvement in dynamic range and bandwidth of high performance mixed signal circuits. In this paper we describe the integration approach and present two demonstration circuits.

A Versatile Optical Head for 3D IC TSV Integration Process Control

3D Integration of miniaturized systems at wafer level generates new needs of metrology and defects inspection for the control of TSV geometries, temporary wafer bonding, wafer thinning, via interconnects technology and of wafer/die stacks. In this paper we demonstrate the capabilities of a versatile optical measurement system combining several microscopy and interferometry techniques in the visible and near infrared wavelength range. I. INTRODUCTION AND BACKGROUND ALL roadmaps predict a large spread of 3D heterogeneous integration technologies for the fabrication of miniaturized systems in the coming years1. Beside a large development of new fabrication processes, 3D integration generates new challenges in terms of metrology and defects inspection for wafer/die bonding, thinning and interconnection processes as well as for 3D architectures. Adaptation and/or combination of existing techniques and the development of new techniques become necessary in order to perform non destructive, fast and inspections or quantitative measurements on large area wafers with high lateral and vertical resolutions. In this work we describe results obtained with an optical system combining several microscopy and interferometry techniques.

A Wafer-level System Integration Technology Incorporates Heterogeneous Devices

A pseudo-SoC technology incorporating heterogeneous devices has been developed by applying a wafer-level system integration technology. The pseudo-SoC is set up to realize one microchip with heterogeneous devices made by using individual processes for epoxy resin, insulating layer and redistribution layer, respectively. The individual heterogeneous devices are embedded in the epoxy resin to reconfigure the integration wafer. As the insulating layer and redistribution layer are formed by semiconductor wafer process without interposer substrate, the pseudo-SoC enables integration density and signal transmission speed as identical to that of SoC. Also, as the commercial LSI devices and peripheral passive components are able to use for the system integration, the pseudo-SoC enables reduction of time-to-market as identical that of SiP. This paper describes the heterogeneous devices integration technologies and focuses on the pseudo-SoC that overcomes the limitation of system integration and provides the complementary advantages of SiP and SoC with various applications.

Localization in mobile wireless and sensor networks

Accurate localization or tracking of wireless devices is a crucial requirement for many emerging location-aware systems. Fields of applications include search and rescue, medical care, intelligent transportation, locationbased billing, security, home automation, industrial monitoring and control, location-assisted gaming, and social networking. During the last few years, there have been intensive research activities in this area and various solutions have been investigated. The main trend now is toward the integration of heterogeneous technologies to ensure global coverage and high accuracy in all possible scenarios, leading to a seamless localization system available anywhere anytime. While satellite-based navigation is well consolidated for open sky scenarios, localization in harsh environments (e.g., indoor or in urban canyons) is still an open issue that requires complementary wireless networks. Cellular systems, local/personal area networks, ad hoc, and wireless-sensor networks can be configured to support localization functionality. Indoor environments, however, are particularly challenging because of severe multipath and non-line-of-sight (NLOS) propagation. In this context, advanced signal processing algorithms must be employed in order to guarantee positioning robustness, such as NLOS identification and mitigation, fusion of data from different sources, and Bayesian methods to enclose any a priori information (e.g., dynamic models for mobile positioning). An important area of research is cooperative localization, which is expected to significantly improve both accuracy and coverage by exploiting all the available measurements on a peer-to-peer basis; efficient protocols and procedures have to be designed to minimize communication overheads and energy consumption. Measurement campaigns are essential for calibrating signal models and testing localization algorithms. A valuable tool for benchmarking algorithms is also provided by fundamental performance bounds, which are being actively analyzed as guidelines for the design of efficient positioning systems. The objective of this special issue, which was promoted under the auspices of the EC Network of Excellence in Wireless Communications NEWCOM++ (in particular, the Work Package WPR.B on Localization and Positioning Techniques), was to gather recent advances in both signal processing and communications areas, for localization in mobile wireless and sensor networks. Articles were solicited on both experimental and theoretical aspects, including new positioning algorithms and methodologies, system design and configuration, performance analysis and measurement campaigns. We received a total of 56 manuscripts addressing the above issues and challenges, of which 16 were selected for publication. Selection of each article was the result of a careful assessment by at least two (mostly three) independent reviewers with expertise on localization and wireless networking. Articles went through a minimum of two to a maximum of four revision phases before acceptance. Accepted articles belong to four main research areas: integration of positioning and communication functionalities, robustness to NLOS errors, indoor positioning, and localization in wireless sensor networks (WSNs). The first group of articles deals with the interaction of positioning and communications at different layers of the protocol stack. Connectivity issues are studied in Gao et al., which considers the relation between distance and communication hops, accounting for the border effect and dependence problems, for a model that is more realistic than the traditional unit-disk graph model. A related problem is investigated in the study of Moragrega et al., which deals with location-aware cluster formation. The authors propose LACFA, a distributed network formation algorithm that significantly increases the probability of localization of sensors in a cluster-tree topology. On the physical layer, Schmeink et * Correspondence: nicoli@elet.polimi.it Dipartimento di Elettronica e Informazione, Politecnico di Milano, Milan, Italy Full list of author information is available at the end of the article Nicoli et al. EURASIP Journal on Wireless Communications and Networking 2011, 2011:197 http://jwcn.eurasipjournals.com/content/2011/1/197

Overview of low temperature hydrophilic Ge to Si direct bonding for heterogeneous integration

Germanium is gaining interest in two important areas of electronics; for high performance metal oxide semiconductor field effect transistors due to the high carrier mobility and for imaging and optical applications due to its superior absorption in the infrared range. Optimally, germanium will be integrated with existing silicon electronics to enhance electrical and optical properties. One method for integration of germanium with silicon is direct wafer bonding of the two materials. In this paper, wafer-level germanium–silicon heterogeneous integration technologies are investigated and described in detail, including structural and electrical features of bonded hetero-structure.

Research on Heterogeneous Data Integration of Coal Mine Safety Monitoring Based on GIS Technology

Coal mine safety information’s remote monitoring, browsing, querying is the general trend of Chinese coal industry information development. The paper analysis coal mine safety monitoring based on heterogeneous data sources, depth study heterogeneous data integration technology. At last, the paper proposed and designed based on OPC technology heterogeneous data integration’s overall program of coal mine safety monitoring. After tested the system is stabled and achieved good results in practice.

How Evolving Network Access and Network Management Technologies are Redefining the Competitive Wireless Markets

This paper examines some of the key problems users encounter when accessing current generation wireless networks. Using a case study of a hypothetical user, the authors explore the emerging services and the new broadband wireless network technologies necessary to carry them out. This paper analyses the issues associated with an observed trend in the industry that exposes potential changes to the long-term, rigid commercial relation between wireless providers and users: as a result of a range of evolved broadband wireless access standards and technologies, autonomic communications and policy-based management, and new pricing schemes, consumers will likely face new opportunities to enter short-term and spot contracts with the new wireless providers. This new landscape also allow multiple competing Access Providers (APs) to dynamically assign prices, and poses new and interesting challenges to the regulatory function. The paper also discusses a framework for the integration of heterogeneous technologies and management policies based on the network context that make up this emerging, hybrid wireless landscape, and describes the economic characteristics of new markets likely to arise.

Heterogeneous Chip Integration Process for Flexible Wireless Microsystem Application

This paper presents a low-cost heterogeneous integration technology combining the previously developed bump less radio-frequency (RF) system-on-a-package scheme with a special surface cleaning process to assemble a complementary metal-oxide-semiconductor chip with an organic substrate (SU-8/ polydimethylsiloxane) by low-temperature Au-Au thermocompressive bonds (<; 200°C) for flexible wireless microsystem fabrication. The RF performance of -15 dB return loss and -0.25 dB insertion loss at 40 GHz and above 6 MPa bonding strength of a microstrip-to-coplanar-waveguide interconnect transition between the chip and the substrate make the technology practical for flexible wireless microsystem integration.

Wafer-Level Heterogeneous Integration for MOEMS, MEMS, and NEMS

Wafer-level heterogeneous integration technologies for microoptoelectromechanical systems (MOEMS), microelectromechanical systems (MEMS), and nanoelectromechanical systems (NEMS) enable the combination of dissimilar classes of materials and components into single systems. Thus, high-performance materials and subsystems can be combined in ways that would otherwise not be possible, and thereby forming complex and highly integrated micro- or nanosystems. Examples include the integration of high-performance optical, electrical or mechanical materials such as monocrystalline silicon, graphene or III-V materials with integrated electronic circuits. In this paper the state-of-the-art of wafer-level heterogeneous integration technologies suitable for MOEMS, MEMS, and NEMS devices are reviewed. Various heterogeneous MOEMS, MEMS, and NEMS devices that have been described in literature are presented.

Heterogeneous integration – packaging on and in organic substrates

Decreasing the bill of materials for an electronic device saves development time, money and space. The integration of more and more functions not only on the chip (SoC; system on chip) but also in the package (SiP; system in package) is therefore a natural and very important step in the devolvement of micro electronics. Realizing the goal of Ambient Intelligence requires low cost system solutions where all necessary components are integrated. The future will be a combination of “System on Chip”- and “System in Package” solution called as “Heterogeneous Integration”. As far as technical and economical feasible “System on Chip” solutions will be chosen, the adoption to various applications and the integration of highly complex systems containing non-electronic functions will be carried out more cost efficiently, with a high degree of miniaturization and flexibility in “Heterogeneous Integration”. “Heterogeneous Integration” integrates several chips or components in one package (system in package or SiP) and carries out the interface to the application environment. This paper will summarize a variety of heterogeneous integration technologies researched at Fraunhofer IZM with a strong focus on embedding in printed circuit boards and embedding in molded reconfigured wafers – looking also on the requirements of sensor packaging. Not only the technological principles but also specific material demands and necessary processes as 3D routing and also 3D interconnection will be discussed in detail. Application examples and technology demonstrators from will be shown to demonstrate technological potential and challenges of miniaturized heterogeneous integration by embedding from a European perspective.

Evolution of Nonvolatile Resistive Switching Memory Technologies: The Related Influence on Hetrogeneous Nanoarchitectures

The emergence of different and disparate materials together with the convergence of both the 'old' and 'emerging' technologies is paving the way for integration of heterogeneous technologies that are likely to extend the limitations of silicon technology beyond the roadmap envisaged for complementary metal-oxide semiconductor. Formulation of new information processing concepts based on novel aspects of nano-scale based materials is the catalyst for new nanoarchitectures driven by a different perspective in realization of novel logic devices. The memory technology has been the pace setter for silicon scaling and thus far has pave the way for new architectures. This paper provides an overview of the inevitability of heterogeneous integration of technologies that are in their infancy through initiatives of material physicists, computational chemists, and bioengineers and explores the options in the spectrum of novel non-volatile memory technologies considered as forerunner of new logic devices.

An Interconnecting Technology for RF MEMS Heterogeneous Chip Integration

An interconnecting technology using a Au-Au thermocompressive bond has been successfully developed for microelectromechanical system (MEMS) heterogeneous chip integration in this paper. The Daisy chain and RF transition structures are both designed and fabricated for the electrical characterization of the interconnect scheme. Measured dc contact resistance is about 14 ±5 m¿ for the bonding interface of Ni (1 ¿m)/Au (0.4 ¿m)/Au (0.4 ¿m)/Ni (1 ¿m) with a pad size of 40 ¿m in diameter. The electrical transition between two chips, which have coplanar waveguides (CPWs) and microstrip lines, respectively, can be well interconnected with less than - 15 dB return loss and - 1.8 dB insertion loss up to 50 GHz without implementing complex structure designs and extra impedance matching networks in the transition by employing this technology. Meanwhile, it is found that the mechanical strength for the interconnecting bond can be as large as 100 MPa. A low-power RF low-noise amplifier has been successfully designed, fabricated, and utilized in this paper to demonstrate the feasibility of the interconnecting technology for RF MEMS heterogeneous chip integration by integrating a Taiwan Semiconductor Manufacturing Corporation 0.18-¿m RF complimentary metal-oxide-semiconductor chip with a silicon carrier, where high <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Q</i> MEMS inductors are fabricated and utilized for good circuit performance in terms of excellent impedance matching, power gain, and gain flatness.

Interconnect Technologies for Heterogeneous 3D Integration : CMOS and MEMS

AbstractMicroelectromechanical Systems (MEMS) market is a rapidly growing market with a wide range of devices. Most of these devices require an interaction with an electronic circuit, and with the increasing number of high performance MEMS devices that are being introduced, a demand for integrating CMOS and MEMS using high-density and low-parasitic interconnects have also been on the rise.Unfortunately, conventional methods of integrating CMOS with MEMS cannot provide the high density and low-parasitic interconnections required by modern high performance MEMS devices, and at the same time provide the flexibility required to accommodate new devices that are made using new materials and highly innovative fabrication processes.Heterogeneous 3D integration of MEMS and CMOS has the potential to provide both the performance and the integration flexibility; however there are two interconnect challenges that need to be addressed. This paper outlines the details of these interconnect challenges and introduces two interconnect technologies, Mechanically Flexible Interconnects (MFI) and Through-Silicon Via (TSV), developed specifically to address these challenges.

3D System-on-Chip technologies for More than Moore systems

3D integration is a key solution to the predicted performance problems of future ICs as well as it offers extreme miniaturization and cost-effective fabrication of More than Moore products. Through silicon via (TSV) technologies enable high interconnect performance compared to 3D packaging. At present TSVs are associated with a relatively high fabrication cost, but research world wide strive to bring the cost down to an acceptable level. An example of a 3D System-on-Chip (3D-SOC) technology is to introduce a post backend-of-line TSV process as an optimized technology for heterogeneous system integration. The introduced ICV-SLID process, that combines both TSVs and bonding, enables 3D integration of fabricated devices. Reliability issues related to thermo-mechanical stress caused by the TSV formation and the bonding are considered. 3D-SOC technology choices made to realize a heterogeneous ultra-small IC stack for a wireless tire pressure monitoring system (TPMS) as an automotive application are described.

Novel interconnection technology for heterogeneous integration of MEMS–LSI multi-chip module

We developed novel interconnection technology for heterogeneous integration of MEMS and LSI multi-chip module, in which MEMS and LSI chips would be horizontally integrated on substrate and vertically stacked each others. The cavity chip composed of deep Cu TSV-beam lead interconnections was developed for interconnecting MEMS chips with high step height of more than few hundreds micrometer without the degradation of sensing elements. Fundamental characteristics were successfully obtained from pressure sensing MEMS chip with 360 μm thickness, which was connected to Si substrate by the cavity chip. MEMS and LSI chips were vertically integrated by using the cavity chip without any changing of chip design and extra processes. This interconnection technology can give strong solution for heterogeneous integration of MEMS and LSI chips multi-chip module.

Nanoimprint lithography and surface modification as prospective technologies for heterogeneous integration

AbstractNanoimprint lithography offers the possibility to pattern wafer‐scale surfaces with nm‐sized structures in polymers reaching the 10 nm lateral size. Printable polymers can be tailored to have a surface upon which molecules self‐assemble. Furthermore, the resulting surfaces may be heterogeneously structured with or without etching away parts of imprinted polymers, in order to provide a flexible platform for structured surfaces with functional materials. We review progress in these combined approaches and discuss three examples: (a) a process to modify printed surfaces in order to grow polymer brushes, (b) a technique to realise patterned surfaces with different emission colours by using a one‐step gas phase deposition of a single type of molecules on pre‐patterned solid substrates and (c) a general method suitable to pattern different conducting polymer species at the nanoscale range by combining nanoimprint lithography process and a lift‐off process. (© 2008 WILEY‐VCH Verlag GmbH &amp; Co. KGaA, Weinheim)

Bonding for 3-D Integration of Heterogeneous Technologies and Materials

Modern electronic applications demand more and more complex, multifunctional microsystems with performance characteristics which can only be achieved by using best-of-breed materials and device technologies. Three-dimensional (3-D) integration of separate, individually complete device layers provides a way to build complex heterogeneous microsystems without compromising the system performance and fabrication yield. In the 3-D integration approach, each device layer is fabricated separately using optimized materials and processes. The layers are bonded and interconnected through area array vertical interconnects with lengths on the order of microns. This paper will review bonding techniques for high density area array 3-D integration of integrated circuits, focusing on techniques suitable for die-to-die and die-to-wafer bonding configurations.

Bonding for 3-D Integration of Heterogeneous Technologies and Materials

not Available.

Integrated Optical Sensor in a Digital Microfluidic Platform

The advent of digital microfluidic lab-on-a-chip (LoC) technology offers a platform for developing diagnostic applications with the advantages of portability, increased automation, low-power consumption, compatibility with mass manufacturing, and high throughput. However, most digital microfluidic platforms incorporate limited optical capabilities (e.g., optical transmission) for integrated sensing, because more complex optical functions are difficult to integrate into the digital microfluidic platform. This follows since the sensor must be compatible with the hydrophobic surfaces on which electrowetting liquid transport occurs. With the emergence of heterogeneous photonic component integration technologies such as those described herein, the opportunity for integrating advanced photonic components has expanded considerably. Many diagnostic applications could benefit from the integration of more advanced miniaturized optical sensing technologies, such as index of refraction sensors (surface plasmon resonance sensors, microresonator sensors, etc.). The advent of these heterogeneous integration technologies, that enable the integration of thin-film semiconductor devices onto arbitrary host substrates, enables more complex optical functions, and in particular, planar optical systems, to be integrated into microfluidic systems. This paper presents an integrated optical sensor based upon the heterogeneous integration of an InGaAs-based thin-film photodetector with a digital microfluidic system. This demonstration of the heterogeneous integration and operation of an active optical thin-film device with a digital microfluidic system is the first step toward the heterogeneous integration of entire planar optical sensing systems on this platform.

Epitaxial and Non-Epitaxial Heterogeneous Integration Technologies at NGST

ABSTRACTTo meet increasingly challenging and complex systems requirements, it is not enough to use one single semiconductor technology but to integrate several high performance technologies in an efficient and cost effective way. Heterogeneous integration (HI) approaches lead to a significant higher design flexibility and performance. In this paper we present some of the HI approaches that are being used and developed at Northrop Grumman Space Technology (NGST) that include selective epitaxial growth, metamorphic growth and wafer level packaging (WLP) technology. More recently we are developing a scaled and selective wafer packaging technique to integrate III-V semiconductors with silicon under the COSMOS DARPA program.