Heterogeneous Embedded System Research Articles

A novel lightweight CNN for chest X-ray-based lung disease identification on heterogeneous embedded system

The global spread of epidemic lung diseases, including COVID-19, underscores the need for efficient diagnostic methods. Addressing this, we developed and tested a computer-aided, lightweight Convolutional Neural Network (CNN) for rapid and accurate identification of lung diseases from 29,131 aggregated Chest X-ray (CXR) images representing seven disease categories. Employing the five-fold cross-validation method to ensure the robustness of our results, our CNN model, optimized for heterogeneous embedded devices, demonstrated superior diagnostic performance. It achieved a 98.56% accuracy, outperforming established networks like ResNet50, NASNetMobile, Xception, MobileNetV2, DenseNet121, and ViT-B/16 across precision, recall, F1-score, and AUC metrics. Notably, our model requires significantly less computational power and only 55 minutes of average training time per fold, making it highly suitable for resource-constrained environments. This study contributes to developing efficient, lightweight networks in medical image analysis, underscoring their potential to enhance point-of-care diagnostic processes.

Evaluating virtualization for fog monitoring of real-time applications in mixed-criticality systems

Technological advances in embedded systems and the advent of fog computing led to improved quality of service of applications of cyber-physical systems. In fact, the deployment of such applications on powerful and heterogeneous embedded systems, such as multiprocessors system-on-chips (MPSoCs), allows them to meet latency requirements and real-time operation. Highly relevant to the industry and our reference case-study, the challenging field of nuclear fusion deploys the aforementioned applications, involving high-frequency control with hard real-time and safety constraints. The use of fog computing and MPSoCs is promising to achieve safety, low latency, and timeliness of such control. Indeed, on one hand, applications designed according to fog computing distribute computation across hierarchically organized and geographically distributed edge devices, enabling timely anomaly detection during high-frequency sampling of time series, and, on the other hand, MPSoCs allow leveraging fog computing and integrating monitoring by deploying tasks on a flexible platform suited for mixed-criticality software, leading to so-called mixed criticality systems (MCSs). However, the integration of such software on the same MPSoC opens challenges related to predictability and reliability guarantees, as tasks interfering with each other when accessing the same shared MPSoC resources may introduce non-deterministic latency, possibly leading to failures on account of deadline overruns. Addressing the design, deployment, and evaluation of MCSs on MPSoCs, we propose a model-based system development process that facilitates the integration of real-time and monitoring software on the same platform by means of a formal notation for modeling the design and deployment of MPSoCs. The proposed notation allows developers to leverage embedded hypervisors for monitoring real-time applications and guaranteeing predictability by isolation of hardware resources. Providing evidence of the feasibility of our system development process and evaluating the industry-relevant class of nuclear fusion applications, we experiment with a safety-critical case-study in the context of the ITER nuclear fusion reactor. Our experimentation involves the design and evaluation of several prototypes deployed as MCSs on a virtualized MPSoC, showing that deployment choices linked to the monitor placement and virtualization configurations (e.g., resource allocation, partitioning, and scheduling policies) can significantly impact the predictability of MCSs in terms of Worst-Case Execution Times and other related metrics.

Online energy-efficient scheduling of DAG tasks on heterogeneous embedded platforms

Heterogeneous distributed computing systems are becoming more and more common to process practical applications in many embedded systems, where energy efficiency is very important, especially for battery-powered systems. This paper studies the problem of how to adaptively schedule dynamic applications on the fly on a heterogeneous embedded system such that the system’s energy consumption can be minimized, while meeting applications’ response time and reliability requirements simultaneously. We first study the problem of scheduling a set of static applications. This problem is formulated as an integer nonlinear programming problem by deriving the response time equation of directed acyclic graph (DAG) applications. A reliability-aware scheduling strategy is designed to solve this problem. On top of this strategy, we develop an algorithm that tries to use as few processors as possible to finish the computation because, in this way, the system’s static energy can be saved. We then extend this solution to handle the problem of scheduling dynamic applications. By developing a task migration algorithm and a schedule adjustment algorithm, the system can adaptively handle suspended and newly released applications on the fly. Extensive simulation experiments are conducted, and the results demonstrate the high efficiency of our proposed approaches against some classic heuristics and a state-of-the-art approach.

Towards an advanced neurotechnological system: colorimetric sensing with a novel grism-based spectrometer, functionalized gold nanoparticles and a heterogeneous embedded system.

Neurotransmitter sensing in the brain is crucial for the understanding of neuro-degenerative diseases. Most modern methods for the purpose rely on bulky instruments or are disruptive to the neurotransmitter medium. In this work, we describe and evaluate the design of a novel, compact and non-invasive instrument for neurotransmitter detection based on the colorimetric sensing method. The instrument includes a grism-based spectrometer that measures the wavelength shift of gold nanoparticles that are functionalized with aptamers to act as neurotransmitter-specific markers. It also includes microfluidic and electronic subsystems for sample preparation and control, and processing of the obtained signal. The instrument is tested with gold nanoparticles and its performance is compared to that of a commercial instrument, showing that the designed prototype matches the commercial instrument in performance while being much smaller, and it can surpass it with further improvements. This article is part of the theme issue 'Advanced neurotechnologies: translating innovation for health and well-being'.

Energy-efficient distributed password hash computation on heterogeneous embedded system

This paper presents the improved version of our cool Cracker cluster (cCc), a heterogeneous distributed system for parallel and energy-efficient bcrypt password hash computation. The cluster consists of up to 8 computational units (nodes) with different performances measured in bcrypt hash computations per second [H/s]. In the cluster, nodes are low-power heterogeneous embedded systems with programmable logic containing specialized hash computation accelerators. In the experiments, we used a combination of Xilinx Zynq-series SoC boards and ZTEX 1.15y board which was initially used as a bitcoin miner. Zynq based nodes use the improved version of our custom bcrypt accelerator, which executes the most costly parts of the bcrypt hash computation in programmable logic. The cluster was formed around the famous open-source password cracking software package John the Ripper (abbr. JtR). On the communication layer, we used Message Passing Interface (MPI)library with a standard Ethernet network connecting the nodes. To mitigate the different performances among the cluster nodes and to balance the load, we developed and implemented password candidate distribution scheme based on the passwords' probability distribution, i.e. the order of appearance in the dictionary. We tested individual nodes and the cluster as a whole, trying different combinations of nodes and evaluating our distribution scheme for password candidates. We also compared our cluster with various GPU implementations in terms of performance, energy-efficiency, and price-efficiency. We show that our solution outperforms other platforms such as high-end GPUs, by a factor of at least 3 in terms of energy-efficiency and thus producing less overall cost of password attack than other platforms. In terms of the total operational costs, our cluster pays off after 4500 cracked passwords for a bcrypt hash with cost parameter 12, which makes it more appealing for real-world password-based system attacks. We also demonstrate the scalability of our cCc cluster.

MOGATS: a multi-objective genetic algorithm-based task scheduling for heterogeneous embedded systems

Multi-objective optimisation is an unavoidable requirement in different steps of embedded systems design, including task mapping and scheduling. In this paper, a new multi-objective genetic algorithm-based task mapping and scheduling (abbreviated as MOGATS) is presented for heterogeneous embedded system design. In MOGATS, the architecture of the hardware platform and the set of tasks in the form of a task graph are assumed to be given as the inputs. Task mapping and scheduling problems are modelled as a genetic algorithm-based optimisation approach. In summary, our task scheduling tool is the first multi-objective task scheduling in the design stage of embedded systems to help the designer to figure out which set of scheduling would provide their desired outcome. Additionally, in comparison to EGA-TS, the state-of-art task scheduling algorithm, in terms of speedup and SLR, we have gain 27.8 and 28.6 immediate improvements respectfully.

Minimizing Resource Consumption Cost of DAG Applications With Reliability Requirement on Heterogeneous Processor Systems

Resource consumption cost minimization is important in embedded systems due to their limited resource and high computation load. Previous approaches apply either meta-heuristic algorithms such as genetic algorithm or simple heuristics to minimize the resource consumption cost, which, however, are computationally expensive and sometimes ineffective. In this article, we propose how to schedule a directed acyclic graph application with reliability requirement in a heterogeneous embedded system. The scheduling aim is to minimize system resource consumption cost. We start by finding a quasi-optimal solution that minimizes the resource consumption cost in ignorance of reliability. Then, we introduce an indicator that price the tradeoff between reliability and resource consumption cost, based on which we build a scheme that progressively tunes this schedule toward improving its reliability. We also explore an approach that updates this indicator in a lightweight way. Compared to several state-of-the-art approaches such as MRCRG, experimental results demonstrate that our approach constantly outperforms them, and its superiority becomes more significant with the enhancement of reliability requirement.

Energy Optimization by Software Prefetching for Task Granularity in GPU-Based Embedded Systems

Energy saving and optimization play an increasingly important role in industrial electronic systems. A heterogeneous embedded system is composed of a general-purpose central processing unit with an enhanced module of graphics processing units (GPU). This article explores the effective strategies of task granularity and software prefetching for energy optimization. In this article, we propose a novel energy optimization model for GPU-based embedded systems by harnessing a communication-based pipeline spatial and temporal relation. We analyze the characteristics of a multiple thread execution of parallel GPUs. We present an effective algorithm for the dynamic power optimization with the adaptively adjusted distance of software prefetching. The experimental results show that the dynamic energy consumption can be saved by 22.1% and 21.8%, respectively, under two prefetching strategies (register and shared memory) without loss of performance. We demonstrate the effectiveness of the proposed methods for energy saving and consumption reduction of performance driven computing in industrial scenarios.

Mixed Cryptography Constrained Optimization for Heterogeneous, Multicore, and Distributed Embedded Systems

Embedded systems continue to execute computational- and memory-intensive applications with vast data sets, dynamic workloads, and dynamic execution characteristics. Adaptive distributed and heterogeneous embedded systems are increasingly critical in supporting dynamic execution requirements. With pervasive network access within these systems, security is a critical design concern that must be considered and optimized within such dynamically adaptive systems. This paper presents a modeling and optimization framework for distributed, heterogeneous embedded systems. A dataflow-based modeling framework for adaptive streaming applications integrates models for computational latency, mixed cryptographic implementations for inter-task and intra-task communication, security levels, communication latency, and power consumption. For the security model, we present a level-based modeling of cryptographic algorithms using mixed cryptographic implementations. This level-based security model enables the development of an efficient, multi-objective genetic optimization algorithm to optimize security and energy consumption subject to current application requirements and security policy constraints. The presented methodology is evaluated using a video-based object detection and tracking application and several synthetic benchmarks representing various application types and dynamic execution characteristics. Experimental results demonstrate the benefits of a mixed cryptographic algorithm security model compared to using a single, fixed cryptographic algorithm. Results also highlight how security policy constraints can yield increased security strength and cryptographic diversity for the same energy constraint.

I<SUP>2</SUP>C Based Networking for Implementing Heterogeneous Microcontroller Based Distributed Embedded Systems

Realising a distributed heterogeneous embedded system using I 2 C requires investigations and findings related to design of networking, architecture, message design and flow for prioritisation, and datagram design. The existing methods for effecting communication among the heterogeneous embedded systems interconnected through I 2 C communication system have not addressed the heterogeneity issues. To suffice, new methods for designing Heterogeneous Embedded networks, communication systems, message flow systems and the message design have presented. The methods have been applied to an existing distributed embedded system and the results obtained proved to be exact as required. Every distributed embedded system is different and the kind of Hardware and protocol conversions required is dependent on the type of distributed embedded system. It has been shown in the paper the kind of conversions that must be undertaken considering I 2 C as the communication method and a set of selected heterogeneous embedded systems that are used for developing an application that monitors and controls the temperatures within a Nuclear reactor system. The way the communication must be effected is dependent on the number of masters and the slaves that must be supported on the network. A communication system architecture that suits the pilot project has been presented. A design flow method which uses priority queues has been presented to effect the communication according to the flow required. The design of datagram required for effecting the communication has also been presented in the paper. The methods have been applied to an existing distributed heterogeneous embedded system that monitors and controls the temperatures with a Nuclear reactor system and the results have been found to be exact fulfilling all the application requirements.

Task Optimization Scheduling Algorithm in Embedded System Based on Internet of Things

Embedded system has been widely used in the network, server, etc., and it has a good application prospect with the development of Internet of things. In the embedded heterogeneous computing system, task scheduling is the key to deciding the system performance. For multi-task scheduling, the current scheduling algorithm is mostly based on task duplication, without a full consideration of the correlation between the predecessor task and its subsequent tasks. Based on modeling the multi-frame task scheduling problem in the heterogeneous embedded system, this paper analyzes the availability of tasks through the design of genetic algorithm, so as to verify the algorithm's feasibility, which is of important guiding significance for the multi-task scheduling in the embedded heterogeneous computing system.

Design of Distributed Heterogeneous Embedded Systems in DDFCharts

The use of formal models of computation in dealing with increasing complexity of embedded systems design is gaining attention. A successful model of computation must be able to handle both control-dominated and data-dominated behaviors, which are most often simultaneously present in complex embedded systems. Besides behavioral heterogeneity, direct support for modeling distributed systems is also desirable, since an increasing number of embedded systems belong to this category. In this paper, we present distributed DFCharts (DDFCharts), a language based on a formal model that targets distributed heterogeneous embedded systems. Its top hierarchical level is made suitable to capture distributed systems. Behavioral heterogeneity is addressed by composing finite-state machines (FSMs) and synchronous dataflow graphs (SDFGs). We illustrate modeling in DDFCharts with practical examples and describe its implementation on heterogeneous target architecture.

EWD

We present the EWD design environment and methodology, a modeling and simulation framework suited for complex and heterogeneous embedded systems with varying degrees of expressibility and modeling fidelity. This environment promotes the use of multiple models of computation (MoCs) to support heterogeneity and metamodeling for conformance tests of syntactic and static semantics during the process of modeling. Therefore, EWD is a multiple MoC modeling and simulation framework that ensures conformance of the MoC formalisms during model construction using a metamodeling approach. In addition, EWD provides a suite of translation tools that generate executable models for two simulation frameworks to demonstrate its language-independent modeling framework. The EWD methodology uses the Generic Modeling Environment for customization of the MoC-specific modeling syntax into a visual representation. To embed the execution semantics of the MoCs into the models, we have built parsing and translation tools that leverage an XML-based interoperability language. This interoperability language is then translated into executable Standard ML or Haskell models that can also be analyzed by existing simulation frameworks such as SML-Sys or ForSyDe. In summary, EWD is a metamodeling driven multitarget design environment with multi-MoC modeling capability.

Non-dominated Sorting Genetic Algorithms for Heterogeneous Embedded System Design

The design of complex embedded systems involves the simultaneous optimization of several conflicting and competing objectives. Instead of a single global optimal solution, there exist a set of Pareto optimal solutions. In this study we have used a multi-objective evolutionary optimization algorithms called non-dominated sorting genetic algorithm (NSGA), which will suit to the requirements of designing a complex heterogeneous embedded system. Further, the algorithm is rigorously tested using Video Codec as a case study

Heterogeneous embedded system with “microcontroller‐CPLD” based shared memory interface for sensor applications

PurposeAims to design a heterogeneous embedded system with CPLD and microcontroller as co‐processors sharing a memory module.Design/methodology/approachThe system receives external analog input signal, which is applied to the PIC 16F73 microcontroller. Upon converting the data in to digital format using the on‐chip ADC, the PIC stores the digitized version in the SRAM (HCM 6264) chip. SRAM HCM 6264 has been used as a shared memory model, of which both the PIC and CPLD can access all the locations. Once the PIC passes controls to the CPLD, the further processing is carried out by the CPLD without any intervention of the PIC. This is a true example of co‐processing of the architecturally diversified computing modules from completely different vendors with totally different programming suits.FindingsThe board has been tested with IC temperature sensors and also found to be useful for sensor array applications involving three types of processing viz. analog (through instrumentation amplifier), real‐time digital (through microcontroller) and customized reconfigurable digital (with the CPLD).Practical implicationsThe system has several potential applications in avionics, military and robotic embedded systems, which have inherent real‐time constraints that need to be supported by the underlying hardware and driver programs.Originality/valueDiscusses the rare and unique combination of diversified processing core to build an embedded system.