Heterogeneous Computing Platforms Research Articles

An Approach to Generating Recommendations for Improving the Performance of Software for Heterogeneous Computing Platforms

The widespread use of heterogeneous computing platforms, as well as the incorporation of computationally expensive implementations of intelligent data analysis algorithms into modern software systems leads to the demand in moving software fragments to most suitable hardware accelerators that are available on a heterogeneous computing platform. In this research, we propose an approach to the generation of recommendations for improving the performance of software systems by finding candidate algorithm implementations for hardware acceleration, and by suggesting the most suitable hardware accelerator among the specialized processors that are available on a given heterogeneous computing platform. The proposed approach is based on a code-to-code search technique, which extracts code fragments from an abstract syntax tree (AST), converts them into vectors containing program features, and compares the vectors with the query program vector. The obtained results confirm that the use of automatically recommended hardware accelerators for the code fragments identified using the proposed approach indeed allows to increase the performance of software systems solving machine learning tasks.

Large‐scale homo‐ and heterogeneous parallel paradigm design based on CFD application PHengLEI

SummaryThe development of computational fluid dynamics (CFD) highly depends on high‐performance computers. Computer hardware has evolved rapidly, yet scalable CFD parallel software remains scarce. In this article, we design a highly scalable CFD parallel paradigm for both homogeneous and heterogeneous supercomputers. The paradigm achieves the separation of communication and computation and automatically adapts to various solvers and hardware environments, thus reducing programming difficulties and increasing automatic parallelization. Meanwhile, the number of communications is greatly reduced and the scalability of the program is improved through implementing centralized communication and two‐level partitioning techniques. Complex flow problems for real aircraft were then computed on different hardware platforms with a grid size of ten billion. The homogeneous computer hardware includes Intel Xeon Gold 6258R and Phytium 2000+ processors, and the heterogeneous computer platforms include NVIDIA Tesla V100 and SW26010 processors. High parallel efficiency was obtained on all computer platforms, verifying that the paradigm has good automatic parallelization, scalability, and stability. The paradigm in this article has an important reference value for CFD massively parallel computing and can promote the development and application of CFD technology.

A Flexible and General-Purpose Platform for Heterogeneous Computing

In the big data era, processing large amounts of data imposes several challenges, mainly in terms of performance. Complex operations in data science, such as deep learning, large-scale simulations, and visualization applications, can consume a significant amount of computing time. Heterogeneous computing is an attractive alternative for algorithm acceleration, using not one but several different kinds of computing devices (CPUs, GPUs, or FPGAs) simultaneously. Accelerating an algorithm for a specific device under a specific framework, i.e., CUDA/GPU, provides a solution with the highest possible performance at the cost of a loss in generality and requires an experienced programmer. On the contrary, heterogeneous computing allows one to hide the details pertaining to the simultaneous use of different technologies in order to accelerate computation. However, effective heterogeneous computing implementation still requires mastering the underlying design flow. Aiming to fill this gap, in this paper we present a heterogeneous computing platform (HCP). Regarding its main features, this platform allows non-experts in heterogeneous computing to deploy, run, and evaluate high-computational-demand algorithms following a semi-automatic design flow. Given the implementation of an algorithm in C with minimal format requirements, the platform automatically generates the parallel code using a code analyzer, which is adapted to target a set of available computing devices. Thus, while an experienced heterogeneous computing programmer is not required, the process can run over the available computing devices on the platform as it is not an ad hoc solution for a specific computing device. The proposed HCP relies on the OpenCL specification for interoperability and generality. The platform was validated and evaluated in terms of generality and efficiency through a set of experiments using the algorithms of the Polybench/C suite (version 3.2) as the input. Different configurations for the platform were used, considering CPUs only, GPUs only, and a combination of both. The results revealed that the proposed HCP was able to achieve accelerations of up to 270× for specific classes of algorithms, i.e., parallel-friendly algorithms, while its use required almost no expertise in either OpenCL or heterogeneous computing from the programmer/end-user.

Prediction and Analysis of Heart Diseases Using Heterogeneous Computing Platform

The work in this paper helps study cardiac rhythms and the electrical activity of the heart for two of the most critical cardiac arrhythmias. Various consumer devices exist, but implementation of an appropriate device at a certain position on the body at a certain pressure point containing an enormous number of blood vessels and developing filtering techniques for the most accurate signal extraction from the heart is a challenging task. In this paper, we provide evidence of prediction and analysis of Atrial Fibrillation (AF) and Ventricular Fibrillation (VF). Long-term monitoring of diseases such as AF and VF occurrences is very important, as these will lead to occurrence of ischemic stroke, cardiac arrest and complete heart failure. The AF and VF signal classification accuracy are much higher when processed on a Graphics Processor Unit (GPU) than Central Processing Unit (CPU) or traditional Holter machines. The classifier COMMA-Z filter is applied to the highly-sensitive industry certified Bio PPG sensor placed at the earlobe and computed on GPU.

A Novel Discrete Grey Wolf Optimizer for Scientific Workflow Scheduling in Heterogeneous Cloud Computing Platforms

There are several scientific workflow applications which need vast amount of processing so the cloud offerings give the sense of economic. Workflow scheduling has drastic impact on gaining desired quality of service (QoS). The main objective of workflow scheduling is to minimize the makespan. The workflow scheduling is formulated to a discrete optimization problem which is NP-Hard. This paper presents a novel discrete grey wolf optimizer (D-GWO) for scientific workflow scheduling problems in heterogeneous cloud computing platforms in the aim of minimizing makespan. Although the original GWO had great achievements in continuous optimization problems, it seems clear gap in utilizing GWO for combinatorial discrete optimization problems. It revolves around the fact that the continuous changes in search space during the course of discrete optimization lead inefficient or meaningless solutions. To this end, the proposed algorithm is customized in such a way to optimize discrete workflow scheduling problem by leveraging some new binary operators and Walking Around approaches to balance between exploration and exploitation in discrete search space. Scientific unstructured workflows were investigated in different circumstances to prove effectiveness of proposed novel meta-heuristic algorithm. The simulation results witnessed the superiority of proposed D-GWO against other state-of-the-arts in terms of scheduling metrics.

PCIe-based FPGA-GPU heterogeneous computation for real-time multi-emitter fitting in super-resolution localization microscopy.

Real-time multi-emitter fitting is a key technology for advancing super-resolution localization microscopy (SRLM), especially when it is necessary to achieve dynamic imaging quality control and/or optimization of experimental conditions. However, with the increase of activation densities, the requirements in the computing resources would increase rapidly due to the complexity of the fitting algorithms, making it difficult to realize real-time multi-emitter fitting for emitter density more than 0.6 mol/µm2 in large field of view (FOV), even after acceleration with the popular Graphics Processing Unit (GPU) computation. Here we adopt the task parallelism strategy in computer science to construct a Peripheral Component Interconnect Express (PCIe) based all-in-one heterogeneous computing platform (AIO-HCP), where the data between two major parallel computing hardware, Field Programmable Gate Array (FPGA) and GPU, are interacted directly and executed simultaneously. Using simulated and experimental data, we verify that AIO-HCP could achieve a data throughput of up to ∼ 1.561 GB/s between FPGA and GPU. With this new platform, we develop a multi-emitter fitting method, called AIO-STORM, under big data stream parallel scheduling. We show that AIO-STORM is capable of providing real-time image processing on raw images with 100 µm × 100 µm FOV, 10 ms exposure time and 5.5 mol/µm2 structure density, without scarifying image quality. This study overcomes the data throughput limitation of heterogeneous devices, demonstrates the power of the PCIe-based heterogeneous computation platform, and offers opportunities for multi-scale stitching of super-resolution images.

An Efficient Task Scheduling Based on Seagull Optimization Algorithm for Heterogeneous Cloud Computing Platforms

Cloud computing provides computing resources like software and hardware as a service by the network for several users. Task scheduling is one of the main problems to attain cost-effective execution. The main purpose of task scheduling is to allocate tasks to resources so that it can optimize one or more criteria. Since the problem of task scheduling is one of the Nondeterministic Polynomial-time (NP)-hard problems, meta-heuristic algorithms have been widely employed for solving task scheduling problems. One of the new bio-inspired meta-algorithms is Seagull Optimization Algorithm (SOA). In this paper, we proposed an energy-aware and cost-efficient SOA-based Task Scheduling (SOATS) algorithm. The aims of proposed algorithm to make a trade-off between five objectives (i.e., energy consumption, makespan, cost, waiting time, and load balancing) using a fewer number of iterations. The experiment results by comparing with several meta-heuristic algorithms (i.e., Genetic Algorithm (GA), Particle Swarm Optimization (PSO), Ant Colony Optimization (ACO), and Whale Optimization Algorithm (WOA)) prove that the proposed technique performs better in solving task scheduling problem. Moreover, we compared the proposed algorithm with well-known scheduling methods: Cost-based Job Scheduling (CJS), Moth Search Algorithm based Differential Evolution (MSDE), and Fuzzy-GA (FUGE). In the heavily loaded environment, the SOATS algorithm improved energy consumption and cost saving by 10 and 25%, respectively.

A novel hybrid heuristic-based list scheduling algorithm in heterogeneous cloud computing environment for makespan optimization

An efficient workflow scheduling can potentially exploit heterogeneity of resources in heterogeneous cloud computing (HCC) platform commensurate with variable requirement of dependent tasks in a given workflow. Minimizing the total scheduling length, makespan, is essential for application performance in heterogeneous computing systems especially in cloud computing environment. The problem of scheduling a set of different dependent tasks onto a set of heterogeneous computational resources is a well-known NP-Hard problem. Therefore, no polynomial scheduling algorithm for computing the optimal solution exists. For approximating a solution to this problem many algorithms have been proposed, but majority of them have low efficiency. In this paper, a novel hybrid heuristic-based list scheduling (HH-LiSch) algorithm is presented for solving the dependent task scheduling in HCC systems in a bounded number of the fully connected virtual machines (VMs). The novelty of the current paper is to present the new task priority strategy, find appropriate VM's slot time, and utilize task duplication technique. Two novel task priority strategies are applied to prioritize tasks in an efficient ordered list. Then, during the scheduling process an insertion-based procedure is called to find an appropriate potential slot time for performing task duplication technique. If it works, the task duplication is added to rudimentary scheduling scheme. In this way, the final scheduling is gradually generated. To validate the work, the experiments are based on six real-world scientific workflows and a random task graph (RTG); then, the performance is evaluated in terms of makespan, Schedule Length Ratio (SLR), speedup and efficiency. The simulation results prove a significant improvement against other counterparts in literature.

De-Anonymizing Users Across Heterogeneous Social Computing Platforms

Many people use multiple online and social computing platforms, and choose to share varying amounts of personal information about themselves depending on the context and type of site. For example, people may be willing to share personally-identifiable details (including their real name and date of birth) on a site like Facebook, but may withhold their identity on a dating site that may be widely viewed by strangers. We study the extent to which subtle correlations in a user's activity patterns across different sites may be used to infer that two accounts correspond to the same person. We study a variety of features, including similarity of temporal access patterns, textual content, geo-tags, and social connections, finding that even very weak signals yield surprisingly accurate de-anonymization results.

Greening Duplication-Based Dependent-Tasks Scheduling on Heterogeneous Large-Scale Computing Platforms

Low-cost and high-performance execution of nowadays computing-intensive applications will not be possible without large-scale heterogeneous computing platforms. The huge computing power of such platforms raises the problem of the electrical energy consumed by such platforms. One of the key issues to achieve high-performance in such platforms is task-scheduling. Among the heuristics-based compile-time dependent-task scheduling heuristics, duplication-based list scheduling heuristics give the earliest finish time of the application tasks. Unfortunately, due to the additional computing cost required by duplication, these heuristics consume more computing power that leads to more electrical energy consumption. Energy-efficiency and green-computing turn the attention to the need for new generations of energy-aware task-scheduling algorithms. This paper presents a duplication reduction mechanism that can be applied to any schedule produced by a duplication-based scheduling algorithm. The aims of the proposed mechanism are to keep the same finish time of the scheduled application tasks, to keep the lower-bound time-complexity of the heuristics-based dependent task scheduling algorithms, and to significantly reduce the energy consumed by task-duplication. The mechanism is called Green. Green was applied to four of the most-recent and well-known duplication-based list-scheduling algorithms. The experimental results based on computer simulation utilizing C# language for large sets of both randomly generated and three real-world applications graphs show that Green can significantly reduce the energy consumed by each algorithm.

Rapid Topology Generation and Core Mapping of Optical Network-on-Chip for Heterogeneous Computing Platform

The explosive growth of deep learning (DL)–based artificial intelligence (AI) applications necessitates extraordinary computing capabilities that cannot be achieved using traditional CPU standalone computing. Therefore, the heavy mission-critical DL kernel computing currently relies on a heterogeneous computing (HGC) platform integrated with CPUs, GPUs, and accelerators, as well as substantial data storage elements. However, the metallic electrical interconnection in the existing manycore platform would not be sustainable for handling the massively increasing bandwidth demand of big data driven AI applications. Incorporating an optical network-on-chip (ONoC) for providing ultrahigh bandwidth, we propose a rapid topology generation and core mapping of ONoC (REGO) for energy-efficient HGC multicore architecture. The genetic algorithm (GA)-based REGO utilizes the structural characteristics of the optical router to the fitness function and thus compromises the trade-off between the required throughput, optical signal-to-noise ratio (OSNR), and total energy consumption. Furthermore, the crossover step accelerates the convergence speed by suppressing randomness in the GA, thus significantly reducing excessive running time owing to the NP-hard property. The generated ONoC through REGO demonstrates, on an average, an increase of 63.29 % and 22.80 % in throughput and a decrease of 50.24 % and 9.56 % in energy per bit, in the VGG-16 and VGG-19 compared with the conventional mesh- and torus-topology-based ONoCs, respectively.

HOSVD prototype based on modular SW libraries running on a high-performance CPU+GPU platform

Efficient prototyping is an invaluable resource for modern enterprises and research centers. An efficient prototyping tool exhibits high throughput while maintaining flexibility, and reduces design and validation efforts, resulting in low time-to-market and high competitiveness. This paper presents a modular implementation of high-performance software (SW) libraries running on a Heterogeneous Computing Platform (HCP) based on CPU+GPU. The proposed SW libraries enable a fast and easy comparison of a prototype under different implementation criteria and maintain a high throughput and reusability due to their modular definition. These features accelerate the prototyping task by removing the overhead of designing and validating ad-hoc implementations. The novelty and benefits of this proposal are presented by prototyping and analysis of the multilinear SVD or Higher-Order SVD (HOSVD), an important, widely-used, and computationally demanding tensor decomposition. The mean square error (MSE), processing time, and speedup of this case study show its high performance, while modularity maintains flexibility. The HOSVD prototype reaches a maximum speedup of 17× that of one of the most important implementations in the state of the art.

überSpark

Today's computing ecosystem, comprising commodity heterogeneous interconnected computing (CHIC) platforms, is increasingly being employed for critical applications, consequently demanding fairly strong end-to-end assurances. However, the generality and system complexity of today's CHIC stack seem to outpace existing tools and methodologies toward provable end-to-end guarantees. This paper describes our on-going research, and presents überSpark, a system architecture that argues for structuring the CHIC stack around Universal Object Abstractions (üobjects), a fundamental system abstraction and building block towards practical and provable end-to-end guarantees.

HCP: Heterogeneous Computing Platform for Federated Learning Based Collaborative Content Caching Towards 6G Networks

A heterogeneous computing architecture is essential to facilitate intelligent network traffic control for a joint computation, communication, and collaborative caching optimization in 6G networks to provide stringent Quality of Experience (QoE) guarantees. In this paper, we consider a 6G integrated aerial-terrestrial network model where Unmanned Aerial Vehicles (UAVs) and terrestrial Remote Radio Heads (RRHs) jointly serve as heterogeneous Base Stations (hgNBs) of a Cloud Radio Access Network (HCRAN) serving different mobile user (UE) types. We propose a distributed heterogeneous computing platform (HCP) across the UAVs and terrestrial Base Stations (BSs) by utilizing their caching and cooperative communication capabilities. In order to preserve the privacy of the content of the UEs, we propose a 2-stage federated learning algorithm among the UEs, UAVs/BSs, and HCP to collaboratively predict the content caching placement by jointly considering traffic distribution, UE mobility and localized content popularity. An asynchronous weight updating method is adopted to avoid redundant learning transfer in the federated learning. Once the global model is learnt by the HCP, it transfers the learned model to the UEs to facilitate the much desired edge intelligence in the considered 6G tiny cell. The effectiveness of the proposal is evaluated by extensive numerical analysis.

Accelerate Scientific Deep Learning Models on Heterogeneous Computing Platform with FPGA

AI and deep learning are experiencing explosive growth in almost every domain involving analysis of big data. Deep learning using Deep Neural Networks (DNNs) has shown great promise for such scientific data analysis applications. However, traditional CPU-based sequential computing without special instructions can no longer meet the requirements of mission-critical applications, which are compute-intensive and require low latency and high throughput. Heterogeneous computing (HGC), with CPUs integrated with GPUs, FPGAs, and other science-targeted accelerators, offers unique capabilities to accelerate DNNs. Collaborating researchers at SHREC1at the University of Florida, CERN Openlab, NERSC2at Lawrence Berkeley National Lab, Dell EMC, and Intel are studying the application of heterogeneous computing (HGC) to scientific problems using DNN models. This paper focuses on the use of FPGAs to accelerate the inferencing stage of the HGC workflow. We present case studies and results in inferencing state-of-the-art DNN models for scientific data analysis, using Intel distribution of OpenVINO, running on an Intel Programmable Acceleration Card (PAC) equipped with an Arria 10 GX FPGA. Using the Intel Deep Learning Acceleration (DLA) development suite to optimize existing FPGA primitives and develop new ones, we were able accelerate the scientific DNN models under study with a speedup from 2.46x to 9.59x for a single Arria 10 FPGA against a single core (single thread) of a server-class Skylake CPU.

Accurate Energy Modelling of Hybrid Parallel Applications on Modern Heterogeneous Computing Platforms Using System-Level Measurements

Modern high-performance computing platforms, cloud computing systems, and data centers are highly heterogeneous containing nodes where a multicore CPU is tightly integrated with accelerators. An important challenge for energy optimization of hybrid parallel applications on such platforms is how to accurately estimate the energy consumption of application components running on different compute devices of the platform. In this work, we propose a method for accurate estimation of the application component-level energy consumption employing system-level power measurements with power meters. We experimentally validate the method on a cluster of two hybrid heterogeneous computing nodes using three parallel applications - matrix-matrix multiplication, 2D fast Fourier transform and gene sequencing. The experiments demonstrate a high estimation accuracy of the proposed method, with the average estimation error ranging between 2% and 5%. The average error demonstrated by the state-of-the-art estimation methods for the same experimental setup ranges from 15% to 75%, while the maximum reaches 178%. We also show that the use of the state-of-the-art estimation methods instead of the proposed one in the energy optimization loop leads to significant energy losses (up to 45% in our case).

Value Iteration Architecture Based Deep Learning for Intelligent Routing Exploiting Heterogeneous Computing Platforms

Recently, the rapid advancement of high computing platforms has accelerated the development and applications of artificial intelligence techniques. Deep learning, which has been regarded as the next paradigm to revolutionize users’ experiences, has attracted networking researchers’ interests to relieve the burden due to the exponentially growing traffic and increasing complexities. Various intelligent packet transmission strategies have been proposed to tackle different network problems. However, most of the existing research just focuses on the network related improvements and neglects the analysis about the computation consumptions. In this paper, we propose a Value Iteration Architecture based Deep Learning (VIADL) method to conduct routing design to address the limitations of existing deep learning based routing algorithms in dynamic networks. Besides the network performance analysis, we also study the complexity of our proposal as well as the resource consumptions in different deployment manners. Moreover, we adopt the Heterogeneous Computing Platform (HCP) to conduct the training and running of the proposed VIADL since the theoretical analysis demonstrates the significant reduction of the time complexity with the multiple GPUs in HCPs. Furthermore, simulation results demonstrate that compared with the existing deep learning based method, our proposal can guarantee more stable network performance when network topology changes.

Dynamic Task Scheduling Algorithm with Deadline Constraint in Heterogeneous Volunteer Computing Platforms

Volunteer computing (VC) is a distributed computing paradigm, which provides unlimited computing resources in the form of donated idle resources for many large-scale scientific computing applications. Task scheduling is one of the most challenging problems in VC. Although, dynamic scheduling problem with deadline constraint has been extensively studied in prior studies in the heterogeneous system, such as cloud computing and clusters, these algorithms can’t be fully applied to VC. This is because volunteer nodes can get offline whenever they want without taking any responsibility, which is different from other distributed computing. For this situation, this paper proposes a dynamic task scheduling algorithm for heterogeneous VC with deadline constraint, called deadline preference dispatch scheduling (DPDS). The DPDS algorithm selects tasks with the nearest deadline each time and assigns them to volunteer nodes (VN), which solves the dynamic task scheduling problem with deadline constraint. To make full use of resources and maximize the number of completed tasks before the deadline constraint, on the basis of the DPDS algorithm, improved dispatch constraint scheduling (IDCS) is further proposed. To verify our algorithms, we conducted experiments, and the results show that the proposed algorithms can effectively solve the dynamic task assignment problem with deadline constraint in VC.

Development of Digital Forensic Framework for Joint Heterogeneous Cloud Computing Platforms

The cloud computing is nowadays an embarrassing computing technology by many organisations, academic institutions and business centres. Cloud Service Providers (CSP)s are limited to some resources, lacking some resources requested by its customers, this gives rise to the needs for interconnecting multiple clouds to interoperate and share resources. The interconnected clouds can be in different features and schemes, and the system can be prone to insecurity or intrusion. In this paper, we developed a Digital Forensics framework that can detect an intrusion within heterogeneous joint clouds. We also developed architecture and algorithm that can handle the joint clouds heterogeneity and complexity during inter-clouds resources management.

ALMARVI Execution Platform: Heterogeneous Video Processing SoC Platform on FPGA

The proliferation of processing hardware alternatives allows developers to use various customized computing platforms to run their applications in an optimal way. However, porting application code on custom hardware requires a lot of development and porting effort. This paper describes a heterogeneous computational platform (the ALMARVI execution platform) comprising of multiple communicating processors that allow easy programmability through an interface to OpenCL. The ALMARVI platform uses processing elements based on both VLIW and Transport Triggered Architectures (ρ-VEX and TCE cores, respectively). It can be implemented on Zynq devices such as the ZedBoard, and supports OpenCL by means of the pocl (Portable OpenCL) project and our ALMAIF interface specification. This allows developers to execute kernels transparently on either processing elements, thereby allowing to optimize execution time with minimal design and development effort.