Hetero-dielectric Gate Research Articles

Ambipolar current suppression in drain elevated TFET using a novel extended drain structure with a moderate doping profile

In this paper, a simple and compact silicon-based Elevated and Extended Drain with Hetero-Dielectric Gate Oxide TFET (EED HDGO TFET) is proposed to suppress the ambipolar current in Elevated Drain TFET (ED TFET). The proposed device structure uses a moderately doped drain with a doping concentration of ∼1018 cm−3 and a high drain length of ∼50–100 nm. The combination of the moderate drain doping profile and the extended drain length reduced the impact of the electrostatic potential from the positive voltage of the drain electrode on the channel–drain junction. This structural technique widens the tunneling width at the channel–drain region causing the tunneling current to decrease significantly. The tunneling width is further increased by structurally isolating the channel–drain junction region from the gate electrode. Thus, distancing the channel–drain junction from both the gate electric field and the static drain potential of the drain electrode causes full suppression of the ambipolar (Iamb) current. The proposed structure yields Iamb and Ioff as low as ∼10−18 A/μm and ∼10−17 A/μm respectively, while maintaining the Ion as ∼0.3 mA. The device is optimized for low power and high-speed digital circuits through intensive parametric analysis on gate–drain Cgd and the gate–source Cgs capacitances for various device parameters.

Performance evaluation of split high–K material based stacked hetero-dielectrics tunnel FET

This research investigates the performance evaluation of a double gate TFET (DGTFET) by employing a hetero-dielectric gate structure featuring distinct high-K dielectrics with different work functions in a dual-material gate configuration. The gate dielectric stack is comprised of split high–K materials placed on the SiO2 dielectric. An outline of the analytical model for the validation of the novel device is developed and 2D simulations-based analysis and investigation are carried out. The impact of different high-K dielectric materials layered on top of silicon dioxide (SiO2) is examined; its effect on transfer characteristics, subthreshold swing (SS), minimum tunneling width, ratio of ON to OFF currents ION/IOFF, and energy band bending are investigated. The work functions optimization for the auxiliary and tunnel gates are made in this work to minimize OFF current, to reduce ambipolar phenomena and to enhance tunnel rate. The effects of gate potentials, source/ drain doping concentrations on the results are further studied. The threshold voltage of DGTFET is also modelled and computed for the proposed structures. The present findings revealed that the low OFF current (10−17 A μm−1) is provided by the proposed device structure, improved ratio of ION/IOFF (1011), and lowered subthreshold swing required for future era.

Novel SiGe/Si Heterojunction Double-Gate Tunneling FETs with a Heterogate Dielectric for High Performance.

In this paper, a new SiGe/Si heterojunction double-gate heterogate dielectric tunneling field-effect transistor with an auxiliary tunneling barrier layer (HJ-HD-P-DGTFET) is proposed and investigated using TCAD tools. SiGe material has a smaller band gap than Si, so a heterojunction with SiGe(source)/Si(channel) can result in a smaller tunneling distance, which is very helpful in boosting the tunneling rate. The gate dielectric near the drain region consists of low-k SiO2 to weaken the gate control of the channel-drain tunneling junction and reduce the ambipolar current (Iamb). In contrast, the gate dielectric near the source region consists of high-k HfO2 to increase the on-state current (Ion) through the method of gate control. To further increase Ion, an n+-doped auxiliary tunneling barrier layer (pocket)is used to reduce the tunneling distance. Therefore, the proposed HJ-HD-P-DGTFET can obtain a higher on-state current and suppressed ambipolar effect. The simulation results show that a large Ion of 7.79 × 10-5 A/μm, a suppressed Ioff of 8.16 × 10-18 A/μm, minimum subthreshold swing (SSmin) of 19 mV/dec, a cutoff frequency (fT) of 19.95 GHz, and gain bandwidth product (GBW) of 2.07 GHz can be achieved. The data indicate that HJ-HD-P-DGTFET is a promising device for low-power-consumption radio frequency applications.

Qualitative Analysis of DG-TFET Structures with Gate Material Engineering

The paper largely focuses on enhancing device parameters of a Double Gate Tunnel Field Effect Transistor structure such as ON current, OFF Current,transconductance and ratio of ON current to OFF current (ION / IOFF) using hetero dielectric gate material. The paper presents three state of art of dual gate TFET i.e., Conventional Double Gate TFET (CDGTFET), horizontally placed Dual Material Double Gate TFET (HDMDGTFET), vertically placed Dual Material Double Gate TFET (VDMDGTFET). The dual material dielectric combinations used in the structures are (SiO2-TiO2), (HfO2-TiO2) and (SiO2-SiC). The Structures are being modeled using Silvaco Atlas tool. Simulations of these structures are carried out and various electrical parameters have been obtained. The results obtained from simulation of these structures are being presented and discussed in this paper. Comparison of the three structures is carried out and resulted in the reduction of ON Current and OFF Current is observed.

Performance Analysis of InAs-GaAs Gate-all-around Tunnel Field Effect Transistors (GAA-TFET) for Analog/ RF applications

The purpose of this study to explore the performance of InAs-GaAs Gate-all-around (GAA) tunnelling field effect transistors (TFETs) in analogue and RF applications. The TCAD tool was used to assess the device’s overall performance. In order to achieve the InAs-GaAs channel design, the suggested TFET features a gate oxide made of SiO2 near the drain and HfO2 near the source region. As a result of the hetero dielectric gate oxide being used, the tunnelling width at junction between drain and channel (JDC) and junction between source and channel (JSC) is reduced, and the ON-current at the drain-channel junction is increased (ION). Device simulations have revealed that the SiO2-HfO2 gate dielectric has a low off-current (IOFF) of 2.27 x 10−17 A/m, a high enhanced ION of 7.39 x 10−6 A/m. At the time of operation, the sub-threshold swing (SS) was 16.8 mV/dec. Because of its low power consumption, the device could potentially be a better choice for power management circuits used in energy harvesting applications, according to the findings.

Investigation and optimization of electro-thermal performance of Double Gate-All-Around MOSFET

The Double Gate-All-Around (DGAA) MOSFET and GAA NWFET are compared and analyzed from both electrical and thermal perspectives under four different conditions by adjusting the channel radius of the NWFET (RGAA). DGAA MOSFET is found to easier form volume inversion than GAA NWFET, and has the advantage of better gate controllability and drivability and the primary concern of worse heat dissipation efficiency. Hetero-Gate-Dielectric (HGD) structure, channel design and spacer engineering are adopted to weaken the serious SHEs in DGAA MOSFET while maintaining a good SCEs immunity. Results show that the DGAA MOSFET with the single-k Al2O3 spacer can generate a better trade-off between electrical and thermal performance than other spacer combinations. In addition, the improvement in thermal performance of DGAA MOSFET by the HGD structure is relatively limited. Compared with GAA NWFET without stacking, the optimized DGAA MOSFET with single-k Al2O3 spacer, appropriate channel thickness (Tch = 5 nm) to form volume inversion and underlap channel (Lun = 4 nm) has better electrical characteristics whose drivability improves at least twice with similar Rth.

Diminish Short Channel Effects on Cylindrical GAA Hetero-gate Dielectric TFET using High-Density Delta

The examined work elucidates a novel concept on Gate All Around (GAA) hetero dielectric gate-cylindrical tunnel field-effect transistor (TFET) to reduce SCEs. In this paper, a hetero dielectric gate (HeG) integrated with Silicon-Germanium (Si-Ge) substrate material is proposed along with a novel placement of a high-density delta (HDD) layer across the source–channel junction to achieve high ION of 1.12 × 10−4 A/µm and robust IOFF of 9.7 × 10−17 A/µm at Vgs = 1.2 V with steepest subthreshold swing (SS) of 55 mV/decade. Designing and computation of the proffered structure have been done with the computer-aided design (TCAD) 3D device computation software. The systematic investigation in terms of AC and DC parameters, such as ON-current, OFF-current, Miller Capacitances (Gate-Drain Capacitance (Cgd)) and Gate-Source Capacitance (Cgs), are examined. Hetero-gate dielectric Cyl-TFET with high-density delta (HDD) is superior to other conventional structures. The result outcomes included a trap analysis while incorporating the hot charge carriers inside the oxide for improved device reliability. Furthermore, a low Cgd of 58fF and high Cgs of 6.6fF at Vds = 0.3 V have been achieved.

Study of Electrical Performance of Hetero-Dielectric Gate Tunnel Field Effect Transistor (HDG TFET): A Novel Structure for Future Nanotechnology

Although, dynamic power in portable mobile devices can be reduced by reducing power supply VDD on the cost of increased leakage current. Therefore, maintaining low leakage current in the device is serious issue for minimizing overall power consumption of the circuit and improving the battery life. The conventional Metal Oxide Field Effect Transistor (MOSFET) requires at least 60 mV of gate voltage for better current drive at room temperature which is difficult to achieve due to thermal limit. This limitation of gate voltage requirement degrades the performance of the device at lower VDD. Tunnel Field Effect Transistor (TFET) is a potential candidate to replace CMOS in deep-submicron region due to its lower subthreshold slope SS (< 60 mV/decade) at room temperature. Steep switching in TFET can extend the supply voltage scaling with improved energy efficiency for both digital and analog applications. Despite those advantages, TFETs are suffering from lower ON current and larger ambipolar current. To overcome these shortcomings, a new structure, known as Hetero-dielectric gate TFET (HDG TFET), has been proposed in the literature. Since, in the absence of the compact analytical model, it is difficult to understand the electrical behaviour of the HDG TFET device, therefore, the present paper presents an analytical model of transconductance parameter of HDG TFET device. The electrical performance analysis of HDG TFET device reflects that on current can be increased considerably by choosing gate material of higher work function near the source region which also suppresses the ambipolar current. It is also observed that a thinner silicon film and larger drain bias result in larger transconductance value.

Source pocket-engineered hetero-gate dielectric SOI Tunnel FET with improved performance

In this paper, we have studied and proposed a planar Tunnel FET device with source side SiGe pocket and hetero-gate dielectric structure that works by utilizing quantum mechanical Band-to-Band tunnelling (BTBT) mechanism. Simulation results obtained using a calibrated SILVACO TCAD device simulator show that the device exhibits good ambipolar performance because of the hetero-gate dielectric and the use of source pocket leads to steep point subthreshold swing of 4.90 mV/dec., an average subthreshold swing of 25.31 mV/dec. and a threshold voltage of 0.23 V. For including the hetero-gate dielectric, the variation in drain current values with high-κ dielectric length is analysed. The change in transfer characteristics with pocket parameters including pocket length and pocket doping is also reported. A 4 nm Si0.7Ge0.3 n+ pocket with doping concentration of 5 × 1019 cm−3 is found to show the maximum ON-OFF current ratio of 5.23 × 1011. This paper also performs a comparative study between different TFET structures and the analysis clearly highlights the potential of proposed Source Pocket-Engineered Hetero Gate Dielectric (SPE-HGD) TFET device for low-power and energy-efficient applications.

Linearly Work-Function Modulated Gate Metal For Hetero Gate Dielectric TFET with Si0.5Ge0.5-Pocket at Source/Channel Junction

Linearly Work-Function Modulated Gate Metal For Hetero Gate Dielectric TFET with Si0.5Ge0.5-Pocket at Source/Channel Junction

An analytical 2-D model of triple metal double gate graded channel junctionless MOSFET with hetero-dielectric gate oxide stack

In this paper, a two-dimensional analytical model of a laterally graded-channel triple-metal double-gate Junctionless Field Effect Transistor with hetero dielectric gate oxide stack consisting of SiO2 and HfO2 is derived. The model illustrates higher drive current and better performance against hazardous SCEs and HCEs in below 30 nm regime. Parabolic approximation method is used here to construct channel potentials and electric fields by solving 2-D Poisson's equation with applicable boundary conditions. The basic central and surface potentials as well as central and surface electric fields are being illustrated, Threshold voltage, DIBL, sub-threshold swing (SS) and a compact current model have also been deduced. These parameters clearly show the benefits of proposed graded-channel triple-metal double-gate structure with hetero-dielectric gate oxide stack. The device has reliability in low power applications because of its better Ion and Ioff control. Finally, the analytical model is validated with self-consistent numerical calculations to illustrate better performance of among available junctionless devices.

Extended-source broken gate tunnel FET for improving direct current and analog/radio-frequency performance* *Project supported by the University Natural Science Research Key Project of Anhui Province (Grant No. KJ2020A0075) and Excellent Talents Supported Project of Colleges and Universities (Grant No. gxyq2018048).

The various advantages of extended-source (ES), broken gate (BG), and hetero-gate-dielectric (HGD) technology are blended together for the proposed tunnel field-effect transistor (ESBG TFET) in order to enhance the direct-current and analog/radio-frequency performance. The source of the ESBG TFET is extended into channel for the purpose of increasing the point and line tunneling in the device at the tunneling junction, and then, the on-state current for the ESBG TFET increases. The influence of the source region length on the direct-current and radio-frequency performance parameters of the ESBG TFET is analyzed in detail. The results show that the proposed TFET exhibits a high on-state current to off-state current ratio of 1013, large transconductance of 1200 μS/μm, high cut-off frequency of 72.8 GHz, and high gain bandwidth product of 14.3 GHz. Apart from these parameters, the ESBG TFET also demonstrates high linearity distortion parameters in terms of the second- and third-order voltage intercept points, the third-order input interception point, and the third-order intermodulation distortion. Therefore, the ESBG TFET greatly promotes the application potential of conventional TFETs.

Design and investigation of the double gate TFET with heterogeneous gate dielectric using different gate materials

A 2 dimensional model of double gate hetero dielectric Tunnel Field Effect Transistor (HD-DG TFET) with hetero dielectric gate stack is carved with Silicon dioxide (SiO2) and Hafnium dioxide (HfO2) as dielectric materials. The electrical characteristics are demonstrated for the device by using 2D numerical device simulator Silvaco TCAD. The channel length, doping concentration of drain and source, thickness of device and effective oxide layer thickness of the device is kept constant throughout the work. It is showed that the proposed structure has better performance than Double Gate TFET. Also gate materials used are silver, gold, platinum and Npolysilicon. By using these materials Drain current and electric field of the device has been plotted. Also the proposed model shows a lower leakage current, better ION/IOFF ratio sub-threshold swing and lower DIBL. It has also been remarked that use of metal gate with appropriate work function along with high-k and hetero dielectric improves the carrier transport in the channel. This model aims to lower the short channel effects and give emphasis to improvement of switching ratio.

Improvement in Self-Heating Characteristic by Incorporating Hetero-Gate-Dielectric in Gate-All-Around MOSFETs

For improving self-heating effects (SHEs) in gate-all-around metal-oxide-semiconductor field-effect transistors (GAA MOSFETs), hetero-gate-dielectric (HGD) is utilized. The HGD consists of hafnium dioxide (HfO2) and silicon dioxide (SiO2), which has high thermal conductivity, hence SHEs are improved. In order to validate the HGD, technology computer-aided design (TCAD) simulation is performed through Synopsys Sentaurus three-dimensional (3D) tool. As a result, when the HGD is adopted in GAA MOSFETs, SHEs can be significantly improved from 498 K to 415 K. In addition, suppression of gate current, more than 2 orders, is also achieved because of bigger bandgap of SiO2 in HGD. Consequently, this structure takes advantage of higher thermal conductivity and bigger bandgap of SiO2, and higher permittivity of HfO2 for improving SHEs and gate leakage current.

Performance Improvement of Heterojunction Double Gate TFET with Gaussian Doping

A new Ge/SiGe heterojunction double-gate tunnel field effect transistor (DGT) model with hetero dielectric gate and Gaussian doping drain region is investigated for the first time. The introduction of heterojunction with hetero dielectric will reduce band-to-band tunneling (BTBT) leakage current while maintaining high mobility to enhance drain current and transconductance characteristics of the device significantly. Along with that, the combined effect of analytical drain doping profile (Gaussian) and hetero dielectric suppresses the ambipolar behavior. Different DC characteristics of the device like energy band analysis, electric field, drain current and BTBT generation rate are analyzed for the proposed structure. RF figure of merit for the HD-HJDGT-GD is express by analyzing its transconductance (gm), cut off frequency (fT), maximum oscillation frequency (fmax), gain bandwidth product (GBP) and transconductance frequency product (TFP). The outcome of the model under study is compared with conventional DGT. It is apparent from the analysis that the recommended model has better DC and RF performance, which makes this device worth studying to be used in high-frequency applications. TCAD simulation is performed by using Sentaurus 2D device simulator from Synopsys.

Impact of Hetero-Dielectric Ferroelectric Gate Stack on Analog/RF Performance of Tunnel FET

We have investigated the characteristics of a hetero-dielectric ferroelectric tunnel (HD-FeTFET). Extensive simulations show that using a hetero-dielectric gate architecture in the lateral direction (non-ferroelectric/ferroelectric/non-ferroelectric) results in more desirable analog/RF characteristics. The proposed structure is compared with conventional tunnel field effect transistors (TFETs) and ferroelectric TFET (FeTFET). Simulation results manifest that HD-FeTFET is superior to other compared structures, and benefits from both ferroelectric and hetero-dielectric structure. Negative capacitance effect in ferroelectric causes a step-up voltage transformer, as a result the subthreshold swing decreases. Owing to two different dielectric constants in the hetero-dielectric structure, the electric field enhances; thereby, the on-state current increases. In this paper, important analog/RF figures of merit, such as cut-off frequency (fT), maximum oscillation frequency (fmax), transconductance frequency product, and intrinsic time delay (τ), are investigated. Also, linearity parameters including VIP2, VIP3, IIP3, and the 1-dB compression point are considered. We achieve average sub-threshold swing of 14 mV for 5 decades for HD-FeTFET, and is improved by ∼ 48% and ∼ 30% for TFET and FeTFET, respectively. Moreover, the ION/IOFF ratio and the on-state current for the proposed structure are 1011 and 5.3 × 10−7 (A/μm), respectively.

A novel gate engineered L-shaped dopingless tunnel field-effect transistor

Recently, dopingless tunnel FET (DL-TFET) has emerged and gathered much attention, for it avoids the physical doping process and provides superior immunity against random dopant fluctuation. Nevertheless, it also suffers from low drive current and severe ambipolar effect. In order to overcome these problems, an L-shaped DL-TFET (LDL-TFET) with the gate engineering technique is proposed in this paper. In this device, the space between the source and the gate electrodes can be further optimized to reduce the tunneling distance, and hence boost the drive current. Also, without much fabrication difficulties, hetero-gate-dielectric (HGD) and tunneling gate (TG) structures can be utilized in the LDL-TFET. Benefiting from the modification of the band energy by HGD and TG, the source-channel tunneling distance is further reduced, while the drain-channel tunneling distance is enlarged. TCAD simulation results show that in comparison with planar DL-TFET (PDL-TFET), LDL-TFET offers better performance in terms of on-current, switch ratio, subthreshold slope, ambipolar current and RF parameters. It indicates that the LDL-TFET is a promising device for low-power RF and digital logic applications.

A nano-FET structure comprised of inherent paralleled TFET and MOSFET with improved performance

Abstract In this paper we unveil of a new structure in which a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is paralleled with a Tunneling Field Effect Transistor (TFET) to increase on-state current. In order to enhance tunneling current injection rate in the device, workfunction engineering in gate and substrate electrodes and doping engineering in channel (source pocket) are utilized. For further on-state current enhancement of device, thermionic injection mechanism is used by incorporating a MOSFET in the structure. In addition, hetero gate dielectric is used to reduce parasitic capacitances. Our analysis show PTM-FET transistor has several excellences in comparison to DW HGD SP TFET in terms of transconductance, Ion/Ioff current ratio, short channel effects like DIBL, Early voltage, maximum transducer power gain, unilateral power gain, gain bandwidth product, unity gain frequency and parasitic capacitances. The mentioned advantages for PTM-FET transistor can be a window of utilizing this device in both low power and high performance integrated circuit applications.

TCAD Simulation of the Doping-Less TFET with Ge/SiGe/Si Hetero-Junction and Hetero-Gate Dielectric for the Enhancement of Device Performance

The device structure of DLTFET is optimized by the Silvaco TCAD software to solve the problems of lower on-state current and larger miller capacitance of traditional doping-less tunneling field effect transistors (DLTFETs), and the performance can be greatly improved. Different from the traditional DLTFETs, the source region and pocket region of the doping-less TFET with the Ge/SiGe/Si hetero-junction and hetero-gate dielectric (H-DLTFET), respectively, use the narrow band-gap semiconductor Ge and SiGe materials, and the channel and drain region both use the silicon material. The H-DLTFET device use the Ge/SiGe hetero-junction engineering to decrease the tunneling barrier width, increase the band-to-band tunneling current, and obtain the higher current switching ratio and ultra-low sub-threshold swing (SS). Besides, the gate dielectric under auxiliary gate uses the low-k dielectric SiO2 material, which can effectively reduce the miller capacitance and improve the capacitance and frequency characteristics. The on-state current, switching ratio, trans-conductance, output current, and output conductance values of H-DLTFET can be increased by two, two, one, one, and one order of magnitude when compared with the DLTFET, respectively. Meanwhile, the point SS and average SS, respectively, decrease from 13 mV/Dec and 31.6 mV/Dec to 5 mV/Dec and 14.3 mV/Dec, and the gate-drain capacitance decrease from 0.99 fF/μm to 0.1 fF/μm. Besides, the cutoff frequency and gain bandwidth product of H-DLTFET are much larger than that of DLTFET, which can be explained by the excellent DC characteristics. The above simulation results show that the H-DLTFET has the better frequency characteristics, so it is more suitable for applications of ultra-low-power integrated circuits.

Device physics and design of hetero-gate dielectric tunnel field-effect transistors with different low/high-k EOT ratios

The hetero-gate dielectric (HGD) structure was recently experimentally demonstrated to enhance the electrical performance of tunnel field-effect transistors (TFETs). This study examined the mechanisms underlying the HGD structure functioning and investigated the design of the structure to enhance the electrical characteristics of TFETs with different ratios of low- and high-k equivalent oxide thicknesses (EOT). The on-current enhancement by the source-side dielectric heterojunction, which directly modulates the on-state tunnel width, was much larger than that by the drain-side dielectric heterojunction, which indirectly affects the on-current by modulating the subthreshold tunnel width. The subthreshold swing is improved by the formation of a conduction band well near the source-channel junction. However, the swing improvement is limited by the hump effect when this local potential well approaches the source. The optimal design of the HGD structure and the maximal enhancement of on-current considerably depend on the EOT ratio of low- and high-k dielectrics. The on-current is most enhanced by the optimized HGD structure at a low/high-k EOT ratio of ten times, that is, approximately 160% of the on-current of the uniform high-k TFET counterpart. Due to the continuous trend of increasing the k-values or scaling EOTs, understanding the dependence of device physics and design on the low/high-k EOT ratio is crucial to optimize the performance of HGD-TFETs.