Heavy Test Research Articles

Analysis and RHBD technique of single event transients in PLLs

Single-event transient susceptibility of phase-locked loops has been investigated. The charge pump is the most sensitive component of the PLL to SET, and it is hard to mitigate this effect at the transistor level. A test circuit was designed on a 65 nm process using a new system-level radiation-hardening-by-design technique. Heavy-ion testing was used to evaluate the radiation hardness. Analyses and discussion of the feasibility of this method are also presented.

SET Response of the Selectively Implanted Deep N-Well —Comparison With Dual Well and Triple Well

The SET response of the selectively implanted deep N-well (SIDNW) was compared with dual well (DW) and triple well (TW) structures by way of heavy-ion experiments on a 65-nm bulk CMOS process. Experimental data produced by P-hit target chains with SIDNW show that a 34.2% decrease in the average pulse width and a 32.1% decrease in the SET cross section is achieved when compared with the DW process, demonstrating the effectiveness of SIDNW in mitigating PMOS SETs by reducing the parasitic bipolar effect during charge collection. Heavy-ion test results on inverter chains, in which the SETs are generated in both PMOS and NMOS, indicate that the SIDNW can mitigate PMOS SETs without bringing adverse effects to the NMOS SETs, when compared with the DW and TW processes.

Evaluation of SEE on a 32-bit Microprocessor by Laser Test and Heavy Ion Test

In this paper the SEE (single event effects) of different parts of device were explored on a 32-bit microprocessor with a five-stage instruction pipeline by laser test and heavy ion test. The cross section curves for different function units were obtained and the comparison of the dates obtained from laser test and heavy ion tests was made. In addition, laser test under different scanning steps were made which indicate that when the scanning step length is in small steps which is considerably equivalent to the laser spot size, there is little change in the number of single event errors caused by each laser pulse. Wherever with the scanning step increasing, the number of single event errors caused by each laser pulse will be reduced. Experiment results suggest that there are differences between laser test and the heavy ion test but have a similar trend. The pulsed laser is an extremely powerful and low-cost technique for SEE testing and will provide invaluable information in characterizing SEE in integrate circuits.

Radiation-Induced Dose and Single Event Effects in Digital CMOS Image Sensors

This paper focuses on radiation-induced dose and single event effects in digital CMOS image sensors using pinned photodiodes. Proton irradiations were used to study cumulative effects. As previously observed, the dark current is the main electrical parameter affected by protons. The mean dark current increase appears proportional to Srour's universal damage factor. Therefore, the degradation is mainly attributed to displacement damage in the pinned photodiode. Heavy ion tests are also reported in this work. This study focuses on single event effects in digital CMOS imagers using numerous electronic functions such as column ADCs, a state machine and registers. Single event transients, upsets and latchups are observed and analyzed. The cross sections of these single events are transposed to specific space imaging missions in order to show that the digital functions can fit the mission requirements despite these perturbations.

New Techniques for SET Sensitivity and Propagation Measurement in Flash-Based FPGAs

Single-event transients (SETs) remain a concern in field-programmable gate arrays (FPGAs) used for space applications. However, accurate measurement of SETs in FPGAs is challenging. This paper describes a calibrated circuit for on-chip measurement of SETs with a temporal precision better than one gate delay. In addition, a technique to measure the final effect of SETs in clocked, complex circuits is presented. Heavy-ion test results for a ProASIC3L FPGA are reported, highlighting a strong dependence between the VersaTile configuration and input signal state with the SET sensitivity and pulse propagation.

Eliminating speed penalties in ECC protected memory designs using “bit bypassing” techniques

In deep sub-micron ICs, growing amounts of on-die memory and scaling effects make embedded memories more vulnerable to reliability problems, such as soft errors induced by radiation. Error Correction Code (ECC) along with scrubbing is an efficient method for protecting memories against these errors. However, the latency of coding circuits brings speed penalties in high performance applications. This paper proposed a “bit bypassing” ECC protected memory by buffering the encoded data and adding an identifying address for the input data. The proposed memory design has been fabricated on a 130 nm CMOS process. According to the measurement, the proposed scheme only gives the minimum delay overhead of 22.6%, compared with other corresponding memories. Furthermore, heavy ion testing demonstrated the single event effects performance of the proposed memory achieves error rate reductions by 42.9 to 63.3 times.

Single-Event Transient Measurements on a DC/DC Pulse Width Modulator Using Heavy Ion, Proton, and Pulsed Laser

This paper discusses multiple methods of Single-Event Transient (SET) measurements on a commercial DC/DC Pulse Width Modulator (PWM). Heavy ion, proton, and pulsed laser are used in the experiments. The correlations between the heavy ion, pulsed laser and proton data are analyzed and presented. A proton cross-section model is used to derive proton cross-section from heavy ion test data. The calculated result is close to the real proton data, which means the heavy ion and proton data fit well. The relationship between pulsed laser and proton are also analyzed through heavy as a medium.

Calculation of single event upset based on Monte Carlo and device simulations

An extraction method for single event upset cross section based on Monte Carlo code and device simulation is proposed, which can be used to calculate single event effects and sensitive regions in memories accurately. Single event upset cross sections of domestic static random access memory (SRAM) and field programmatic gate array (FPGA) devices are calculated, and results agree well with these from heavy ion test. Simulation results reveal the physical mechanism of the relationship between single event upset sensitivity and surface area of off-state NMOSFET and PMOSFET. Sensitive regions of single event upset under different linear energy transfer (LET) values are obtained. The radial ionization profiles of heavy ions with different energy, but the same LET, are also calculated using the Monte Carlo method. The track radius of high-energy ion is significantly larger than that of low-energy ion, while the charge density at the track center of low-energy ion is higher by two or three orders of magnitude. With decreasing technology scaling, the impact of these differences on single event effects will be more pronounced, and the threshold LET and saturated cross-section will not be capable of describing the single event response completely.

A 130 nm radiation hardened flip—flop with an annular gate and a C-element

This paper presents a radiation hardened flip—flop with an annular gate and a Muller C-element. The proposed cell has multiple working modes which can be used in different situations. Each part of the cell can be verified easily and completely by using different modes. This cell has been designed under an SMIC 0.13 μm process and 3-D simulated by using Synopsys TCAD. Heavy-ion testing has been done on the cell and its counterparts. The test results demonstrate that the presented cell reduces the cell's saturation cross section by approximately two orders of magnitude with little penalty on performance.

Correlation of Heavy-Ion and Laser Testing on a DC/DC PWM Controller

Pulsed laser and heavy-ion experiments were carried out on a commercial-off-the-shelf DC/DC pulse width modulation controller to study the equivalent laser Linear Energy Transfer (LET) at wavelengths of 750 nm, 800 nm, 850 nm and 920 nm. The laser experiments showed that the shorter wavelength laser has smaller threshold energy to generate single-event transient pulses. The cross-sections versus heavy-ion LET and laser energy per pulse were obtained and correlated. The heavy-ion and laser cross-sections fit well considering the effects of metal layers on the chip. The results of this research facilitate the future pulsed laser testing by providing explicit coefficients to evaluate the equivalent laser LET, which can be used to replace costly heavy-ion testing.

A Comprehensive Methodology to Rate SETs of Complex Analog and Mixed-Signal Circuits Demonstrated on 16-bit A-to-D Converters

3-D histograms grading the frequency of occurrence of pulsed-laser and heavy-ion induced ASETs against their durations and amplitudes are collected and interpreted on both radiation-hardened and commercial 16-bit ADCs operated at 10 MSps. The histograms encompass traditional cross-section tabulations, modeled after digital upset scoring techniques based on counting events that exceed an arbitrary threshold; yet, they provide a more exhaustive alternative. This data representation technique offers an intuitive visual assessment of the circuit response to radiation, which helped us identify in heavy-ion test results the same trend of ASET width increase, peak decrease versus LET recently published for laser data. The method proposed in this work hinges on a database structure that allows for the definition of custom figures of merit, providing a comprehensive tool for rating radiation hardness in complex analog and mixed-signal circuits.

Electron impact ionization measurements at the Heidelberg heavy ion storage ring TSR

Reliable rate coefficients are needed in order to model the charge state distributions (CSDs) of astrophysical plasmas. We are carrying out electron impact ionization (EII) measurements for astrophysically important ions using the heavy ion Test Storage Ring (TSR) at the Max-Planck Institute for Nuclear Physics in Heidelberg, Germany. These storage ring measurements provide unambiguous data from essentially pure ground-state ion beams.

A 90-nm Radiation Hardened Clock Spine

A RHBD clock distribution network is described that reliably synchronizes the flow of signals through an integrated circuit in the presence of SETs. The clock spine design controls both redundant and non-redundant hardened circuits. The design uses techniques to reduce the jitter due to SETs, as well as error detection at every clock edge, since errors may be in the clock gating enables rather than the clocks themselves. The clock spine has been fabricated and tested on both standard and a low power 90-nm test chips, and proven hard as demonstrated by both heavy ion and proton broad beam testing.

Influence of Beam Conditions and Energy for SEE Testing

The effects of heavy-ion test conditions and beam energy on device response are investigated. These effects are illustrated with two types of test vehicles: SRAMs and power MOSFETs. In addition, GEANT4 simulations have also been performed to better understand the results. Testing to high fluence levels is required to detect rare events. This increases the probability of nuclear interactions. This is typically the case for power MOSFETs, which are tested at high fluences for single event burnout or gate rupture detection, and for single-event-upset (SEU) measurement in SRAMs below the direct ionization threshold. Differences between various test conditions (e.g., “in air” or vacuum irradiations, with or without degraders) are also explored. Nuclear interactions with any materials in the beam's path can increase the number of high collected charge events potentially impacting the experimental results. A “species” effect has been observed in the power MOSFET devices examined in this work. When the beam energy increases, the single-event-burnout (SEB) voltage is constant, such that the SEB voltage is determined only by the species of the ion beam. The species effect is shown to be due to high collected charge events induced by nuclear interactions, which can lead to premature SEB. If a device is sensitive to the species effect, the worst-case test conditions will be for the heaviest ion species, which can produce the largest linear-energy-transfer (LET) secondaries. SRAMs can also be sensitive to the species effect below the direct ionization threshold LET. For the devices used in this work, the worst-case energy for SEU characterization is <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\sim 10'{\rm s}~{\rm MeV/u}$</tex> </formula> where the species dominates the device response. In the 10's MeV/u range the heaviest species result in the largest cross sections. However, at very high energies (100's MeV/u), the species is not the dominant parameter because of differences in the population of secondaries created by nuclear interactions. At very high energies the SEU cross section below the direct ionization threshold LET decreases by several orders of magnitude compared to 10's MeV/u SEU data. The results of this work emphasize that there is no such thing as an “ideal” test facility. Nevertheless, these results can be used by experimenters to optimize the integrity of their results for given test conditions.

Laser- and Heavy Ion-Induced Charge Collection in Bulk FinFETs

Through-wafer two-photon absorption laser experiments were performed on bulk FinFETs. Transients show distinct signatures for charge collection from drift and diffusion, demonstrating the contribution of charge generated in the substrate to the charge collection process. This result was validated through heavy ion testing on more advanced bulk FinFETs with fin widths as narrow as 5 nm. The drain region dominates the charge collection, with as much as 45 fC of charge collected in the drain region.

A Dual Mode Redundant Approach for Microprocessor Soft Error Hardness

A dual mode redundant (DMR) logic data path with instruction restart that detects errors at register file (RF) write-back is presented. The DMR RF allows SEU correction using parity to detect RF entry nibbles that are correct in one copy but not the other. Detection and backing out incorrect write data are also described. The radiation hardened by design (RHBD) circuits are implemented in 90 nm CMOS. The DMR microarchitecture is described, including pipelining, error handling, and the associated hardware. Heavy ion and proton testing validate the approach. Experimentally measured cross sections and examples of errors due to pipeline SET or RF SEU are shown. Critical node spacing and the mitigation of multiple node collection are also described.

Fully Automated, Testable Design of Fine-Grained Triple Mode Redundant Logic

A fully automated logic design methodology for radiation hardened by design high-speed logic using fine-grained triple modular redundancy (TMR) is presented. The methodology and circuits leverage commercial logic design automation tools. The circuit approach is validated for hardness using both heavy ion and proton broad beam testing. The base TMR self-correcting master-slave flip-flop is described, including testability features that disable the self-correction. The flow allows hardening of any synthesizable logic at clock frequencies comparable to unhardened designs and supports standard low-power techniques, e.g., clock gating and supply voltage scaling.

Circuit-Level Layout-Aware Single-Event Sensitive-Area Analysis of 40-nm Bulk CMOS Flip-Flops Using Compact Modeling

A circuit-level layout-aware single-event simulation capability is presented. Multiple 40-nm bulk CMOS flip-flops are analyzed to determine single-event upset (SEU) sensitive area. Comparisons between simulation results and broadbeam heavy-ion test data show excellent agreement. Simulations of single-event strikes over the entire flip-flop layout can be performed in less than 1 h.

Combining Results of Accelerated Radiation Tests and Fault Injections to Predict the Error Rate of an Application Implemented in SRAM-Based FPGAs

An approach combining the SRAM-based field-programmable gate array static cross-section with the results of fault injection campaigns allows predicting the error rate of any implemented application. Experimental results issued from heavy ion tests are compared with predictions to validate the proposed methodology.

Area-Efficient Temporally Hardened by Design Flip-Flop Circuits

Two temporally hardened master-slave flip-flops are presented. Both designs utilize master latches containing Muller C-elements and dual redundant temporal hardening, as well as spatially interleaved circuits in both the master and slave latches to obtain large critical node spacing for immunity to multiple node charge collection. Heavy ion test results on the first flip-flop, which uses a DICE slave latch, demonstrates effectiveness of the temporal hardening approach. The second design uses a temporally hardened slave latch, which also hardens the flip-flop against clock transients. The use of automated CAD synthesis and layout techniques using these multibit flip-flops is also described, as is the hardening impact on design size and power.