Heavy Ion Single Event Effects Research Articles

A comprehensive study of InGaAs based linearly graded channel DL-TFET and its single event transient effect

In this paper, the DC, RF and single-event transient effect studies are carried out for investigating the performance and reliability of hetero-junction InGaAs DL-TFET having linearly graded channel region. The mole-fraction of source side In1−xGaxAs is varied for obtaining the higher ION i.e. obtained at x = 0.40; this also impact the RF simulation studies by increasing the gain-bandwidth product range to 52.4 GHz. To reduce Iambipolar, a step junction is introduced for first time in the channel region at channel-drain interface which reduces the Iambipolar by 93.27% to the magnitude of 0.867 μA μm−1. Further reduction in ambipolarity is achieved at TG = 3.9 eV to the level of 0.269 fA μm−1, ION increases to 0.558 mA μm−1, sub-threshold swing is 23.8 mV/decade and shows highest cut-off frequency upto 155 GHz. Hence, the optimized device structure is investigated under the influence of single-event transient; therefore, the effect of heavy ion is investigated on optimized linearly graded structure for different LETs’ (Linear energy transfer). It shows increase in the drain current and charge collected with increase in LET. The maximum IDS is 0.618 mA μm−1 in OFF state, and IDS of 0.819 mA μm−1 in ON state at VDS = 1.0 V, which is higher than its ION at 10 MeV.cm2/mg (i.e. 0.11 pC μm−1). By simulating heavy ion single event effect on different positions, it is found that channel-drain interface is more sensitive to irradiation. This gives an insight for radiation hardened applications in space for TFET based circuit designs.

Heavy Ion Single Event Effects in CMOS Image Sensors: SET and SEU

High-energy particles in space often induce single event effects in CMOS image sensors, resulting in performance degradation and functional failure. This paper focuses on the formation and morphology of transient bright spots in CMOS image sensors and analyzes the formation process of transient bright spots by conducting heavy ion irradiation experiments to obtain the variation law of transient bright spots with heavy ion linear energy transfer values and background gray values; in addition, we classify the single event upset that occurred in the experiments according to the state of transient bright spots and extract the characteristics of different single event upsets. The failure mechanisms of different single event upsets are analyzed according to their characteristics and are combined with the information given by transient bright spots. This provides an essential reference for rapidly evaluating single event effects and the reinforcement design of CMOS image sensors.

Influences of well contact on multiple-cell upsets in 28 nm SRAM

In order to study the effects of the feature size reduction and well contact placement on the characterization of topology patterns and the charge collection mechanism of device heavy ion single event multiple upset on a nanometer scale, the heavy ion single event effect experiment on the domestic 28 nm static random-access memory (SRAM) is carried out on the experimental platform of HI-13 heavy ion accelerator in Beijing. Based on the mapping relationship between the logical address and physical address of the device, the experimental data are processed, and the 28 nm SRAM heavy ion single event upset cross section curves, multiple upset percentage, and multiple upset topology patterns are obtained. The results are compared with those of heavy ion single event effect experiments in 65 nm SRAM, showing that under the influences of factors such as feature size reduction and lower operating voltage, the heavy ion single event upset threshold and the bit upset saturation cross section of 28 nm SRAM decrease significantly. In the direction perpendicular to the well, owing to the reduced 28 nm SRAM feature size, even if the single nucleon energy of the incident high LET (linear energy transfer) heavy ion is low, its deposited charge is sufficient to affect the three SRAM cells across the well direction due to the combined effect of ion track coverage, well potential modulation caused by the parasitic bipolar amplification effect and carrier diffusion, resulting in the fact that the 28 nm SRAM topology pattern has a shape of <i>n</i> rows × 3 columns, which poses new challenges and requirements for the anti-radiation hardened technology with scrubbing and EDAC (error detection and correction). Owing to the global well contact deployment, the charge deposited by the incident ions in the well far away from the well contact is difficult to discharge quickly, and the parasitic bipolar amplification effect lasts longer. The charge sharing competition between two p-channel metal oxide semiconductor in SRAM cell causes the single event upset recovery, which is the fundamental reason why the discontinuity of multiple upset topology pattern appears in 28 nm SRAM. This study provides a new anti-radiation hardened idea for suppressing the single event upset by using the parasitic bipolar amplification in the future.

Heavy ion single event effect in double-trench SiC metal-oxide-semiconductor field-effect transistors

In this paper, experiments on 208 MeV Ge ion irradiation with different source-drain bias voltages are carried out for the double-trench SiC metal–oxide–semiconductor field-effect transistors, and the physical mechanism of the single event effect is analyzed. The experimental results show that the drain leakage current of the device increases more obviously with the increase of the initial bias voltage during irradiation. When the bias voltage is 400 V during irradiation, the device has a single event burned at a fluence of 9×10<sup>4</sup> ion/cm<sup>2</sup>, and when the bias voltage is 500 V, the device has a single event burned at a fluence of 3×10<sup>4</sup> ion/cm<sup>2</sup>, so when the LET value is 37.3 MeV·cm<sup>2</sup>/mg, the SEB threshold of DUT does not exceed 400 V, which is lower than 34% of the rated operational voltage. The post gate-characteristics test results show that the leakage current of the device with a bias voltage of 100 V does not change significantly during irradiation. When the bias voltage is 200 V, the gate leakage and the drain leakage of the device both increase, so do they when the bias voltage is 300 V, which is positively related to bias voltage. In order to further analyze the single particle effect mechanism of device, the simulation is conducted by using TCAD tool. The simulation results show that at low bias voltage, the heavy ion incident device generates electron-hole pairs, the electrons are quickly swept out, and the holes accumulate at the gate oxygen corner under the effect of the electric field, which combines the source-drain bias voltage, leading to the formation of leakage current channels in the gate oxygen layer. The simulation results also show that at high bias voltage, the electrons generated by the incident heavy ion move towards the junction of the N<sup>–</sup> drift layer and the N<sup>+</sup> substrate under the effect of the electric field, which further increases the electric field strength and causes significant impact ionization. The local high current density generated by the impact ionization and the load large electric field causes the lattice temperature to exceed the melting point of silicon carbide, causing single event burnout. This work provides a reference and support for studying the radiation effect mechanism and putting silicon carbide power devices into aerospace applications.

Dealing With Ion LET Uncertainties: An Application of Generalized Linear Models

Although most single-event effect (SEE) rate estimation methods presume a fit to SEE cross section versus linear energy transfer (LET), fitting SEE data is challenging because the data are not compatible with the assumptions of many common fitting techniques (e.g., linear regression). The difficulty of fitting such data is compounded when the LET of the ion responsible for an SEE is uncertain. We modify a generalized linear model, SEE data fitting methodology, to accommodate uncertain LET and apply the method to the problem of backside heavy-ion SEE testing to demonstrate its utility, explore the dependence of systematic errors that arise from improper treatment of LET uncertainty, and develop guidelines for minimizing such systematic errors when proper treatment is not possible. Additional applications are suggested and assessed for suitability to treatment by the model.

Research on single event effect test of a RRAM memory and space flight demonstration

As a non-volatile memory, the resistive random access memory (RRAM) has some advantages in radiation tolerance and application prospects in space. RRAM has the advantages of high storage density, high repetition times and three-dimensional storage. This paper analyzed the working principle of RRAM, selected an RRAM memory as the research object, carries out the sensitivity test of heavy ion single event effect. The single event effect on orbit outage rate of the device was calculated by using the space on-orbit prediction software, ForeCAST. In addition, the natural anti-radiation performance of the storage area of the device was verified by pulsed laser induced test, and the good anti-radiation performance of the device was further verified by space flight test.

Effect of source-drain conduction in single-event transient on nanoscaled bulk fin field effect transistor

Fin field effect transistor (FinFET) is a most widely used structure when the field effect transistor is scaled down to 30 nm or less. And there are few studies on single-event transient of FinFET devices with gate length below 30 nm. The single-event-transient on FinFET with gate length below 30 nm is worth studying. The single-event-transient responses of bulk FinFETs with 30 nm, 40 nm, 60 nm and 100 nm gate length are examined by using the pulsed laser and technology computer-aided design (TCAD) simulation in this article. First, we use the pulsed laser to ionize the gate of the FinFET device and detect the transient drain current of the FinFET device. The experimental results show that there are obvious platforms for the transient drain current tails of FinFETs with different gate lengths, and the platform current increases as the gate length of FinFET becomes shorter. The charges collected in the platform of FinFET devices with gate lengths of 100, 60, 40, and 30 nm are 34%, 40%, 51%, and 65% of the total charge collected in transient drain current, respectively. Therefore, when the FinFET device with the gate length below 100 nm, the platform current will seriously affect the device performance. Second, we use TCAD to simulate the heavy ion single-event effect of FinFET device and study the generation mechanism of platform region in transient drain current. The TCAD simulation explains this mechanism. Laser or heavy ions ionize high concentration electron-hole pairs in the device. The holes are quickly collected and the high concentration electrons are left under the FinFET channel. High concentration electrons conduct source and drain, generating the source-to-drain current at the tail of the transient drain current. Moreover the source-drain conduction enhances the electrostatic potential below the FinFET channel and suppresses high-concentration electron diffusion, making source-to-drain current decrease slowly and form the platform. The transient drain current tail has a long duration and a large quantity of collected charges, which seriously affects FinFET performance. This is a problem that needs studying in the single-event effect of FinFET device. It is also a problem difficult to solve when the FinFET devices are applied to spacecraft. And the generation mechanism of the transient drain current plateau region of FinFET device can provide theoretical guidance for solving these problems.

Erratum to: Experimental study on heavy ion single-event effects in flash-based FPGAs

Erratum to: Experimental study on heavy ion single-event effects in flash-based FPGAs

Experimental study on heavy ion single-event effects in flash-based FPGAs

With extensive use of flash-based field-programmable gate arrays (FPGAs) in military and aerospace applications, single-event effects (SEEs) of FPGAs induced by radiations have been a major concern. In this paper, we present SEE experimental study of a flash-based FPGA from Microsemi ProASIC3 product family. The relation between the cross section and different linear energy transfer (LET) values for the logic tiles and embedded RAM blocks is obtained. The results show that the sequential logic cross section depends not too much on operating frequency of the device. And the relationship between 0 → 1 upsets (zeros) and 1 → 0 upsets (ones) is different for different kinds of D-flip-flops. The devices are not sensitive to SEL up to a LET of 99.0 MeV cm2/mg. Post-beam tests show that the programming module is damaged due to the high-LET ions.

Use of Proton SEE Data as a Proxy for Bounding Heavy-Ion SEE Susceptibility

Although heavy-ion single-event effects (SEE) pose serious threats to semiconductor devices in space, many missions face difficulties testing such devices at heavy-ion accelerators. Low-cost missions often find such testing too costly. Even well funded missions face issues testing commercial off the shelf (COTS) due to packaging and integration. Some missions wish to fly COTS systems with little insight into their components. Heavy-ion testing such parts and systems requires access to expensive and hard-to-access ultra-high energy ion accelerators, or significant system modification. To avoid these problems, some have proposed using recoil ions from high-energy protons as a proxy to bound heavy-ion SEE rates.

Radiation Hardness Assurance Testing of Microelectronic Devices and Integrated Circuits: Test Guideline for Proton and Heavy Ion Single-Event Effects

This document gives detailed test guidelines for single-event upset (SEU), single-event latchup (SEL), single-event burnout (SEB), and single-event gate rupture (SEGR) hardness assurance testing. It includes guidelines for both heavy-ion and proton environments. The guidelines are based on many years of testing at remote site facilities and our present understanding of the mechanisms for single-event effects.

纳米DDR SRAM器件重离子单粒子效应试验研究

纳米DDR SRAM器件重离子单粒子效应试验研究

Effects of Scaling in SEE and TID Response of High Density NAND Flash Memories

Heavy ion single-event effect (SEE) measurements and total ionizing dose (TID) response for Micron Technology single-level cell 1, 2, 4, 8 Gb commercial NAND flash memory and multi-level cell 8, 16, 32 Gb are reported. The heavy ion measurements were extended down to LET 0.1 MeV-cm2/mg. Scaling effects in SEE and TID response are discussed. Floating gate bit error upset cross section does not scale with feature size at high LETs, except for single-level cell 8 Gb device which is built with 51 nm processes. The threshold LET does not change with scaling. Charge pump TID degradation and standby current improves with scaling. In general, the effect of radiation is either unchanged or is less severe for highly scaled NAND flash memories.

Experimental study on heavy ion single event effects in SOI SRAMs

Silicon-on-insulator (SOI) technologies have been developed for radiation-hardened military and space applications. The use of SOI has been motivated by the full dielectric isolation of individual transistors, which prevents latch-up. The sensitive region for charge collection in SOI technologies is much smaller than for bulk-silicon devices potentially making SOI devices much harder to single event upset (SEU). In this study, 64 kB SOI SRAMs were exposed to different heavy ions, such as Cu, Br, I, Kr. Experimental results show that the heavy ion SEU threshold linear energy transfer (LET) in the 64 kB SOI SRAMs is about 71.8 MeV cm 2/mg. Accorded to the experimental results, the single event upset rate (SEUR) in space orbits were calculated and they are at the order of 10 −13 upset/(day bit).

Heavy-Ion SEE Test Concept and Results for DDR-II Memories

In order to investigate heavy ion single event effects (SEEs) in advanced commercial DDR-II SDRAM memories, a large number of practical problems need to be addressed ranging from test approach, sample preparation, error analysis, physical error identifications and effective LET corrections before test results can be presented. This paper continues where Harboe-Soslashrensen et al. , 2003, ended with further details on most of the critical steps mentioned above. Additionally, the first set of SEE data will be presented and discussed covering Samsung, Infineon, Micron, and Elpida 512 M-bit DDR-II memory devices.

Radiation testing of GLAST LAT tracker ASICs

Gamma-ray large area space telescope (GLAST) is a next generation high-energy gamma-ray space observatory designed for observations of celestial gamma-ray sources in the energy band extending from 10 MeV to more than 100 GeV. The main instrument, the large area telescope (LAT), consists of a microstrip silicon tracker, a calorimeter, an anticoincidence detector, and the data acquisition (DAQ) system. This paper summarizes the results obtained during the radiation testing of the ASIC chips used in the LAT tracker. Both single event effects (SEE) and total ionizing dose effect (TID) tests have been performed, as part of the radiation hardness assurance (RHA) for the planned 5-yr mission. Heavy-ion SEE tests have been performed at the SIRAD irradiation facility at the INFN National Laboratories of Legnaro, Italy (LNL) and at the Texas A&M University (TAMU) Cyclotron Institute, with LET values ranging up to /spl sim/80 MeV/spl times/cm/sup 2//mg. The tolerance of the chips to ionizing radiation has been evaluated with heavy ions and by irradiating chips with the spherical /sup 60/Co gamma source of the LNL CNR-ISOF laboratory.

Heavy-ion single-event effects testing of lead-on-chip assembled high-density memories

For space applications, can cost-effective and reliable heavy ion single-event effect (SEE) testing still be carried out on commercially available, plastic packaged, high-density memories? Their complexity, architecture, and packaging assemblies as well as their short life cycle pose many practical problems that needs to be tackled. This paper summarizes steps taken by the European Space Agency in order to address these issues.

Effects of low-temperature buffer-layer thickness and growth temperature on the SEE sensitivity of GaAs HIGFET circuits

Heavy-ion Single Event Effects (SEE) test results reveal the roles of growth temperature and buffer layer thickness in the use of a low-temperature grown GaAs (LT GaAs) buffer layer for suppressing SEE sensitivity in GaAs HIGFET circuits.

Update on parts SEE suspectibility from heavy ions

Jet Propulsion Laboratory (JPL) and the Aerospace Corporation have collected a fourth set of heavy ion single event effects (SEE) test data (previous sets were reported in contribution IEEE Trans. on Nuclear Sci. in December 1985, 1987, and 1989). Trends in SEE susceptibility (including soft errors and latchup) for state-of-the-art parts are displayed. All data are conveniently divided into two tables: one for MOS devices, and one for a shorter list of recently tested bipolar devices. In addition, a new table of data for latchup tests only (invariably CMOS processes) is given. >