Head Process Research Articles

PROCESSING OF WELLHEAD CHRISTMAS TREES PIPE HEADER

In this study, the components of the tubing head of the Wellhead Christmas tree are classified. Information on how to install the tubing head to the Christmas tree (oil and gas) is also provided. The tested tubing head ensures the passage of liquid or gas into the spaces between the tubes. They have to control the pressure and conduct the necessary well studies. The tubing header seals and hangs the riser columns, which is especially effective when inserting concentric or parallel columns into the well. As a result of the conducted studies, the tubing head fully controls the flow of the technological liquid. Tubing headers to perform these processes should be manufactured according to the working pressure requirements between 14 and 105 MPa. Using a tubing head, you can connect different numbers of pipelines, as well as control the distribution of the medium flow in the circular zone of the valve. Of the cost-effective methods we have mentioned one is connected to the upper flange of the pipeline column header with a lower mounting fixing component. The design of the tubing head is completed by threaded holes in the body through which you can quickly replace the side valves in the head tube. The tubing head is designed to stop one or more rows of riser (pump and compressor) tubes and is used to perform technological operations during the development, operation and repair of wells. The top of the tubing at the wellhead is screwed into the tubing cap of the Christmas tree (oil and gas). Once installed at the wellhead, the Christmas tree (oil and gas) tubing header is compressed to the allowable pressure for pressure testing the production casing. Tubing head design and strength characteristics are shown in this figure: a) working pressure (7, 14.21, 35, 70 and 105 MPa), b) numbers of pipes lowered into the well (one and two concentric rows of pipes), c) constructions of locking devices (valves and taps) dimensions of the flow section along the trunk (50... 150 mm) and side branches (50... 100 mm). The tubing head holds and takes over the pressure generated between the tubes and can be prohibitive, which is quite dangerous for people's lives and health. Keywords: Christmas tree (oil and gas), tubing header, pressure, flow, wellhead, test, well.

High Precision Latency Forwarding for Wide Area Networks Through Intelligent In-Packet Header Processing (gLBF)

High Precision Latency Forwarding for Wide Area Networks Through Intelligent In-Packet Header Processing (gLBF)

Network Coding Datagram Protocol for TCP/IP Networks

In this article, a new multicast protocol is introduced at the session layer, which is based on network coding and is called the Network Coding Datagram Protocol (NCDP). The NCDP protocol is specifically designed for content delivery systems that utilize multicast data transmission from multiple sources. The development of the NCDP packet and its operational logic takes into consideration the variability of the protocols used in conjunction with it, as well as the packet header processing algorithms for routing nodes-coders. Additionally, a virtual laboratory bench is proposed to facilitate research on the operation of the protocol. The article also includes the results of testing the NCDP protocol in networks with butterfly and diamond topologies, with a comparison between simple sequential multicast transmission and network coding transmission.

Simulation and analysis models of hybrid software­configured devices

The analysis of the algorithm, based on which the simulation and analytical model of the hybrid software-configurable device is automatically synthesized, was carried out. The solution for modeling OpenFlow equipment was also considered, and an original OpenFlow switch model was developed, which is distinguished by the ability to manage delays based on the results of its mathematical model. The operation scheme of a hybrid switch that supports both traditional switching and OpenFlow switching has been developed. This scheme allows solving complex tasks in the physical infrastructure of virtualized networks. A module has been developed to create a realistic delay and limit the capacity and performance of the hybrid switch model, which can work according to the data obtained as a result of the experimental study. Additional traffic processing schemes have been developed for a more detailed implementation of the hybrid software-configurable equipment model. The basic model of the switch presented in the INET OMNeT++ framework is considered. The switch is represented by a set of modules interacting through the OMNeT transmission system. The most detailed modules of Ethernet interfaces are implemented, in particular, there are implementations of the input queue of the Tail-Drop type, output queues of the FIFO, RED, WRED, PQ, CBFQ types, as well as the implementation of the transmission delay on the line. The virtualization technology of network functions, which is built on the basis of software-configured networks, has been studied, and the most popular Linux-based solutions are used as a software-controlled Open vSwitch switch. The considered methods of forming a model of such a switch. Open vSwitch is architecturally different from both classical and OpenFlow real switches, as there are no dedicated packet refactoring units (except for network cards with hardware header processing and FPGAs), dedicated memory and processors for switching, Open vSwitch uses a kernel module (or module DPDK for direct transmission without the participation of the kernel) to transmit packets based on information from the OVSDB database or OpenFlow tables.

High‐performance user plane function (UPF) for the next generation core networks

Comparing with previous mobile communications, the fifth generation (5G) mobile communication provides three different types of services including enhanced mobile broadband, massive machine type communications, and ultra-reliable and low latency communications. To fulfil various requirements of these services, 5G defines new technologies and architectures such as the next-generation core network (NGC) and the new radio of the access network (5G-AN). The user plane function (UPF), which is an essential component in 5G NGC, connects 5G-AN and packet data networks (e.g. internet). Typically, the UPF provides the tunnelling, internet protocol/port translation, and forwarding functions. To provide flexibility and scalability deployment for 5G NGC, this study virtualises the UPF by using the Docker container. However, the virtualisation architecture degrades the performance of the UPF, and the performance of the UPF dominates the performance (e.g. throughput) of the 5G user-plane transmission. To provide high-performance packet processing, this study utilises Intel Data Plane Development Kit to develop the UPF, reduces the number of memory copy on header processing, and investigates the CPU core allocation methods for the UPF deployment. Based on the results of this study, the proposed UPF can provide the UPF functions and process the packets up to 40 Gbps on a x86-based platform.

Photonic-Frame-Based TCP proxy architecture in optically interconnected data center networks

Optical switching is a good candidate for achieving the key requirements of high scalability, low latency and low power consumption in future large-scale data center networks (DCNs). However, circuit-based optical switching has a disadvantage of a long reconfiguration time. Packet-based optical switching also faces challenges such as the complexity of optical header processing and the difficulty of buffering in optical switches to resolve contention. To address these problems, we present a packet-switched optical network architecture design with a photonic frame wrapper that can generate variable-size photonic frames for optically interconnected intra-DCN. The proposed architecture forms hybrid DCN architecture consisting of a flattened optical switch layer for the data path and a conventional electrical switch layer for the control path. The photonic frame wrapper can increase bandwidth utilization by minimizing guard-time insertion in the optical switch domain. We also introduce a photonic frame wrapper with proxy solution to fully exploit the gain of the proposed architecture even in inter-DCN communication with long delays, which is compliant with standard TCP instances at end nodes. In intra-DCN, the average queuing delay is analyzed to find the efficient combinations between the guard time and time-slot length for the variable-sized photonic frame. We also analyzed the bandwidth overhead of guard time, to show it is comparable to that of Ethernet based DCN. In inter-DCN, the proxy solution demonstrates a noticeable TCP performance enhancement compared with the photonic frame wrapper in terms of bandwidth efficiency and end-to-end delay by theoretical and OPNET simulation analyses.

Design of 2-to-4 All-Optical Decoder with the Help of Terahertz Optical Asymmetric Demultiplexer

An all-optical 2-to-4 decoder unit with the assist of terahertz optical asymmetric demultiplexer (TOAD) is presented. The all-optical 2-to-4 decoder with a set of all-optical switches is designed which can be used to achieve a high-speed central processor unit using optical hardware. The unique output lines can be used for all-optical header processing. We attempt to develop an integrated all-optical circuit which can perform decoding of signal. This scheme is very simple and flexible for performing different logic operation and to design advanced complex logic. Simulated results are confirming the described methods.

Demonstration of 100 Gbps optical packet switching using header processor based on 48-bit longest prefix matching

Wire-rate packet processing and its energy saving for over 100 Gbps speed of line are major issues to be resolved in optical packet switching (OPS) networks. For that purpose, we newly develop a high-speed, deterministic-latency electronic header processor based on longest prefix matching (LPM) for searching optical packet destination addresses (OP-DAs). This paper reports the successful experimental results of electronic header processing based on LPM search of up to 48 bits and optical switching of 100 Gbps optical packets by the use of the header processor. We demonstrate 48-bit LPM-capable optical packet switching. We also demonstrate IP packet transfer and 32-bit LPM-capable optical packet switching. In the latter demonstration, the 32-bit OP-DA of optical packets is directly copied from the 32-bit destination address of Internet Protocol version 4 (IPv4) packets. This result indicates that OPS networks can be deployed with electronic IP networks by the use of integrated network operation between OPS and IP networks.

Performance evaluation of optical code division multiple access systems

In this paper, a new mechanism of faster routing known as message priority and fast routing (MPFR) mechanism in optical code division multiple access (OCDMA) is proposed for optimization of routing performance and to provide effective data transfer. In this proposed work, we have reduced the size of the header bits which are used in MPFR mechanism. In proposed algorithm, with accordance to packet header, the message size is being increased and priority bit is being added which leads to faster data transfer rate and effective data transfer in OCDMA. The transmitter sent the 2D codes to the MPFR which is then added priority bit. If the cover bit in any codes is enabling then the code is considered to be a priority packet and its superior bit then the code is considered to be routing. A modern novel approach which reduces the overhead for fast data transfer is proposed on name of MPFR. Thus the routing can be faster and the codes to be sent are being priorities and send. Thus the OCDMA can now become much faster to be used in critical areas. MPFR protocol, which prioritizes the code with high priority and also it reduces the header processing time of the codes with increase in message size. The prioritization of the code helped to process the particular code first and then rest of the codes and with increase in message size, help to reduce the transmission and processing time of the packet header.

Energy Efficient Parallel Optical Burst Switching (POBS) Networks

Greening the Internet has recently become one of the main challenges for the research community due to economic and environmental reasons. In this context, optical technology can offer an energy efficient solution. As such it is interesting to examine Optical Burst Switching (OBS) network that provides an avenue for reducing energy consumption by significantly reducing the amount of header processing in the core switch. A variant of OBS, which is known as Parallel Optical Burst Switching (POBS), takes this concept further by transmitting bursts in two dimensions: the wavelength dimension and the time dimension. Consequently, this study investigates the power consumption in both the OBS and POBS technologies when used in the core network. The simulation results show that in the core network, the use of POBS can provide significant saving in energy as compared to the use of OBS. Furthermore, the use of POBS can lower the power consumption and the number of packets dropped in the network when appropriate parameter settings are used, particularly the burstification time and waveband granularity.

Keyflow: a prototype for evolving SDN toward core network fabrics

The large bulk of packets/flows in future core networks will require a highly efficient header processing in the switching elements. Simplifying lookup in core network switching elements is capital to transport data at high rates and with low latency. Flexible network hardware combined with agile network control is also an essential property for future software-defined networking. We argue that only further decoupling between the control and data planes will unlock the flexibility and agility in SDN for the design of new network solutions for core networks. This article proposes a new approach named KeyFlow to build a flexible network-fabricbased model. It replaces the table lookup in the forwarding engine by elementary operations relying on a residue number system. This provides us tools to design a stateless core network by still using OpenFlow centralized control. A proof of concept prototype is validated using the Mininet emulation environment and OpenFlow 1.0. The results indicate RTT reduction above 50 percent, especially for networks with densely populated flow tables. KeyFlow achieves above 30 percent reduction in keeping active flow state in the network.

Linear random code-based label encoding scheme for label swapping free optical packet switching networks

Optical Label Switching (OLS) has been considered to be a promising approach to realize optical packet switching (OPS) networks. In an OLS router, the header processing module retrieves the routing information carried in the optical header and then replaces the old header with a new one through optical label swapping. The cost-effectiveness and the speed of performing label swapping are two major concerns. Due to lack of optical random access memory, optical label swapping has become a big challenging issue in implementing OLS switches. To overcome these difficulties, in this paper, we propose two Linear Random Code (LRC)-based label encoding schemes to achieve label swapping free OPS networks. Using the proposed schemes, a small sized label is needed. Only simple modulo-2 multiplication and modulo-2 addition operations are required to decode an optical label and there is no optical label swapping during packets traverse along the entire routing path. In our system, each source–destination pair is assigned multiple paths so the network is with traffic engineering and fault tolerance capabilities. We have carried out extensive simulations to evaluate the performance of the proposed scheme. Compared with the well-known KIS encoding scheme, the proposed LRC-based scheme can reduce the label size significantly. An 8-byte LRC label is long enough to support all node pair with five paths in a 300-node network.

A 10 Gbps in-line network security processor based on configurable hetero-multi-cores

This paper deals with an in-line network security processor (NSP) design that implements the Internet Protocol Security (IPSec) protocol processing for the 10 Gbps Ethernet. The 10 Gbps high speed data transfer, the IPSec processing including the crypto-operation, the database query, and IPSec header processing are integrated in the design. The in-line NSP is implemented using 65 nm CMOS technology and the layout area is 2.5 mm×3 mm with 360 million gates. A configurable crossbar data transfer skeleton implementing an iSLIP scheduling algorithm is proposed, which enables simultaneous data transfer between the heterogeneous multiple cores. There are, in addition, a high speed input/output data buffering mechanism and design of high performance hardware structures for modules, wherein the transfer efficiency and the resource utilization are maximized and the IPSec protocol processing achieves 10 Gbps line speed. A high speed and low power hardware look-up method is proposed, which effectively reduces the area and power dissipation. The post simulation results demonstrate that the design gives a peak throughput for the Authentication Header (AH) transport mode of 10.06 Gbps with the average test packet length of 512 bytes under the clock rate of 250 MHz, and power dissipation less than 1 W is obtained. An FPGA prototype is constructed to verify the function of the design. A test bench is being set up for performance and function verification.

All-Optical Header Recognition and Packet Switching Using Polarization Bistable VCSEL

We demonstrate an optical header processing system using a 1.55-μm polarization bistable vertical-cavity surface-emitting laser (VCSEL) that operates as an all-optical AND gate and a holding element. Depending on the state of 1 bit in the 4-bit header, the VCSEL held one of two-orthogonal polarization states. The light of the VCSEL output through a polarizer switched and held the output state of an optical switch. This enables the payload to be sent to the destination determined by the header. The characteristics of the polarization bistable VCSEL enable low-power consumption and lower latency operation. The system also has the potential to process multibit optical headers involved in ultrafast optical packets.

Building Optical Packet Networks Without Buffering, Signaling or Header Processing

We propose a technique for building optical packet networks that does not require any buffering, signaling or header processing. Contentions are solved by means of an optical device that allows the first packet to go through while blocking others. Blocked packets are redirected back to their source nodes, thus notifying the latter about the packet status. We describe the design principles of the corresponding all-optical networks, assess their performance and power consumption, and give examples of application in the context of access networks and data centers.

Frame Assembly and Scheduling on Edge Routers in Fixed-Size Frame-Switching Networks

Frame assembly is seen as an important technology in future core networks since it can mitigate the ever-increasing packet header processing load on network nodes. Since frame assembly changes the pattern of traffic entering the network, it has a significant impact on such aspects of network performance as packet drop probability and end-to-end delay. This paper focus on the packet drop and delay performance on assembly nodes, sometimes called edge routers. We reveal that frame assembly on edge routers is in fact a tradeoff between packet loss performance and fairness, especially when the input client traffic is non-uniformly distributed among multiple destinations. We evaluate existing frame assembly and scheduling algorithms and try to cope with the assembly and scheduling process holistically by proposing a new algorithm, named highest efficiency fair queuing. Simulation results show that the proposed algorithm provides better performance in terms of delay and jitter, while also minimizing the average packet loss rate.

NP-SARC: Scalable network processing in the SARC multi-core FPGA platform

A multicore FPGA platform with cache-integrated network interfaces (NIs) has been developed, appropriate for scalable multicores, that combine the best of two worlds - the flexibility of caches (using implicit communication) and the efficiency of scratchpad memories (using explicit communication). Furthermore, the proposed scheme provides virtualized user-level RDAM capabilities and special hardware primitives (counter, queues) for the communication and synchronization of the cores. This paper presents how the proposed architecture can be utilized in the domain of network processing applications using the hardware synchronization mechanisms. Two representatives network processing benchmarks are used; one for header processing and one for payload processing. The Multiple Reader Queue (MRQ) scheme is utilized in the case of header processing, while in the case of payload processing where transfer of bulk data is required, the user-level RDMA scheme is utilized. These applications are mapped and evaluated to an FPGA platform with up to 24 processors. The performance evaluation in the domain of network processing shows that the proposed scheme can offer low latency communication and increased programming efficiency while it also offloads the processor from the communication and synchronization processes.

Broadband Silicon Photonic Packet-Switching Node for Large-Scale Computing Systems

We present a broadband packet-switching node that utilizes silicon photonic technology. The node design uses a silicon microring for switching functionality, leverages in-flight header processing for arbitration, and has a tunable driving circuit for thermal-effect mitigation. Moreover, these integrated microring switches are capable of scaling to tremendously high port counts in a compact area, which are attractive for data-center networks. We experimentally characterize the extinction ratio of the switch for varying packet durations, interarrival times, and driving voltages and demonstrate an error-free routing of 10-Gb/s wavelength-striped packets with lengths of up to 1536 ns. We further study the resonance thermal drifting for long- hold-time packet switching through carrier injection and show thermal-effect mitigation using a pre-emphasized gating signal.

A 320 Gb/s-Throughput Capable 2$\,\times\,$2 Silicon-Plasmonic Router Architecture for Optical Interconnects

We demonstrate a 2 × 2 silicon-plasmonic router architecture with 320 Gb/s throughput capabilities for optical interconnect applications. The proposed router platform relies on a novel dual-ring Dielectric-Loaded Surface Plasmon Polariton (DLSPP) 2 × 2 switch heterointegrated on a Silicon-on-Insulator (SOI) photonic motherboard that is responsible for traffic multiplexing and header processing functionalities. We present experimental results of a Poly-methyl-methacrylate (PMMA)-loaded dual-resonator DLSPP waveguide structure that uses two racetrack resonators of 5.5 μm radius and 4 μ m-long straight sections and operates as a passive add/drop filtering element. We derive its frequency-domain transfer function, confirm its add/drop experimental spectral response, and proceed to a circuit-level model for dual-ring DLSPP designs supporting 2 × 2 thermo-optic switch operation. The validity of our circuit-level modeled 2 × 2 thermo-optic switch is verified by means of respective full vectorial three-dimensional Finite Element Method (3D-FEM) simulations. The router setup is completed by means of two 4 × 1 SOI multiplexing circuits, each one employing four cascaded second order micro-ring configurations with 100 GHz spaced resonances. Successful interconnection between the DLSPP switching matrix and the SOI circuitry is performed through a butt-coupling design that, as shown via 3D-FEM analysis, allows for small coupling losses of as low as 2.6 dB. The final router architecture is evaluated through a co-operative simulation environment, demonstrating successful 2 × 2 routing for two incoming 4-wavelength Non-Return-to-Zero (NRZ) optical packet streams with 40 Gb/s line-rates.

A novel scheme of all optical header extraction for optical packet switching network

A novel scheme of all optical header extraction using a semiconductor optical amplifier-Mach-Zehnder-Interferometer with asymmetric control light is proposed for optical packet switching with all-optical header processing at a header rate of 20 Gb/s and payload rate of 80 Gb/s in this article. The scheme parameters are discussed and analyzed to optimize the performance of optical header extraction with the proposed scheme. Numerical analysis and simulation show that a more than 17 dB contrast ratio can be achieved for the optical header separation when the input optical signal energy is as low as 0.2 pJ. In addition, the system structure is simple, stable, and photonic integratable.