HDL Description Research Articles

Flexible and High-Efficiency LDPC Encoder Architecture for CCSDS Standard

Abstract The Consultative Committee for Space Data Systems (CCSDS) has adopted quasi-cyclic low-density parity-check (QC-LDPC) codes for use in near-Earth (C2) and deep space (AR4JA) communications. Existing encoder architectures for C2 codes, however, fall short in efficiency for high-throughput applications. This paper introduces a comprehensive approach combining algorithmic and architectural optimizations to enhance hardware usage efficiency (HUE) while offering flexibility. We propose an integrated inter-block and intra-block parallel (IIB-IBP) encoding algorithm that leverages the unique matrix structure to significantly enhance performance. Additionally, a matrix-specific command register pretreatment (MSCRP) technique is developed to effectively handle the special dimensions of the generator matrix. Furthermore, we detail an offline design process for the automated generation of the encoder core’s HDL description, facilitating fine-tuning of encoding parallelism, latency, FPGA resource utilization, and overall throughput. Hardware implementation on a Virtex XC5VLX110T FPGA demonstrates that our encoder reaches an impressive throughput of 10.6 Gb/s with only 2531 LUTs and 1040 FFs, achieving a HUE of 2.97 Mbps/logic unit. This performance marks a 70.6% increase in HUE when compared to state-of-the-art designs.

A generator tool for Carry Look-ahead Adders (CLA)

A carry look-ahead adder (CLA) is a digital circuit which is used widely used in any electronic computational device to improve speed calculation by reducing the time required to define carry bits. Despite the fact that CLA is used massively in modern digital systems, there is no online tool to automatically generate the HDL description. For this reason we developed a cloud based tool to automate the design of optimized CLA and provide custom testbenches to verify their correctness for singed and unsigned numbers. It is also can be used by the students to create and understand deeply the way CLA works.

Methodology of Firmware Development for ARUZ—An FPGA-Based HPC System

ARUZ is a large scale, massively parallel, FPGA-based reconfigurable computational system dedicated primarily to molecular analysis. This paper presents a methodology for ARUZ firmware development that simplifies the process, offers low-level optimization, and facilitates verification. According to this methodology, firstly an expanded, generic, all-in-one VHDL description of variable Processing Elements (PEs) is developed manually. GCC preprocessing is then used to extract only the desired target functionality. A dedicated software instantiates and connects PEs in form of a scalable network, divides it into subsets for chips and generates its HDL description. As a result, individual HDL-coded specification, optimized for certain analysis, is provided for the synthesis tool. Code reuse and automated generation of up to 81% of the code economizes the workload. Using well-optimized VHDL for core description rather than High Level Synthesis eliminates unnecessary overhead. The PE network can be scaled inversely proportional to PEs complexity, in order to efficiently utilize available resources. Moreover, downscaling the problem makes verification during HDL simulations and testing the prototype systems easier.

Hardware Implementation of Authenticated Ciphers for Embedded Systems

The demand for embedded systems in applications that handle critical or private information has strongly focused designers' attention on the security aspects of this kind of system. Using the C programs and HDL descriptions available in the repositories of the CAESAR Competition and the ATHENa Project, this work presents a design flow that eases the development and evaluation of different solutions for the hardware implementation of authenticated ciphers and their incorporation as accelerating peripherals in embedded systems for different application cases. Three ciphers, finalists in the different categories established in the contest, have been analyzed, although the described approaches can be applied to any of the proposals submitted to the CAESAR Competition. A Zybo-Z7 development board that incorporates a Zynq-7000 device from Xilinx, which combines programmable logic from the FPGAs of the 7-Series with a dual-core Cortex-A9 ARM processing system, has been used as hardware platform in all the designs. The Vivado environment has been employed to perform the different stages of synthesis and verification necessary to carry out the implementation of the cipher, its conversion into an IP module, and its integration in an embedded system using different interconnection schemes that allow establishing cost/performance tradeoffs for different applications.

Hardware-Based Single-Clock-Cycle Edge Detector for a PLC Central Processing Unit

This article discusses edge detectors implemented in programmable logic controllers. The behaviors of different vendors’ solutions are presented with pros and cons. The trigger functions defined in the IEC 61131-3 standard were analyzed for implementations. The main contribution of this paper is an idea for hardware acceleration of standard trigger functions that enables us to build single-clock-cycle edge detectors. Additionally, the structure for automatic edge detection on every input is shown. The structure with a synthesizable Verilog HDL description is presented. The comparison of the solution with vendor programmable logic controllers (PLCs) proves the effectiveness of the designed hardware-aided unit.

Поиск конфликтов доступа к данным в HDL-описаниях

Data access conflicts may arise in hardware designs. One of the ways of detecting such conflicts is static analysis of hardware descriptions in HDL. We propose a static analysis-based approach to data conflicts extraction from HDL descriptions. This approach has been implemented in the Retrascope tool. The following types of conflicts are considered: simultaneous reads and writes, simultaneous writes, reading of uninitialized data, no reads between two writes. Conflict assertions are formulated as conditions on variables. HDL descriptions are automatically translated into formal models suitable for the nuXmv model checker. The translation process consists of the following steps: 1) preliminary processing; 2) Control Flow Graph (CFG) building; 3) CFG transformation into a Guarded Actions Decision Diagram (GADD); 4) GADD translation into a nuXmv format. Conflict assertions are automatically built using static analysis of the GADD model and passed to the nuXmv model checker. Bounded model checking is used to check whether these assertions are satisfiable. If true, counterexamples are generated and then translated to HDL testbenches by the Retrascope tool. The proposed approach was applied to several open source HDL benchmarks like Texas-97, Verilog2SMV, VCEGAR and mips16 modules. Potential conflicts have been detected for all of these benchmarks. Future work includes propagation of conflict assertions to the interface level (thus getting assertions on modules’ communication protocols) and generation of built-in HDL checkers.

A Flexible Framework for Exploring, Evaluating, and Comparing SHA-2 Designs

Hash functions are a crucial tool in a large variety of applications, ranging from security protocols to cryptocurrencies down to the Internet-of-Things devices used, for example, as biomedical appliances. In particular, SHA-2 is today a ubiquitous hashing primitive. Its acceleration has driven a wealth of contributions in the technical literature and even a whole industry segment involving dedicated hash processing accelerators. Because of the variety of requirements in terms of performance, resources, and energy consumption as well as the impact of the particular hardware technology of choice, evaluating and comparing different architectural schemes is a nontrivial task, along with the exploration of new solutions matching given user requirements. Based on a careful review of the state of the art, this paper introduces an SHA-2 workbench to be used as a framework for evaluating different implementation styles and architectural choices. The workbench comes in the form of a generic HDL description, where the various implementation options are exposed in the form of user-configurable parameters and can be variously combined obtaining either known solutions or possibly new configurations to be explored. We systematically use the workbench to analyze the available SHA-2 architectural techniques. This extensive evaluation provides a deep understanding of the performance and energy implications of each implementation style and even allows the identification of nonobvious matches between architectural choices and target technologies in order to optimize hash rate and area efficiency figures.

A Fast Wire-Routing Method and an Automatic Layout Tool for RSFQ Digital Circuits Considering Wire-Length Matching

A fast wire-routing method considering wire-length matching of passive transmission lines (PTLs) is proposed. The method deals with channel routing between adjacent columns of active devices, and generates paths of PTLs with specified additional length packed in compact area based on simulated annealing. It uses a generation method of paths from a sequence of symbols for searching solutions efficiently. An automatic layout tool is also shown. It consists of a placer and a router based on the proposed method. The placer uses total extension length of PTLs for length matching as one of the evaluation metrics for detailed placement using simulated annealing. By introducing this metric, total extension length in routing phase is reduced and compact layouts are obtained. Using the tool, design flow from HDL descriptions to layout generation can be established. As an experimental result, a layout of an adder designed by the tool is shown.

FPGA based hardware and device-independent implementation of chaotic generators

In this paper we will describe the use of Matlab/Simulink without third party toolboxes as a single integrated environment to study and generate the HDL description of chaotic systems for rapid prototyping purposes. We will provide a review of different approaches to implement chaos generators in both analog and digital forms with a focus on digital one. We will present a rapid prototyping method of digital chaos generators on FPGAs that is of great use for a seamless study, simulation and implementation of those systems in one environment. This will ease the design phase of the chaotic systems and will provide more flexibility for their study. Multiple chaos generators, such as Lorenz, Rössler, Chua, Linz-Sprott, and Sprott types have been designed using this method to showcase its effectiveness. In addition, for a better investigation of the chaotic dynamics, this work makes use of an implementation scheme that permits the visualization of the 3D chaotic attractor on the oscilloscope. The main focus of this paper is to provide a common implementation framework of chaos generators to target various applications, mainly cryptographic one. Newcomers to the field will easily dive in and active researchers will be able to speak the same language and build upon one anothers works more efficiently by adopting the presented guidelines.

Генерация тестов для цифровой аппаратуры на основе высокоуровневых моделей

Hardware testing is a process aimed at detecting manufacturing faults in integrated circuits. To measure test quality, two main metrics are in use: fault detection abilities (fault coverage) and test application time (test length). Many algorithms have been suggested for test generation; however, no scalable solution exists. In this paper, we analyze applicability of functional tests generated from high-level models for low-level manufacturing testing. A particular test generation method is considered. The input information is an HDL description. The key steps of the method are system model construction and coverage model construction. Both models are automatically extracted from the given description. The system model is a representation of the design in the form of high-level decision diagrams. The coverage model is a set of LTL formulae defining reachability conditions for the transitions of the extended finite state machine. The models are translated into the input format of a model checker. For each coverage model formula the model checker generates a counterexample, i.e. an execution that violates the formula (makes the corresponding transition to fire). The approach is intended for covering of all possible execution paths of the input HDL description and detecting dead code. Experimental comparison with the existing analogues has shown that it produces shorter tests, but they achieve lower stuck-at fault coverage comparing with the dedicated approach. An improvement has been proposed to overcome the issue.

A Flexible FPGA-Based Quasi-Cyclic LDPC Decoder

Low-density parity check (LDPC) error correction decoders have become popular in diverse communications systems, owing to their strong error correction performance and their suitability to parallel hardware implementation. A great deal of research effort has been invested into the implementation of LDPC decoder designs on field-programmable gate array (FPGA) devices, in order to exploit their high processing speed, parallelism, and re-programmability. Meanwhile, a variety of application-specific integrated circuit implementations of multi-mode LDPC decoders exhibiting both inter-standard and intra-standard reconfiguration flexibility are available in the open literature. However, the high complexity of the adaptable routing and processing elements that are required by a flexible LDPC decoder has resulted in a lack of viable FPGA-based implementations. Hence in this paper, we propose a parameterisable FPGA-based LDPC decoder architecture, which supports run-time flexibility over any set of one or more quasi-cyclic LDPC codes. Additionally, we propose an off-line design flow, which may be used to automatically generate an optimized HDL description of our decoder, having support for a chosen selection of codes. Our implementation results show that the proposed architecture achieves a high level of design-time and run-time flexibility, whilst maintaining a reasonable processing throughput, hardware resource requirement, and error correction performance.

Flexible architectures for retinal blood vessel segmentation in high-resolution fundus images

Blood vessel segmentation from high-resolution fundus images is a necessary step in several retinal pathologies detection. Automatic blood vessel segmentation is a computing-intensive task, which raises the need for acceleration with hardware architectures. In this paper, we propose two architectures for blood vessel segmentation using a matched filter (MF). The first architecture is a scalable hardware architecture, while the second one is an application-specific instruction-set processor. An efficient, real-time hardware implementation of the algorithm is made possible through parallel processing and efficient resource sharing. A tool for the automatic generation of particularized HDL descriptions of the architecture is proposed. The tool starts from a common architecture template and takes as input the parameters of the MF. A designer thus gains a significant amount of flexibility and productivity with the parameter selection problem and the evaluation of corresponding implementations. Several designs were verified and implemented on an FPGA platform. Performance in terms of area utilization and maximum frequency are reported. The results show significant improvement over state-of-the-art implementations, by up to a factor of 14? for high-resolution fundus images. The second architecture is based on the Tensilica Xtensa LX processor. With only two additional custom instructions requiring an additional 4? the area of the basic processor, the ASIP achieves a significant speedup of 7.76? when compared to the basic processor, while retaining all its flexibility.

Application specific instruction set processor for sensor conditioning in automotive applications

In the automotive electronic market, sensor conditioning is one of the driving applications. Sensor solutions are pervasive in the vehicle, while signal processing in such application is getting more and more complex. Currently the design strategy is often the standard ASIC flow, but the design effort can be reduced by automatic or platform-aided design strategies, or by using software-based solutions. In this paper SensASIP platform is presented. It is a design platform targeting a microprocessor architecture enhanced by dedicated instructions for computing intensive sensor signal processing tasks. SensASIP allows a seamless design flow from MATLAB-based algorithm definition and instruction set design and simulation, down to hardware macrocell HDL description and implementation in CMOS technology. SensASIP features are described through two automotive sensor conditioning examples. Special focus is put on its increased flexibility and reduced design-effort vs. standard ASIC design approach and on its low complexity overhead vs. other state-of-art software-based solutions.

RunFein: a rapid prototyping framework for Feistel and SPN-based block ciphers

Block ciphers are the most prominent symmetric-key cryptography kernels, serving as fundamental building blocks to many other cryptographic functions. This work presents RunFein, a tool for rapid prototyping of a major class of block ciphers, namely product ciphers (including Feistel network and Substitution permutation network-based block ciphers). RunFein accepts the algorithmic configuration of an existing/new block cipher from the user through a GUI to generate a customized software implementation. The user may choose from various micro-architectural templates (unrolled, pipelined, sub-pipelined) to generate an HDL description of the cipher. Various modes of operation and the NIST test suite may also be included. This high-level design approach eliminates the laborious and repetitive development efforts for VLSI realizations of block ciphers. It allows a quick design exploration, consequently enabling fast benchmarking in terms of critical resource estimation of various versions/configurations of a cipher that varies in terms of security, complexity and performance. Using RunFein, we have successfully implemented some well-known product ciphers and benchmarked their performance without significant degradation against their published hand-crafted implementations in literature.

TCONMAP

Parameterised configurations are FPGA configuration bitstreams in which the bits are defined as functions of user-defined parameters. From a parameterised configuration, it is possible to quickly and efficiently derive specialised, regular configuration bitstreams by evaluating these functions. The specialised bitstreams have different properties and functionality depending on the chosen values of the parameters. The most important application of parameterised configurations is the generation of specialised configuration bitstreams for Dynamic Circuit Specialisation, a technique for optimising circuits at runtime using partial reconfiguration of the FPGA. Generating and using parameterised configurations requires a new FPGA tool flow. In this article, we present a new technology mapping algorithm for parameterised designs, called TCONMAP, that can be used to produce parameterised configurations in which both the configuration of the logic blocks and routing is a function of the parameters. In our experiments, we demonstrate that in using TCONMAP, the depth and area of the mapped circuit is close to the minimal depth and area attainable. Both Dynamic Circuit Specialisation and fine-grained modular reconfiguration are extracted by TCONMAP from the HDL description of the design requiring only simple parameter annotations.

VHDL Implementation of Robust WI-FI Positioning System

Design of a cost effective and accurate positioning of a wireless device is one of the challenging issues in Wireless Local Area Networks (WLANs). In this paper we present a novel positioning system by utilizing WLAN received signal strength measurements. The technique includes two parts; First, distance estimation using received signal strength indication (RSSI) using polynomial fitting method. Second, simplified and accurate geometric location algorithm (GLA) is proposed. The proposed technique is less complex and easy to implement. The technique not requires any extra hardware and offline training. This location algorithm is designed and tested in MATLAB tool and described using Very high speed integrated circuit Hardware Description Language (VHDL), synthesized in XILINX ISE 10.1 and simulated in ISE simulator. Novelty of the HDL description is that, IEEE754 floating point representation is used, which increases the accuracy.

A Method of Extended Finite State Machines Construction from HDL Descriptions Based on Static Analysis of Source Code

A Method of Extended Finite State Machines Construction from HDL Descriptions Based on Static Analysis of Source Code

Tracing Fault Effects in FPGA Systems

Abstract The paper presents the extent of fault effects in FPGA based systems and concentrates on transient faults (induced by single event upsets - SEUs) within the configuration memory of FPGA. An original method of detailed analysis of fault effect propagation is presented. It is targeted at microprocessor based FPGA systems using the developed fault injection technique. The fault injection is performed at HDL description level of the microprocessor using special simulators and developed supplementary programs. The proposed methodology is illustrated for soft PicoBlaze microprocessor running 3 programs. The presented results reveal some problems with fault handling at the software level.

An automatic energy consumption characterization of processors using ArchC

The design complexity of integrated circuits requires techniques that automate and ease common tasks, allowing developers to keep up with the rapid growth and demand of the industry. This paper presents acSynth, an integrated framework for development and synthesis based on ArchC ADL descriptions and introduces a new power characterization method at the architectural level. The acSynth is composed of a characterization tool used to extract the energy consumption behavior of processors and also of a simulation method that, after characterization, is able to estimate software energy consumption at high speeds. Our experimental results show the power figures obtained by the characterization flow of Plasma and Leon3 processors, a MIPS-I and SPARCv8 HDL descriptions, respectively, using two different synthesis tools: Xilinx Xpower and Altera PowerPlay. The acSynth simulator used these power figures to allow power analysis at more than 35 million instructions per second in a simulation with small accuracy diversion and without loss of generality. The system executes large tests in minutes, which would otherwise take years in standard HDL methodologies.

The evolution of MEMS and modelling methodologies

PurposeThe purpose of this paper is to show the evolution of microsystems together with modeling methods in the space of dozen years as a result of finished research in the frame of several projects.Design/methodology/approachIn this paper several approaches are presented. First, microsystems were built in multi project wafer technology. They were demonstrators like micromotor, micromirrors or micropumps modeled using dedicated design tool. A multi purpose chip was also designed using HDL description and FEM simulations. The next project concerned chemical sensors, where specialized models were developed and implemented in VHDL‐AMS in order to perform multidomain behavioral simulations. Dedicated tools were also developed for medical applications.FindingsThe evolution of MEMS technology is strictly connected with simulation and modeling methods. The success and short time to market need fast and accurate simulation methods. This paper shows that the approach depends on application. Moreover, it is connected with the access to the technology.Originality/valueThis paper presents a brief overview on projects performed in DMCS‐TUL department. It shows the evolution of modeling methods and technology used in developing and fabrication of microsystems for various applications.