Abstract
Data access conflicts may arise in hardware designs. One of the ways of detecting such conflicts is static analysis of hardware descriptions in HDL. We propose a static analysis-based approach to data conflicts extraction from HDL descriptions. This approach has been implemented in the Retrascope tool. The following types of conflicts are considered: simultaneous reads and writes, simultaneous writes, reading of uninitialized data, no reads between two writes. Conflict assertions are formulated as conditions on variables. HDL descriptions are automatically translated into formal models suitable for the nuXmv model checker. The translation process consists of the following steps: 1) preliminary processing; 2) Control Flow Graph (CFG) building; 3) CFG transformation into a Guarded Actions Decision Diagram (GADD); 4) GADD translation into a nuXmv format. Conflict assertions are automatically built using static analysis of the GADD model and passed to the nuXmv model checker. Bounded model checking is used to check whether these assertions are satisfiable. If true, counterexamples are generated and then translated to HDL testbenches by the Retrascope tool. The proposed approach was applied to several open source HDL benchmarks like Texas-97, Verilog2SMV, VCEGAR and mips16 modules. Potential conflicts have been detected for all of these benchmarks. Future work includes propagation of conflict assertions to the interface level (thus getting assertions on modules’ communication protocols) and generation of built-in HDL checkers.
Highlights
Modern hardware designs contain multiple modules and processes operating on the common set of internal variables
In [3], a GoldMine methodology is presented for automatic generation of hardware assertions
We propose a new approach to data access conflicts extraction in HDL descriptions
Summary
Modern hardware designs contain multiple modules and processes operating on the common set of internal variables. In this case conflicts, i.e. illegal accesses from different processes to the same data, may appear. Requirements on how to operate with modules and avoid conflicts in a communication protocol can be described both in formal (machine-readable) and informal (humanreadable) ways. The idea is to analyze an HDL description aimed at finding data access conflicts [1]. Both the conflicts and the target description are automatically translated into the input format of a model checking tool. Труды ИСП РАН, том 31, вып. 3, 2019 г., стр. 135-144
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