Hardware Utilization Efficiency Research Articles

Maximizing RAG efficiency: A comparative analysis of RAG methods

Abstract This paper addresses the optimization of retrieval-augmented generation (RAG) processes by exploring various methodologies, including advanced RAG methods. The research, driven by the need to enhance RAG processes as highlighted by recent studies, involved a grid-search optimization of 23,625 iterations. We evaluated multiple RAG methods across different vectorstores, embedding models, and large language models, using cross-domain datasets and contextual compression filters. The findings emphasize the importance of balancing context quality with similarity-based ranking methods, as well as understanding tradeoffs between similarity scores, token usage, runtime, and hardware utilization. Additionally, contextual compression filters were found to be crucial for efficient hardware utilization and reduced token consumption, despite the evident impacts on similarity scores, which may be acceptable depending on specific use cases and RAG methods.

Design of Universal Code Generator for Multi-Constellation Multi-Frequency GNSS Receiver

A multi-constellation, multi-frequency Global Navigation Satellite System (GNSS) receiver is capable of simultaneously receiving signals from multiple satellite constellations across various frequency bands. This allows for increased observations, thereby enhancing navigation accuracy, continuity, effectiveness, and reliability. The spread spectrum code structures used in satellite navigation signals differ among systems. Compatible code generators are employed in multi-constellation, multi-frequency GNSS receivers to support tasks such as signal acquisition and tracking. There are three main types of spread spectrum code structures: Linear Feedback Shift Register (LFSR), Legendre sequences, and Memory codes. The Indian Regional Navigation Satellite System (IRNSS) released the L1-SPS (Standard Positioning Service) signal format in August 2023, which utilizes the Interleaved Z4-linear ranging code (IZ4 code) as its spread spectrum code. Currently, there is no universal code generator design compatible with the IZ4 code. In this paper, a proposed universal code generator is based on the hardware structure of the IRNSS IZ4 code generator. It achieves compatibility with all LFSR-based spread spectrum codes and enables parallel generation of multiple sets of GNSS signal spread spectrum codes, thereby improving hardware utilization efficiency. The proposed structure is implemented and validated using FPGA design, and resource consumption is provided as part of the validation results.

FOM-CDS PUF: A Novel Configurable Dual State Strong PUF Based on Feedback Obfuscation Mechanism against Modeling Attacks

The configurable Ring oscillator Physical unclonable function (CRO PUF) is the newly proposed strong PUF based on classic RO PUF, which can generate exponential Challenge-Response Pairs (CRPs) and has good uniqueness and reliability. However, existing proposals have low hardware utilization and vulnerability to modeling attacks. In this paper, we propose a Novel Configurable Dual State (CDS) PUF with lower overhead and higher resistance to modeling attacks. This structure can be flexibly transformed into RO PUF and TERO PUF in the same topology according to the parity of the Hamming Weight (HW) of the challenge, which can achieve 100% utilization of the inverters and improve the efficiency of hardware utilization. A feedback obfuscation mechanism (FOM) is also proposed, which uses the stable count value of the ring oscillator in the PUF as the updated mask to confuse and hide the original challenge, significantly improving the effect of resisting modeling attacks. The proposed FOM-CDS PUF is analyzed by building a mathematical model and finally implemented on Xilinx Artix-7 FPGA, the test results show that the FOM-CDS PUF can effectively resist several popular modeling attack methods and the prediction accuracy is below 60%. Meanwhile it shows that the FOM-CDS PUF has good performance with uniformity, Bit Error Rate at different temperatures, Bit Error Rate at different voltages and uniqueness of 53.68%, 7.91%, 5.64% and 50.33% respectively.

A High-Performance Dual-Context MQ Encoder Architecture Based on Extended Lookup Table

Multiple quantization (MQ) encoder is a basic entropy encoder widely used in multimedia encoding systems, especially in JPEG2000 and JBIG2, which play a key role and make outstanding contributions to digital imaging. However, due to its strict serial working characteristics, the MQ encoder has become a key bottleneck restricting the optimization of JPEG2000 encoding performance. Many single ejection encoder architectures use pipeline staging to improve the throughput, but they have all reached their limits. A high-performance MQ encoder based on a novel lookup table is proposed to overcome this bottleneck, which improves the throughput while utilizing reasonable hardware resources and with low-power consumption. Experimental results show that the proposed encoder architecture can encode two symbols per cycle with a throughput of 1204.82 MSymbol/s, and it has a power consumption of only 11.05 mW. Compared with the conventional multi-context coder, the hardware utilization is reduced by 26%, and the hardware utilization efficiency is improved by 16%. Compared with the conventional single-context coder, the throughput is improved by 14.3%, and the power consumption is reduced by 40.1%.

Real-Time CRLB Based Antenna Selection in Planar Antenna Arrays

Estimation of User Terminals’ (UTs’) Angle of Arrival (AoA) plays a significant role in the next generation of wireless systems. Due to high demands, energy efficiency concerns, and scarcity of available resources, it is pivotal how these resources are used. Installed antennas and their corresponding hardware at the Base Station (BS) are of these resources. In this paper, we address the problem of antenna selection to minimize Cramer-Rao Lower Bound (CRLB) of a planar antenna array when fewer antennas than total available antennas have to be used for a UT. First, the optimal antenna selection strategy to minimize the expected CRLB is proposed. Then, using this strategy as a preliminary step, we present a two-stage greedy antenna selection method whose goal is to minimize the instantaneous CRLB. The optimal start point of the greedy algorithm is presented alongside some methods to reduce the algorithm’s computational complexity. Numerical results confirm the accuracy of proposed solutions. They demonstrate that the proposed antenna selection method only requires a small proportion of the total available antennas to accomplish a significant amount of the total performance, enhancing hardware utilization efficiency. Also, it is shown that the presented algorithm has a high error tolerance.

A Reconfigurable CNN-Based Accelerator Design for Fast and Energy-Efficient Object Detection System on Mobile FPGA

In limited-resource edge computing circumstances such as on mobile devices, IoT devices, and electric vehicles, the energy-efficient optimized convolutional neural network (CNN) accelerator implemented on mobile Field Programmable Gate Array (FPGA) is becoming more attractive due to its high accuracy and scalability. In recent days, mobile FPGAs such as the Xilinx PYNQ-Z1/Z2 and Ultra96, definitely have the advantage of scalability and flexibility for the implementation of deep learning algorithm-based object detection applications. It is also suitable for battery-powered systems, especially for drones and electric vehicles, to achieve energy efficiency in terms of power consumption and size aspect. However, it has the low and limited performance to achieve real-time processing. In this article, optimizing the accelerator design flow in the register-transfer level (RTL) will be introduced to achieve fast programming speed by applying low-power techniques on FPGA accelerator implementation. In general, most accelerator optimization techniques are conducted on the system level on the FPGA. In this article, we propose the reconfigurable accelerator design for a CNN-based object detection system on the register-transfer level on mobile FPGA. Furthermore, we present RTL optimization design techniques that will be applied such as various types of clock gating techniques to eliminate residual signals and to deactivate the unnecessarily active block. Based on the analysis of the CNN-based object detection architecture, we analyze and classify the common computing operation components from the Convolutional Neuron Network, such as multipliers and adders. We implement a multiplier/adder unit to a universal computing unit and modularize it to be suitable for a hierarchical structure of RTL code. The proposed system design was tested with Resnet-20 which has 23 layers and it was trained with the dataset, CIFAR-10 which provides a test set of 10,000 images in several formats, and the weight data we used for this experiment was provided from Tensil. Experimental results show that the proposed design process improves the power efficient consumption, hardware utilization, and throughput by 16%, up to 58%, and 15%, respectively.

Configurable Independent Component Analysis Preprocessing Accelerator

An independent component analysis (ICA) has been used in many applications, including self-interference cancellation (SIC) for in-band full-duplex (IBFD) wireless systems and anomaly detection in industrial Internet of Things (IoT). This article presents a high-throughput and highly efficient configurable preprocessing accelerator for the ICA algorithm. The proposed ICA accelerator has three major blocks that perform data centering, covariance matrix for computation, and eigenvalue decomposition (EVD). Specifically, the proposed accelerator is based on a high-performance matrix multiplication array (MMA). The proposed MMA architecture uses time-multiplexed processing, so that the efficiency of hardware utilization is greatly enhanced. Furthermore, the processing flow utilizes parallel processing, such that the centering, the calculation of the covariance matrix, and the EVD are conducted simultaneously and are individually pipelined to maximize throughput. This article presents the architecture, circuit design, and performance estimates based on post-layout extraction of the proposed preprocessing ICA accelerator. The proposed design achieves a throughput of 40.7 kMatrices/s at a complexity of 73.3 kGE.

A Universal Efficient Circular-Shift Network for Reconfigurable Quasi-Cyclic LDPC Decoders

Quasi-cyclic low-density parity-check (QC-LDPC) codes for modern communication standards usually have multiple code rates and block lengths. Therefore, reconfigurable LDPC decoders have received widespread attention, which require circular-shift networks to support various expansion factors. Besides, for inputs smaller than the network size, the circular-shift network is desired to process multiple frames in parallel to maximize hardware utilization efficiency. The increasing demands put severe challenges to low-complexity implementations of shift networks, especially for codes with numerous expansion factors, such as 5G LDPC codes. In this brief, we present a universal design of efficient reconfigurable circular-shift networks. Through an ingenious modification on the order of permutations, the generation of control signals is considerably simplified, leading to a significant reduction of area and critical path. Moreover, a hybrid architecture organically integrating different networks is proposed for further complexity reduction. Implementation results under TSMC 90 nm technology demonstrate that the proposed network can achieve 25% area reduction and 46% area-efficiency (AE) improvement over the state-of-the-art ones.

Vertical Federated Edge Learning With Distributed Integrated Sensing and Communication

This letter studies a vertical federated edge learning (FEEL) system for collaborative objects/human motion recognition by exploiting the distributed integrated sensing and communication (ISAC). In this system, distributed edge devices first send wireless signals to sense targeted objects/human, and then exchange intermediate computed vectors (instead of raw sensing data) for collaborative recognition while preserving data privacy. To boost the spectrum and hardware utilization efficiency for FEEL, we exploit ISAC for both target sensing and data exchange, by employing dedicated frequency-modulated continuous-wave (FMCW) signals at each edge device. Under this setup, we propose a vertical FEEL scheme for realizing the recognition based on the collected multi-view wireless sensing data. In this scheme, each edge device owns an individual local L-model to transform its sensing data into an intermediate vector with relatively low dimensions, which is then transmitted to a coordinating edge device for final output via a common downstream S-model. By considering a human motion recognition task, experimental results show that our vertical FEEL based approach achieves recognition accuracy up to 98% with an improvement up to 8% compared to the benchmarks, including on-device training and horizontal FEEL.

Massively parallel data analytics for smart grid applications

Complexity involved in operating modern power and energy systems is constantly increasing given the volatility induced by the rapid integration of intermittent renewable energy sources. In order to operate the power grid in secure and reliable way, a plethora of uncertain parameters need to be considered and hundreds of thousands of different power grid scenarios need to be rapidly evaluated. This works analyzes the computational aspects in massively parallel simulations from the perspective of efficient hardware utilization. A method for efficiently managing and processing the computational tasks is presented, carefully considering the level of parallelism in order to avoid computational bottlenecks and efficiently utilizing modern multicore architectures with deep memory hierarchies. An extensive set of numerical experiments is presented, considering multiple aspects of the computational pipeline. The numerical experiments are performed using mathematical models typically used in the power grid problems, including linear and quadratic programs as well as the models containing the discrete variables. The optimized high-throughput computation strategy has been shown to significantly reduce response times by preventing the memory bottlenecks for various computational models.

FPGA Implementation of Reconfigurable CORDIC Algorithm and a Memristive Chaotic System With Transcendental Nonlinearities

Coordinate Rotation Digital Computer (CORDIC) is a robust iterative algorithm that computes many transcendental mathematical functions. This paper proposes a reconfigurable CORDIC hardware design and FPGA realization that includes all possible configurations of the CORDIC algorithm. The proposed architecture is introduced in two approaches: multiplier-less and single multiplier approaches, each with its advantages. Compared to recent related works, the proposed implementation overpasses them in the included number of configurations. Additionally, it demonstrates efficient hardware utilization and suitability for potential applications. Furthermore, the proposed design is applied to a memristive chaotic system with different transcendental functions computed using the proposed reconfigurable block. The memristive system design is realized on the Artix-7 FPGA board, yielding throughputs of 0.4483 and 0.3972 Gbit/s for the two approaches of reconfigurable CORDIC.

FPGA realization of fractals based on a new generalized complex logistic map

This paper introduces a new generalized complex logistic map and the FPGA realization of a corresponding fractal generation application. The chaotic properties of the proposed map are studied through the stability conditions, bifurcation behavior and maximum Lyapunov exponent (MLE). A relation between the mathematical analysis and fractal behavior is demonstrated, which enables formulating the fractal limits. A compact fractal generation process is presented, which results in designing and implementing an optimized hardware architecture. An efficient FPGA implementation of the fractal behavior is validated experimentally on Artix-7 FPGA board. Two examples of fractal implementation are verified, yielding frequencies of 34.593MHz and 31.979MHz and throughputs of 0.415 Gbit/s, 0.384 Gbit/s. Compared to recent related works, the proposed implementation demonstrates its efficient hardware utilization and suitability for potential applications.

A Resource-Efficient Convolutional Neural Network Accelerator Using Fine-Grained Logarithmic Quantization

Convolutional Neural Network (ConNN) implementations on Field Programmable Gate Array (FPGA) are being studied since the computational capabilities of FPGA have been improved recently. Model compression is required to enable ConNN deployment on resource-constrained FPGA devices. Logarithmic quantization is one of the efficient compression methods that can compress a model to very low bit-width without significant deterioration in performance. It is also hardware-friendly by using bitwise operations for multiplication. However, the logarithmic suffers from low resolution at high inputs due to exponential properties. Therefore, we propose a modified logarithmic quantization method with a fine resolution to compress a neural network model. In experiments, quantized models achieve a negligible loss of accuracy without the need for retraining steps. Besides this, we propose a resource-efficient hardware accelerator for running ConNN inference. Our design completely eliminates multipliers with bit shifters and adders. Throughput is measured in Giga Operation Per Second (GOP/s). The hardware utilization efficiency is represented by GOP/s per block of Digital Signal Processing (DSP) and Look-up Tables (LUTs). The result shows that the accelerator achieves resource efficiency of 9.38 GOP/s/DSP and 3.33 GOP/s/kLUTs.

High performance modified bit-vector based packet classification module on low-cost FPGA

The packet classification plays a significant role in many network systems, which requires the incoming packets to be categorized into different flows and must take specific actions as per functional and application requirements. The network system speed is continuously increasing, so the demand for the packet classifier also increased. Also, the packet classifier's complexity is increased further due to multiple fields should match against a large number of rules. In this manuscript, an efficient and high performance modified bitvector (MBV) based packet classification (PC) is designed and implemented on low-cost Artix-7 FPGA. The proposed MBV based PC employs pipelined architecture, which offers low latency and high throughput for PC. The MBV based PC utilizes <2% slices, operating at 493.102 MHz, and consumes 0.1 W total power on Artix-7 FPGA. The proposed PC considers only 4 clock cycles to classify the incoming packets and provides 74.95 Gbps throughput. The comparative results in terms of hardware utilization and performance efficiency of proposed work with existing similar PC approaches are analyzed with better constraints improvement.

Data Visualization in Cloud Service for Scientific Computations

The saas.jinr.ru service is an attempt to simplify the usage of the JINR Multifunctional Information and Computing Complex (MICC) of the Joint Institute for Nuclear Research (JINR). It aims at providing a simple problem-oriented web-interface to help students and beginner researchers in the physics domain to abstract away the complexity of the computing infrastructure and to focus on the actual research. In this paper we show our approach to one of the problems within the scope of the project: interactive data visualization in a web-browser. When approaching this problem, we considered two major requirements to the system: first, users may not have any programming skills, so any interaction should be performed using simple visual components; second, the system must be horizontally scalable to cope with irregular user work-sessions. The paper describes how we used Bokeh and Dask for integrating our data visualization solution within the Django framework to deal with the first requirement, and the JINR cloud for service scaling. Application of cloud technologies facilitates dynamic distribution of workload across virtual machines, thus making it possible for us to control the balance between efficient hardware utilization and end-user experience. Shared in this work resulting software architecture and applied solutions, as well as some performance considerations, can be used as an example when designing other cloud-native scientific applications.

Reconfigurable FPGA Realization of Fractional-Order Chaotic Systems

This paper proposes FPGA realization of an IP core for generic fractional-order derivative based on Grünwald-Letnikov approximation. This generic design is applied to achieve reconfigurable realization of fractional-order chaotic systems. The fractional-order real-time configuration boosts the suitability of this particular realization for different applications, including dynamic switching, synchronization, and encryption. The proposed design targets optimized utilization of the FPGA internal resources and efficient employment of the external peripherals: switches and I/O ports in the FPGA board. The digital design of the fractional-order dependent terms: binomial coefficients and power function is proposed. Three approximations of the power function using curve fitting are compared, settling on the quadratic approximation that balances accuracy and efficiency. Three fractional-order chaotic systems: Liu, Li and Chen four-wing, are verified for both commensurate and incommensurate orders cases, using one approach for the commensurate order case and two approaches for the incommensurate order case. The reconfigurable design is realized on the Artix-7 FPGA board, yielding throughputs of 1.1266, 1.1266, and 1.434 Gbit/s for both commensurate and incommensurate orders cases of the three systems, respectively. Compared to recent related works, the proposed implementation demonstrates its efficient hardware utilization and suitability for potential applications.

CyExec*: A High-Performance Container-Based Cyber Range With Scenario Randomization

With increasing threats to information security, information security education through practical exercises specifically cyber range has attracted attention. However, the use of a cyber range is not widespread because of the high initial and maintenance cost and difficulty of developing new scenarios. Because many virtual instances are executed in the cyber range, the advantage of container type virtualization, which can provide a lightweight execution environment, is expected to increase efficient hardware utilization and decrease the total cost. On the other hand, containers pose challenges in scalability and scenario development when it comes to their use in cyber ranges because their performance advantages and vulnerability reproducibility have not been reported. In this paper, we conducted an exhaustive experiment to compare the performance and reproducibility of container-type virtualization with other virtualization types. The results show that containers can provide a more efficient execution environment than the other types, with almost perfect vulnerability reproducibility of more than 99% while reducing memory consumption by half and storage consumption to 1/60. The container's high performance and reproducibility enabled us to develop CyExec*, a cyber range system with DAG-based scenario randomization technology. CyExec* can increase educational effectiveness by automatically generating multiple scenarios with the same learning objective. Compared with a random scenario generator for CTF using another virtualization type, CyExec* shows more than three times higher performance. CyExec* can solve existing cyber range issues.

Comparison of Swarm Optimization and Memetic Algorithm for Systolic Mapping of Texture Analysis

Systolic processors offer a hardware design which can accommodate more functions in a small footprint. Hardware utilization efficiency can be enhanced by appropriately designating the intended hardware with a task in space and time through parallel computing platforms. Regular algorithms known for their computational complexity can be mapped to systolic array by dependence graphs, which allot hardware to the design data. Manual mapping techniques tend to be tedious with more inaccuracy and calls for efficient mapping techniques, automated through algorithmic procedures. Texture Analysis marks the preliminary progression of image analysis and interpretation. Automotive systems, Robotics, Industrial processing and similar automated applications can be simplified through texture analysis. This work deals with employing evolutionary algorithms for mapping texture analysis onto systolic architecture. Memetic Algorithms (MA) and Particle Swarm Optimization (PSO) algorithms were comparatively studied and the efficiency of designing a parallel architecture through systolic array is analyzed through cost function and processing time.

A Precision-Scalable Energy-Efficient Convolutional Neural Network Accelerator

Quantization is a promising technique to compress the size of Convolutional Neural Network (CNN) models. Recently, various precision-scalable designs have been presented to reduce the computational complexity in CNNs. However, most of them adopt straightforward calculation scheme to implement the CNN, which causes high bandwidth requirement and low hardware utilization efficiency. This paper proposes a new precision-scalable architecture which can fully reduce the computational complexity in CNN inference and meanwhile has a finely simplified calculation scheme. Based on the proposed scheme, a well-optimized multiplier called Compositional Processing Element (C-PE) is devised. Compared with the previous multipliers, the new C-PE requires less area and power. Furthermore, two levels of optimization are introduced to the design to relieve the bandwidth problem and increase the hardware utilization efficiency. Implemented under the TSMC 90nm CMOS technology, the whole design achieves 6-68.1 fps in various precisions on VGG16 benchmark and a 49.8TOPS/W energy efficiency at 500MHz when scaled to 28nm, which is much better than previous precision-scalable ones.

Flexible High Throughput QC-LDPC Decoder With Perfect Pipeline Conflicts Resolution and Efficient Hardware Utilization

Modern communication standards, such as 5G new radio (5G NR), require a high speed decoder for highly irregular quasi-cyclic low density parity check (QC-LDPC) codes. A widely used approach in QC-LDPC decoders is a layered decoding schedule which processes the parity check matrix in parts, thus providing faster convergence. However, pipelined layered decoding architecture suffers from data hazards that reduce the throughput. This paper presents a novel architecture, which can facilitate any QC-LDPC decoding without stall cycles caused by pipeline hazards. The decoder conveniently incorporates both the layered and the flooding schedules in cases when hazards occur. The paper also presents the genetic algorithm based optimization of the decoding schedule for better signal-to-noise ratio (SNR) performance. The proposed architecture enables insertion of a large number of pipeline stages, thus providing high operating frequency. As a case study, the FPGA implementation for WiMAX, DVB-S2X, and 5G NR provided coded throughput of up to 1.77 Gbps, 4.32 Gbps, and 4.92 Gbps at 10 iterations, respectively. The results show a strong throughput increase of 30%–109% compared with the conventional layered decoder for 5G NR for the same SNR performance. The decoder provides highly efficient utilization of resources when compared with the state-of-the-art solutions.