A Resource-Efficient Convolutional Neural Network Accelerator Using Fine-Grained Logarithmic Quantization

Hadee Madadum,Yasar Becerikli

doi:10.32604/iasc.2022.023831

Hadee Madadum, Yasar Becerikli

Open Access

https://doi.org/10.32604/iasc.2022.023831

Copy DOI

Abstract

Convolutional Neural Network (ConNN) implementations on Field Programmable Gate Array (FPGA) are being studied since the computational capabilities of FPGA have been improved recently. Model compression is required to enable ConNN deployment on resource-constrained FPGA devices. Logarithmic quantization is one of the efficient compression methods that can compress a model to very low bit-width without significant deterioration in performance. It is also hardware-friendly by using bitwise operations for multiplication. However, the logarithmic suffers from low resolution at high inputs due to exponential properties. Therefore, we propose a modified logarithmic quantization method with a fine resolution to compress a neural network model. In experiments, quantized models achieve a negligible loss of accuracy without the need for retraining steps. Besides this, we propose a resource-efficient hardware accelerator for running ConNN inference. Our design completely eliminates multipliers with bit shifters and adders. Throughput is measured in Giga Operation Per Second (GOP/s). The hardware utilization efficiency is represented by GOP/s per block of Digital Signal Processing (DSP) and Look-up Tables (LUTs). The result shows that the accelerator achieves resource efficiency of 9.38 GOP/s/DSP and 3.33 GOP/s/kLUTs.

Highlights

Edge devices such as low-end Field Programmable Gate Array (FPGA) have limited resources, but Convolutional Neural Network (ConNN) models require large amounts of multipliers and extensive storage [1]
The hardware utilization efficiency is represented by Giga Operation Per Second (GOP/s) per block of Digital Signal Processing (DSP) and Look-up Tables (LUTs)
Resource utilization is challenging in deploying the ConNN model to FPGA devices

Summary

Introduction

Edge devices such as low-end FPGA have limited resources, but ConNN models require large amounts of multipliers and extensive storage [1]. ConNN models can be transformed from 32-bit to lower precision, for example 8-bits [2], binary-bits [3] or fixed-point format [4]. A resource efficiency can be improved by replacing the complexity of multiplication with bitwise operations such as XNOR-Net [5,6] This approach is mostly used in previous work to map a 32-bit floating-point to a lower bit-width such as binary, ternary, and fixed-point formats. This method is uniform quantization which the quantization levels are spaced. Increasing the bit-width linearly increases the number of quantization level and gives a higher resolution It requires more memory space, and the cost of computation is expensive. On the other hand, using the lower bit-width takes less memory but the accuracy degradation is a trade-off

Objectives

Methods

Conclusion