Hardware Supported Research Articles

An efficient hardware supported and parallelization architecture for intelligent systems to overcome speculative overheads

In the last few decades, technology advancements have paved the way for the creation of intelligent and autonomous systems that utilize complex calculations which are both time-consuming and central processing unit intensive. As a consequence, parallel processing systems are gaining popularity to enhance overall computer performance. Programmers should be able to efficiently utilize available hardware resources with parallelization in an ideal world. Through the automatic parallelization of sequential code, multithreading can be executed without extra supervision. However, a wide range of software dependencies prevents this from being feasible. An architectural framework for speculative parallelization along with an efficient memory analysis and computational algorithms for the code generation are proposed that can provide optimal performance. Furthermore, a suitable support of hardware design as a runtime library to the proposed architectural framework is presented which can be used to recover misspeculated results during execution to minimize speculative parallelism overhead. The implementation makes use of the Low-Level Virtual Machine compiler infrastructure and is tested on numerous benchmarks, thus making it highly scalable in terms of programming languages and architectures. According to our experimental results, there is significant potential for speedup increase. In comparison to the overall function speedup, that is, geomean speedup of 5.2× approximately when using the proposed architecture without hardware support, the proposed architectural framework and algorithm with hardware support give an average geomean speedup of 7.0× approximately on the given benchmark which is written in C/C++.

Improving applications performance

This paper presents a memory model and architecture for synchronization of threads or tasks when accessing regions of virtual memory. Access control is defined on a memory region through a view that defines the size of access units and also the protocol in terms of a Finite State Machine (FSM). The size of access units, although fixed within a view, can vary across views and is thus customizable to applications. Variable-sized access units are obtained without altering the underlying fixed sized paging implementation. By defining access control through FSM definitions, any protocol that is decomposable into a set of states and can be expressed using an FSM can be supported.A cache-based architecture of the Protection Control Unit (PCU), which decides whether a read/write memory access to an access unit of a region/view can proceed or leads to a fault, is presented. The PCU is not invoked on each read/write memory access, but only on data cache misses and write access faults. The cache-based architecture forms flexible hardware support for access control in that by loading the caches with definitions of different FSM, different protocols can be supported. Furthermore, by providing for hardware supported changes in state of access through state transitions, frequency of context switching is reduced.Trace-driven simulation is used to examine the delay in the memory hierarchy due to inclusion of the caches in the PCU unit, and to examine delay in the memory hierarchy for a conventional software implementation of the same access control protocol. A TPC-C benchmark application under different transaction loads was traced and the results show that it is the number of TLB accesses (approximately 15 times more as compared to PCU accesses) for the modeled application that incurs the dominant delay, as compared to delay in the PCU memory hierarchy.

On hardware support for interval computations and for soft computing: theorems

This paper presents a rationale for providing hardware supported functions of more than two variables for processing incomplete knowledge and fuzzy knowledge. The result is in contrast to Kolmogorov's (1957) theorem in the numerical (nonfuzzy) case.

Hardware support for memory protection

This paper is intended to stimulate discussion on the present state of hardware supported capability systems. Interest in such systems grew up in the mid-1960's and since that time information has been published on several different versions. In the opinion of some observers, the software complexity of these systems outweighs the advantage gained. The paper surveys the situation, and endeavors to set out the general features that a hardware supported capability system should possess. An attempt is made to identify the causes of the complexity and to make recommendations for removing them. The arguments for and against the tagging of capabilities are discussed and attention is drawn to a system of semi-tagging previously proposed by the author.

Hardware support for memory protection

This paper is intended to stimulate discussion on the present state of hardware supported capability systems. Interest in such systems grew up in the mid-1960's and since that time information has been published on several different versions. In the opinion of some observers, the software complexity of these systems outweighs the advantage gained. The paper surveys the situation, and endeavors to set out the general features that a hardware supported capability system should possess. An attempt is made to identify the causes of the complexity and to make recommendations for removing them. The arguments for and against the tagging of capabilities are discussed and attention is drawn to a system of semi-tagging previously proposed by the author.