Hardware-software Partitioning Research Articles

Analysis of Program Representations Based on Abstract Syntax Trees and Higher-Order Markov Chains for Source Code Classification Task

In this paper we consider the research and development of classifiers that are trained to predict the task solved by source code. Possible applications of such task detection algorithms include method name prediction, hardware–software partitioning, programming standard violation detection, and semantic code duplication search. We provide the comparative analysis of modern approaches to source code transformation into vector-based representations that extend the variety of classification and clustering algorithms that can be used for intelligent source code analysis. These approaches include word2vec, code2vec, first-order and second-order Markov chains constructed from abstract syntax trees (AST), histograms of assembly language instruction opcodes, and histograms of AST node types. The vectors obtained with the forementioned approaches are then used to train such classification algorithms as k-nearest neighbor (KNN), support vector machine (SVM), random forest (RF), and multilayer perceptron (MLP). The obtained results show that the use of program vectors based on first-order AST-based Markov chains with an RF-based classifier leads to the highest accuracy, precision, recall, and F1 score. Increasing the order of Markov chains considerably increases the dimensionality of a vector, without any improvements in classifier quality, so we assume that first-order Markov chains are best suitable for real world applications. Additionally, the experimental study shows that first-order AST-based Markov chains are least sensitive to the used classification algorithm.

Hardware Software Co-Design for Impact Localization using Hybrid Laminates

Impact detection using piezoelectric sensors is an actual and widespread research field. The current work provides an approach for a real-time realization of an impact detection system using deep learning methods. For realization a hardware software co-design approach is used utilizing hardware acceleration by a continuous pipelining FPGA structure. The concept describes the hardware software partitioning of the underlying functions and the methodology for ensuring continuous data processing and the associated real-time capability. The behavior of the hardware is realized with the help of a finite state machine and thus the correctness of the data is ensured and the impact identification is realized. The results show the real-time capability as well as a reasonable resource utilization of the FPGA design.

Specific Electronic Platform to Test the Influence of Hypervisors on the Performance of Embedded Systems

Some complex digital circuits must host various operating systems in a single electronic platform to make real-time and not-real-time tasks compatible or assign different priorities to current applications. For this purpose, some hardware–software techniques—called virtualization—must be integrated to run the operating systems independently, as isolated in different processors: virtual machines. These are monitored and managed by a software tool named hypervisor, which is in charge of allowing each operating system to take control of the hardware resources. Therefore, the hypervisor determines the effectiveness of the system when reacting to events. To measure, estimate or compare the performance of different ways to configure the virtualization, our research team has designed and implemented a specific testbench: an electronic system, based on a complex System on Chip with a processing system and programmable logic, to configure the hardware–software partition and show merit figures, to evaluate the performance of the different options, a field that has received insufficient attention so far. In this way, the fabric of the Field Programmable Gate Array (FPGA) can be exploited for measurements and instrumentation. The platform has been validated with two hypervisors, Xen and Jailhouse, in a multiprocessor System-on-Chip, by executing real-time operating systems and application programs in different contexts.

Hardware-software partitioning using three-level hybrid algorithm for system-on-chip platform

This study discusses hardware-software partitioning, which is useful for system-on-chip (SoC) applications. Hardware-software partitioning attempts to obtain the lowest execution time by combining a hardware processor system and a field programmable gate array on the SoC platform in embedded system applications. A three-level hybrid algorithm called GAGAPSO is proposed in this study. The algorithm consists of two successive genetic algorithms (GAs) and one particle swarm optimization (PSO). The drawbacks of these two algorithms are GA has low convergence speed and PSO has premature convergence because of low diversity. These algorithms are combined in this study to achieve high-capacity global convergence and enhanced search efficiency. In this study, three algorithms are developed, namely, GA, GAPSO and GAGAPSO using MATLAB. These algorithms are evaluated on the basis of the number of nodes and the minimum cost that can be achieved. The number of nodes varies from 10 to 1000 nodes. The minimum cost and the number of iterations to achieve the minimum cost are recorded. Results show that GAGAPSO can converge faster than GA and GAPSO. Furthermore, GAGAPSO can achieve the lowest cost for all nodes.

FSA: A Fine-Grained Systolic Accelerator for Sparse CNNs

Sparsity, as an intrinsic property of convolutional neural networks (CNNs), has been widely employed for hardware acceleration, and many customized accelerators tailored for sparse weights or activations have been proposed in these years. However, the irregular sparse patterns introduced by both weights and activations are much more challenging for efficient computation. For example, due to the issues of access contention, workload imbalance, and tile fragmentation, the state-of-the-art sparse accelerator SCNN fails to fully leverage the benefits of sparsity, leading to nonoptimal results for both speedup and energy efficiency. In this article, we propose an efficient sparse CNN accelerator for both weights and activations, namely finegrained systolic accelerator (FSA), which jointly optimizes both hardware dataflow and software partitioning and scheduling strategy. Specifically, to deal with the access contentions problem, we present a fine-grained systolic dataflow, in which the activations move rhythmically along the horizontal processing element array while the weights are fed into the array in a fine-grained order. We then propose a hybrid network partitioning strategy that sets different partitioning strategies for different layers to balance the workload and alleviate the fragmentation problem caused by both sparse weights and activations. Finally, we present a scheduling search strategy to find the optimized schedules for neural networks, which can further improve energy efficiency. Extensive evaluations show that the proposed FSA consistently outperforms SCNN over AlexNet, VGGNet, GoogLeNet, and ResNet with an average speedup of 1.74× and up to 13.86× energy efficiency.

Heuristic algorithms for multi-criteria hardware/software partitioning in embedded systems codesign

The Codesign is a powerful methodology adopted in designing modern embedded systems. The objective of this methodology is to optimize some non-functional factors of the system while meeting its functional specifications. Partitioning the system into a hardware set and a software set (Hardware/Software Partitioning (HSP)) is a key step in this process of Codesign. In this paper, we propose two heuristic approaches to deal with the HSP problem, taking into consideration three metrics: hardware cost, execution time and power consumption. The goal is to minimize one metric yet respecting the constraints on the two other metrics. The first approach uses a combination of the Lagrangian Relaxation (LR) with the Subgradient methods; the second approach combines the LR method with the 0–1 Knapsack Algorithm and the Genetic Algorithm. In order to validate the effectiveness of the two proposed approaches, this paper gives a comparison with the Simulated Annealing algorithm and the Genetic algorithm.

GO Game Inspired Algorithm for Hardware Software Partitioning in Multiprocessor Embedded Systems

The codesign is a robust methodology, used in modern embedded systems with the objective of achieving the functional specifications and meeting the non-functional requirements. The most interesting step in the codesing  is the process of  Hardware/Software Partitioning. The aim is to decide which functionalities of the system should be implemented in hardware ($HW$) or in software ($SW$). In this article, a new heuristic algorithm is proposed to simultaneously optimize the hardware area (cost) and the execution time (performance) of a multiprocessor system. The proposed algorithm is inspired from game theory and especially from the GO game. The system is modeled using the DAG graph (Data Acyclic Graph), and two players (HW player and SW player) play in turn and choose a block (functionality) from the graph (system). The HW player has the goal of optimizing the global HW area while the SW player has the objective of minimizing the global execution time. After the game termination, and based on the 0-1 Knapsack algorithm, a step of refinement is used to meet the constraint on the total hardware area or on the overall execution time if a constraint is pre-defined. Experimental results show that the proposed algorithm gives better solutions compared to the Simulated Annealing algorithm and the Genetic Algorithm.

High-level optimised systems design using hardware-software partitioning

Embedded systems have a wide range as they have become essential parts of modern life. A typical embedded system consists of application-specific hardware and programmable software. Hardware-software (HW/SW) partitioning problem defines which tasks should be mapped to software and hardware. It allows the proposition of an optimised system with predefined constraints. In this paper, a heuristic algorithm, the hybrid-bee-colony-optimisation for multiple-choice HW/SW partitioning is proposed. The proposed algorithm aims to minimise power consumption and execution time, while meeting area constraint. This heuristic algorithm is developed to generate an approximate solution in acceptable delay. The Virtex 5 is chosen as a target platform. Simulation results are compared with existing works and they show rapidity with the generation of an optimal solution near to the exact one.

High-level optimised systems design using hardware-software partitioning

High-level optimised systems design using hardware-software partitioning

PGMA: An algorithmic approach for multi-objective hardware software partitioning

Designing embedded systems efficiently has always been of significant interest. This has been tremendously scaled-up for contemporary and high-end applications with their increasing complexity and the need to satisfy multiple conflicting constraints. This paper presents a high-speed Hardware Software Partitioning technique for the design of such systems. The partitioning problem has been modeled as a multi-dimensional optimization problem with the aim of minimizing the area utilization, power dissipation, time of execution and system memory requirement of the implementation. A two-phased algorithm (Phased Greedy Metaheuristic Algorithm or PGMA) has been proposed which also takes into consideration the communication costs between hardware and software Processing-Engines (PEs) while partitioning. Subsequently, a detailed empirical analysis of the proposed algorithm is presented to ascertain its efficiency, quality and speed. The execution time is as low as 18 ms for partitioning an algorithm consisting of 1000 blocks. Thereafter, the proposed algorithm is applied to a real-life embedded system, the Joint Photographic Expert-Group (JPEG) Encoder, to demonstrate its effectiveness. For a power constraint of 600 mW, an area utilization of 58.28% has been achieved, which is the maximum amongst all the reported works till date, to the best of our knowledge. This allowed for a decreased offloading of tasks to software, resulting in a memory usage of only 14 KB and execution time of 20 ms.

A metaheuristic based on the tabu search for hardware-software partitioning

Several metaheuristics have become increasingly interesting in solving combinatorial problems. In this paper, we present an algorithm involving a metaheuristic based on tabu search and binary search trees to address the problem of hardware-software partitioning. Metaheuristics do not guarantee an optimum solution, but they can produce acceptable solutions in a reasonable time. Our proposed algorithm seeks to find the efficient hardware-software partitioning that minimizes the logic area of a system on a programmable chip under the condition of time constraints. Our goal is to have a better trade-off between the logic area of the application and its execution time. Finally, we compare our algorithm to some metaheuristic-based algorithms.

Power and Execution Time Optimization through Hardware Software Partitioning Algorithm for Core Based Embedded System

Shortening the marketing cycle of the product and accelerating its development efficiency have become a vital concern in the field of embedded system design. Therefore, hardware/software partitioning has become one of the mainstream technologies of embedded system development since it affects the overall system performance. Given today’s largest requirement for great efficiency necessarily accompanied by high speed, our new algorithm presents the best version that can meet such unpreceded levels. In fact, we describe in this paper an algorithm that is based on HW/SW partitioning which aims to find the best tradeoff between power and latency of a system taking into consideration the dark silicon problem. Moreover, it has been tested and has shown its efficiency compared to other existing heuristic well-known algorithms which are Simulated Annealing, Tabu search, and Genetic algorithms.

Multi-core model checking and maximum satisfiability applied to hardware-software partitioning

Bounded model checking (BMC) based on satisfiability modulo theories (SMT) is well-known by its capability to verify software. However, its use as optimisation tool, to solve hardware and software (HW-SW) partitioning problems, is something new. In particular, its integration with the maximum satisfiability solver vZ tool, which provides a portfolio of approaches for solving linear optimisation problems over SMT formulas, is unprecedented. We present new alternative approaches to solve the HW-SW partitioning problem. First, we use SMT-based BMC in conjunction with a multi-core support using open multi-processing to create four variants to solve the partitioning problem. The multi-core SMT-based BMC approaches allow initialising many verification instances based on the number of available processing cores, where each instance checks a different optimum value until the optimisation problem is satisfied. Additionally, we integrate the vZ into the BMC, making it a specialised solution for optimisation in a single-core environment. We implement all five approaches on top of the efficient SMT-based context-bounded model checker (ESBMC) and compare them to a state-of-the-art optimisation tool. Experimental results show that there is no single optimisation tool to solve all HW-SW partitioning benchmarks, but based on medium-size benchmarks, ESBMC-vZ had better performance.

Multi-core model checking and maximum satisfiability applied to hardware-software partitioning

Bounded model checking (BMC) based on satisfiability modulo theories (SMT) is well-known by its capability to verify software. However, its use as optimisation tool, to solve hardware and software (HW-SW) partitioning problems, is something new. In particular, its integration with the maximum satisfiability solver vZ tool, which provides a portfolio of approaches for solving linear optimisation problems over SMT formulas, is unprecedented. We present new alternative approaches to solve the HW-SW partitioning problem. First, we use SMT-based BMC in conjunction with a multi-core support using open multi-processing to create four variants to solve the partitioning problem. The multi-core SMT-based BMC approaches allow initialising many verification instances based on the number of available processing cores, where each instance checks a different optimum value until the optimisation problem is satisfied. Additionally, we integrate the vZ into the BMC, making it a specialised solution for optimisation in a single-core environment. We implement all five approaches on top of the efficient SMT-based context-bounded model checker (ESBMC) and compare them to a state-of-the-art optimisation tool. Experimental results show that there is no single optimisation tool to solve all HW-SW partitioning benchmarks, but based on medium-size benchmarks, ESBMC-vZ had better performance.

Research and Medical Transcranial Doppler System

Abstract A new ultrasound digital transcranial Doppler system (digiTDS) is introduced. The digiTDS enables diagnosis of intracranial vessels which are rather difficult to penetrate for standard systems. The device can display a color map of flow velocities (in time-depth domain) and a spectrogram of a Doppler signal obtained at particular depth. The system offers a multigate processing which allows to display a number of spectrograms simultaneously and to reconstruct a flow velocity profile. The digital signal processing in digiTDS is partitioned between hardware and software parts. The hardware part (based on FPGA) executes a signal demodulation and reduces data stream. The software part (PC) performs the Doppler processing and display tasks. The hardware-software partitioning allowed to build a flexible Doppler platform at a relatively low cost. The digiTDS design fulfills all necessary medical standards being a new useful tool in the transcranial field as well as in heart velocimetry research.

Hardware/Software Partitioning for Heterogenous MPSoC Considering Communication Overhead

Hardware/software partitioning (HSP) is an important step in the co-design of hardware/software. This paper addresses the problem of HSP with communication (HSPC) on heterogeneous multiprocessor system-on-chip (MPSoC). The classic HSP is modeled as an optimization problem with an objective of minimizing the finishing time in system under the hardware area constraints. First, we put forward an optimal method, integer linear programming (ILP) algorithm, for solving the problem for small inputs. Then, we propose two other algorithms using dynamic programming (DP) method, i.e., Optimal Tree Partitioning (OTP) method for tree-structured graphs and Tree Cover Partitioning (TCP) algorithm for general graphs in polynomial time. The overall performance of the proposed algorithms is evaluated through comparisons with that of a genetic algorithm (GA) and a greedy algorithm which are commonly used to solve HSP problem. We have conducted experimental performance evaluation on various benchmarks with different combinations of computation to communication ratios and hardware area constraints. The experimental results show that OTP algorithm can generate optimal solutions with much faster speed than ILP, and TCP algorithm can obtain near-optimum with higher quality than those produced by GA and greedy algorithm.

Algorithms for bi-objective multiple-choice hardware/software partitioning

This paper proposes three algorithms for multiple-choice hardware-software partitioning with the objectives of minimizing execution time and power consumption, while meeting area constraint. Firstly, a heuristic algorithm is proposed to rapidly generate an approximate solution. In the second algorithm we refined the approximate solution using a customized tabu search algorithm. Finally, a dynamic programming algorithm is proposed to calculate the exact solution. Simulation results show that the approximate solution is very close to the exact solution. This can be further refined by tabu search to achieve a solution with less than 1.5% error for all cases considered in this paper.

Combined Partitioning Hardware-Software Algorithms

In recent years, meta-heuristics have become increasingly interesting in solving combinatorial problems including hardware-software partitioning. In this paper, we present a comparative study between some algorithms which involve meta-heuristics based on Tabu search, genetic algorithm and Binary Search Trees to address the problem of hardwaresoftware partitioning. In fact, meta-heuristics can produce acceptable solutions within a reasonable time, but they do not guarantee an optimal solution. We have proposed these algorithms to find the efficient hardware-software partition that minimizes the logic area of System on a Programmable Chip while respecting a time constraint. This paper presents an analysis of these meta-heuristics by identifying the fundamental ideas guiding the choice of a meta-heuristic in practice.

Hardware software partitioning of control data flow graph on system on programmable chip

A System On Programmable Chip (SOPC) is a circuit that integrates all components of an electronic system into a single chip. It may consist of memories, one or more microprocessors, interface devices, configurable logic blocks and other necessary components to achieve an intended function. In this paper, we propose a new hardware–software partitioning algorithm of control data flow graph for SOPC. The main aim of our algorithm is to find a best compromise between hardware and software implementation of operations in order to satisfy design constraints in terms of latency and hardware resources of the target application. Our algorithm has been evaluated on real hardware device. In fact, experimentations have been done using a real FPGA Virtex-5. Results have shown that our algorithm provides a better performing system with the lowest possible cost compared to existing approaches.

A Modified Inertial Method for Loop-free Decomposition of Acyclic Directed Graphs

Abstract Graph decomposition is a key process in system-level synthesis, even if it is used for allocation (e.g. hardware-software partitioning) or simple decomposition as a preprocessing step (e.g. for pipelining). Acyclic graphs are usually desirable in the design processes, thus preserving the acyclicity during decomposition is crucial. We propose a modified inertial decomposition to create loop-free decomposition results. We assign coordinates to the nodes based on their maximal distance from the inputs, and give an algorithm that finds the required number of cuts in polynomial time while balancing the size of segments and looking for minimal number of edges along cuts.