Hardware-software Co-simulation Research Articles

Hardware software co-simulation of a digital EMI filter using Xilinx system generator

Hardware software co-simulation of a digital EMI filter using Xilinx system generator

Hardware–Software Co-Design Framework for Data Encryption in Image Processing Systems for the Internet of Things Environment

Data protection is a severe constraint in the heterogeneous IoT era. This article presents a Hardware-Software Co-Simulation of AES-128 bit encryption and decryption for IoT Edge devices using the Xilinx System Generator (XSG). VHDL implementation of AES-128 bit algorithm is done with ECB and CTR mode using loop unrolled and FSM-based architecture. It is found that AES-CTR and FSM architecture performance is better than loop unrolled architecture with lesser power consumption and area. For performing the Hardware-Software Co-Simulation on Zedboard and Kintex-Ultra scale KCU105 Evaluation Platform, Xilinx Vivado 2016.2 and MATLAB 2015b is used. Hardware emulation is done for grey images successfully. To give a practical example of the usage of proposed framework, we have applied it for Biomedical Images (CTScan Image) as a case study. Security analysis in terms of the histogram, correlation, information entropy analysis, and keyspace analysis using exhaustive search and key sensitivity tests is also done to encrypt and decrypt images successfully.

Implementation of image copyright protection tool using hardware-software co-simulation

The proposed work presents particulars of a technique for the design and hardware implementation of an information hiding scheme using hardware-software co-simulation. The methodology aims to improve the design verification efficiency, development time and cost for DSP solutions. The scheme represents architecture for visual information hiding framework where information bits embedded into the host image by means of LSB matching technique. The design is tested by targeting a Spartan-3A DSP edition board (XC3SD3400A-4FGG676C) and the simulated results illustrate that this architecture provides a better opening for application specific events as well as explores different areas concerned to low cost hardware implementation through a graphical user interface.

Derivative-Free Direct Search Optimization Method for Enhancing Performance of Analytical Design Approach-Based Digital Controller for Switching Regulator

Although an analytical design approach-based digital controller—which is essentially a deadbeat controller—shows zero steady-state error and no intersampling oscillations, it takes a finite number of sampling periods to settle down to a steady-state value. This paper describes the application of a derivative-free Nelder–Mead (N–M) simplex method to the digital controller for retuning of its coefficients intelligently to ensure improved settling and rise times without disturbing the deadbeat controller characteristics (i.e., no ripples between the sampling periods and no steady-state error). A switching-mode buck regulator working at 1 MHz in continuous conduction mode (CCM) is considered as a plant. Numerical simulation results depict that the N–M algorithm-based optimized digital controller not only shows improved steady-state and transient performance but also guarantees rigorous robustness against model uncertainty and disturbance as compared to its traditional counterpart, as well as the other optimized digital controller fine-tuned through other derivative-free metaheuristic optimization techniques, such as the genetic algorithm (GA). A system generator-based hardware software co-simulation is also performed to validate the simulation results.

Hyperchaos and Coexisting Attractors in a Modified van der Pol–Duffing Oscillator

This paper deals with a new modified hyperchaotic van der Pol–Duffing (MVPD) snap oscillator. Various dynamical properties of the proposed system are investigated with the help of Lyapunov exponents, stability analysis of the equilibrium points and bifurcation plots. The existence of the Hopf bifurcation is established by analyzing the corresponding characteristic equation. It is also proved that the MVPD oscillator shows multistability with coexisting attractors. Various numerical simulations are conducted and presented to show the dynamical behavior of the MVPD system. To show that the system is hardware realizable, we derive the discrete model of the MVPD system using the Euler’s method and using the hardware–software cosimulation, the proposed MVPD system is implemented in Field Programmable Gate Arrays. It is shown that the output of the digital implementations of the MVPD systems matches the numerical analysis.

A family of conservative chaotic systems with cyclic symmetry

In this paper, we propose a family of circulant systems with conservative property. Various dynamical properties of the circulant systems are derived and investigated. Bifurcation plots are derived and presented for a system and the Lyapunov exponents are derived to show the existence of chaotic oscillations, and their sum being zero confirms the conservativeness for certain values of parameters. One of the proposed systems is then implemented in field programmable gate array (FPGA) to show the hardware reliability. We used the hardware–software co-simulation to see the phase portraits of the FPGA implemented system. The discrete integrators required for solving the initial value problem are implemented using the Euler’s method. The register transfer level schematics of the FPGA implemented system and the resources used for the implementations are presented.

Time-delayed chameleon: Analysis, synchronization and FPGA implementation

In this paper we report a time-delayed chameleon-like chaotic system which can belong to different families of chaotic attractors depending on the choices of parameters. Such a characteristic of self-excited and hidden chaotic flows in a simple 3D system with time delay has not been reported earlier. Dynamic analysis of the proposed time-delayed systems are analysed in time-delay space and parameter space. A novel adaptive modified functional projective lag synchronization algorithm is derived for synchronizing identical time-delayed chameleon systems with uncertain parameters. The proposed time-delayed systems and the synchronization algorithm with controllers and parameter estimates are then implemented in FPGA using hardware–software co-simulation and the results are presented.

FIELD PROGRAMMABLE GATE ARRAY IMPLEMENTATION OF A VARIABLE LEAKY LEAST MEAN SQUARE ADAPTIVE ALGORITHM

Adaptive noise cancellation is an extensively researched area of signal processing. Many algorithms had been studied such as least mean square algorithm (LMS), recursive least square algorithm, and normalized LMS algorithm. The statistical characteristics of noise are fast in nature and the algorithms for noise cancellation should converge fast. Since LMS algorithm has slow convergence; in this paper, a variable leaky LMS (VLLMS) algorithm is explored. VLLMS is implemented using the concept of hardware-software cosimulation using Xilinx System Generator. The design is implemented on Virtex-6 ML605 field programmable gate array board. The implemented design is tested for sinusoidal signal added with an additivewhite Gaussian noise. The design summary and the utilization summary are presented.

Emulation-Based Analysis of System-on-Chip Performance Under Variations

The scaling of integrated circuits into the nanometer regime has led to variations emerging as a primary design concern. Most efforts in the area of variation-tolerant design have focused on the physical, circuit, and logic levels of abstraction. However, inevitable increases in the magnitude of variations with scaling have elevated them to a design concern that must be addressed starting at the system level. We address the problem of analyzing the performance of system-on-chip (SoC) architectures in the presence of variations. A modern SoC is a complex ensemble of components that are organized into multiple voltage and frequency domains or islands. The impact of variations on the clock frequencies of individual SoC components may be analyzed using existing tools, such as circuit-level statistical timing analysis. However, the key challenge that needs to be addressed is how to translate these component-level clock frequency distributions into a system-level performance distribution. This task is particularly complex and challenging due to the interdependences between components’ execution, indirect effects of shared resources, and interactions between multiple system-level execution paths. We argue that an accurate variation-aware performance analysis requires Monte Carlo-based repeated system execution. We describe a framework variability emulation for SoC performance analysis (VESPA)—that leverages emulation to significantly speed up the performance analysis without sacrificing the generality and accuracy achieved by Monte Carlo-based simulation. We further improve the efficiency of VESPA by utilizing correlated sampling to reduce the number of samples needed for Monte Carlo simulations. We demonstrate the utility of VESPA by applying it to design variation-tolerant architectures for three example SoCs. Our experiments show the performance improvements of $\sim 180\times $ compared with the state-of-the-art hardware–software cosimulation tools and also underscore the potential of VESPA to enable variation-aware design and exploration at the system level.

Real-time hand gesture recognition in FPGA

Hand Gesture has been used in different applications and also implemented on different platforms. A faster and smooth approach with reasonable accuracy is always needed to make smart devices smarter and faster. This paper describes a novel procedure of hand gesture recognition using Principal Component Analysis (PCA) implemented in FPGA Simulator. The simulation was done using co-simulation tool of Simulink with Xilinx System Generator (XSG). Hardware-Software co-simulation is a good methodology which assures accurate and rapid prototyping leading to faster simulation times for heterogeneous systems design. Total processing time for the designed hardware was found to be 530ns using FPGA having the operating frequency of 100MHz.

Real Time Hardware Co - Simulation for Image Processing Algorithms Using Xilinx System Generator

The implementation of digital image processing required detailed knowledge of both hardware design and hardware description languages. This paper presents an efficient approach for the implementation of real time hardware digital image processing algorithms without requiring detailed knowledge of hardware design and hardware description languages. The purpose of this work is to achieve a real time hardware implementation with higher performance in both size and speed. It focuses on the implementation of an efficient architecture for image processing algorithms like segmentation (threshold) and contrast stretching by using the fewest possible system generator blocks for DSP tool, which integrates itself with the MATLAB based Simulink graphics environment and relieves the user of the textual HDL programming. While Past research has shown that the Image enhancement techniques on FPGA based on the Xilinx System Generator. This study connect between image histogram and Image enhancement techniques depending on the type of enhancement required. This paper describes also the methodology for implementing real-time DSP applications on FPGA and concept of hardware software co-simulation for digital image processing by using the Mathworks model-based design tool Simulink / Xilinx System Generator (XSG). Performances of efficient architectures are implemented on FPGA Virtex5 (XUPV5-LX110T).

FPGA Based Design Implementation forDetection of Exudates Using XSG

A methodology for implementing DSP applications on Field programmable gate arrays employing Xilinx System Generator (XSG) is presented. This paper outlines efficient hardware architecture for detection of exudates in retinal images. The proposed design comprises architecture for Sobel and Prewitt edge detection algorithms. The egde map image obtained is enhanced for its perception using contrast stretching. Further the image is segmented to detect the exudates. This design has been implemented on Virtex-II Pro (xc2vp30-7ff896 platform). The code is synthesized within ISE 9.2 development suite. The results obtained via hardware software co-simulation use limited FPGA resources at higher maximum frequency.

Hardware Software Co-Simulation of Canny Edge Detection Algorithm

Edge detection is a method to detect presence of an object’s imagetypically this is identified by sharp changes in pixel density. We realized Canny Edge Detection Algorithm, the most optimal edge detector, in FPGA hardware utilizing Hardware-Software Co-Simulation with the help of Simulink (Mathworks) and System Generator (Xilinx). We explored and utilized different edge detection operators, in addition to Sobel, which is the typical such operator, for gradient calculation (the primary edge detection process). After comparative analysis, we found both Sobel and Robert operators among the best with hardware realization of Robert operator utilizing less resources (LUT & Flip-Flops). All the different versions of the algorithm was synthesized for Spartan-6 LX16 FPGAs from Xilinx. General Terms Edge Detection Algorithm, Canny Edge Detection, H/W Software Co-Simulation.

A Review on Implementation of Image Processing Algorithms using Hardware Software Co-simulation

Edge detection is necessary tool for extraction of information for further image processing operation. Many computer vision application use edge detectors as primary operators before high level image processing. Several algorithms are available for edge detection which makes use of derivative approach. Roberts, Prewitt , sobel, canny are some of the examples of edge detection methods. In this project edge detection algorithms are to be implemented over FPGA board. Proposed architecture gives an alternative by using a graphical user interface which is developed by combining MATLAB, Simulink and XSG tool. Prototype of Application Specific Integrated Circuit [ASIC] can be obtained by FPGA based implementation of edge detection algorithm. Comparative analysis using software and hardware is to be done. Instead of using traditional approach of programming FPGA, Xilinx System Generator [XSG] is used for programming and modeling FPGA. XSG has an integrated design flow to move directly to the bit stream file from simulink design environment which is necessary for programming the FPGA. Advantage of using FPGA is power efficient circuits can be fabricated; it has large memory and superior parallel computing capacity. With use of FPGA, design procedure becomes more flexible. Keywords— ASIC, FPGA,MATLAB ,Prewitt, Sobel, XSG. __________________________________________________*****_________________________________________________

Verification of Embedded System Designs through Hardware-Software Co-Simulation

This work proposes an environment for real- time testing of heterogeneous embedded systems through co- simulation. The verification occurs on real-time between the system software and hardware platform using the High Level Architecture (HLA) as a middleware between the hardware device and the simulated model. The novelty of this approach is not only providing support for simulations, but also allowing the synchronous integration with any physical hardware devices. In this paper we use the Ptolemy framework as a simulation platform. The integration of HLA with Ptolemy and the hardware models open a vast set of applications, like the test of many devices at the same time, running the same, or different applications or modules, the usage of Ptolemy for real-time control of embedded systems and the distributed execution of different embedded devices for performance improvement or collaborative execution. A case study is presented to prove the concept, showing the successful integration between the Ptolemy framework with an implementation using Atmel and ARM microcontrollers.

Hardware Software Co-Simulation of the Multiple Image Encryption Technique Using the Xilinx System Generator

Hardware-Software co-simulation of a multiple image encryption technique shall be described in this paper. Our proposed multiple image encryption technique is based on the Latin Square Image Cipher (LSIC). First, a carrier image that is based on the Latin Square is generated by using 256-bits of length key. The XOR operation is applied between an input image and the Latin Square Image to generate an encrypted image. Then, the XOR operation is applied between the encrypted image and the second input image to encrypt the second image. This process is continues until the nth input image is encrypted. We achieved hardware co-simulation of the proposed multiple image encryption technique by using the Xilinx System Generator (XSG). This encryption technique is modeled using Simulink and XSG Block set and synthesized onto Virtex 2 pro FPGA device. We validated our proposed technique by using the hardware software co-simulation method.

HW/SW Co-design of the Instrument Control Unit for the Energetic Particle Detector on-board Solar Orbiter

ESA’s medium-class Solar Orbiter mission is conceived to perform a close-up study of our Sun and its inner heliosphere to better understand the behaviour of our star. The mission will provide the clues to discover how the Sun creates and controls the solar wind and thereby affects the environments of all the planets. The spacecraft is equipped with a comprehensive suite of instruments. The Energetic Particle Detector (EPD) is one of the in-situ instruments on-board Solar Orbiter. EPD is composed of five different sensors, all of them sharing the Instrument Control Unit or ICU that is the sole interface with the spacecraft. This paper emphasises on how the hardware/software co-design approach can lead to a decrease in software complexity and highlights the versatility of the toolset that supports the development process. Following a model-driven engineering approach, these tools are capable of generating the high-level code of the software application, as well as of facilitating its configuration control and its deployment on the hardware platforms used in the different stages of the development process. Moreover, the use of the Leon2ViP virtual platform, with fault injection capabilities, allows an early software-before-hardware verification and validation and also a hardware–software co-simulation. The adopted solutions reduce development time without compromising the whole process reliability that is essential to the EPD success.

SystemC-based HW/SW co-simulation platform for system-on-chip (SoC) design space exploration

The development of digital designs today is much more complex than before, as they now impose more severe demands and require greater number of functionalities to be conceived. The current approach, based on the register transfer level (RTL) design methods, can result in extremely long simulation time compounded with time-consuming verification process. Hence, today digital system design begins with modelling at a higher level of design abstraction, that is, the electronic system level (ESL). This paper presents a hardware-software (HW/SW) co-simulation environment based on SystemC for application in the design of system-on-chip (SoC). We discuss the SystemC modelling of the hardware and the software parts of the system, and the interprocess communication module of the co-simulation platform. Its objective is to help designers obtain an appropriate HW/SW partitioning that satisfy specified area-speed design tradeoffs. Besides, an early system verification can also be carried out with a high simulation speed. A case study of a SoC implementing elliptic curve cryptography (ECC) is presented to validate the co-simulation platform in terms of system functionality verification and design space exploration.

Multi-carrier Receiver for Broadband Power Line Communications

This paper presents the design of a broadband power line communication (BPLC) receiver optimized for reduced hardware complexity. To this end, the Radio-Frequency (RF) stage uses a direct conversion architecture while some innovative solutions are used in the base-band signal processing, such as a new frequency offset synchronization scheme based on the frequency domain. Every part of the receiver has been optimized using a new non-commercial hardware-software co-simulation package named BROCOLI (Broadband Co-simulation Library) based on a set of hierarchical models, specially developed for this application. A prototype of the BPLC transceiver has been built and some experimental results are shown which validate the design process and the implemented solutions.

PeaCE

Existent hardware-software (HW-SW) codesign tools mainly focus on HW-SW cosimulation to build a virtual prototyping environment that enables software design and system verification without need of making a hardware prototype. Not only HW-SW cosimulation, but also HW-SW codesign methodology involves system specification, functional simulation, design-space exploration, and hardware-software cosynthesis. The PeaCE codesign environment is the first full-fledged HW-SW codesign environment that provides seamless codesign flow from functional simulation to system synthesis. Targeting for multimedia applications with real-time constraints, PeaCE specifies the system behavior with a heterogeneous composition of three models of computation and utilizes features of the formal models maximally during the whole design process. It is also a reconfigurable framework in the sense that third-party design tools can be integrated to build a customized tool chain. Experiments with industry-strength examples prove the viability of the proposed technique.