Hardware-software Codesign Methodology Research Articles

D-wash – A dynamic workload aware adaptive cache coherance protocol for multi-core processor system

In today's world, multi-processor plays the vital role in designing supercomputer, mobile phones and other wearable embedded systems. To handle power and latency issues in multicore processors, this paper proposes the workload aware adaptive cache coherence protocol in which works on the principle of the workload characterization that ranges from snooping to directory based mechanism. In this protocol, workload is characterized as low workloads and heavy workloads in which the snooping is adopted for heavy types whereas low workloads employs the directory protocol. The proposed protocol adapts dynamically cache coherence and its interconnection in the multi-processor adopting low latency and energy. For the evaluation different benchmarks such as IoMT (Internet of Medical Things) are utilized and implemented in Zync-SoC using hardware-software codesign methodology. Various parameters such as energy, latency and throughput are calculated and analyzed. Experimental results shows that the proposed protocol has achieved the 50% reduction in latency, 40% reduction in energy when compared with the other existing protocols.

Onboard Powerline Perception System for UAVs Using mmWave Radar and FPGA-Accelerated Vision

Autonomous Unmanned Aerial Vehicle (UAV) interactions with powerlines, such as close-up inspections for fault detection or grasping and landing for recharging, require advanced onboard perception capabilities. To solve such tasks, the UAV must be equipped with perception abilities that allow it to navigate between powerlines and safely approach specific cables of interest. A perception system with such capabilities requires state-of-the-art sensor technologies and data processing while still being subject to the limited hardware and energy resources of the UAV. In this paper, we present an advanced embedded system based on the cutting-edge Multiprocessing System-on-Chip (MPSoC) for onboard UAV powerline perception. Our platform consists of a mmWave radar and an RGB camera with data processing carried out on the MPSoC, covering both CPU and Field-Programmable Gate Array (FPGA) computations. Following hardware-software co-design methodology, the heavy image processing tasks are accelerated in the FPGA and fused with computationally light mmWave data on the CPU, facilitating pose-estimation of the power lines. Utilizing the open-source autonomy frameworks PX4 and ROS2, we demonstrate integration of the system with onboard path planning based on the estimated cable positions. The robustness of the detection and pose-estimation methods have been demonstrated in several tests performed both in simulated and real-world powerline environments. The results show that our proposed perception system allows the UAV to safely navigate in close proximity to powerlines, by perceiving more individual cables at longer distances compared to previous work, while remaining lightweight, power-efficient, and low-cost.

FPGA Implementation of Deep Leaning Model for Video Analytics

In recent years, deep neural networks have become a fascinating and influential research subject, and they play a critical role in video processing and analytics. Since, video analytics are predominantly hardware centric, exploration of implementing the deep neural networks in the hardware needs its brighter light of research. However, the computational complexity and resource constraints of deep neural networks are increasing exponentially by time. Convolutional neural networks are one of the most popular deep learning architecture especially for image classification and video analytics. But these algorithms need an efficient implement strategy for incorporating more real time computations in terms of handling the videos in the hardware. Field programmable Gate arrays (FPGA) is thought to be more advantageous in implementing the convolutional neural networks when compared to Graphics Processing Unit (GPU) in terms of energy efficient and low computational complexity. But still, an intelligent architecture is required for implementing the CNN in FPGA for processing the videos. This paper introduces a modern high-performance, energy-efficient Bat Pruned Ensembled Convolutional networks (BPEC-CNN) for processing the video in the hardware. The system integrates the Bat Evolutionary Pruned layers for CNN and implements the new shared Distributed Filtering Structures (DFS) for handing the filter layers in CNN with pipelined data-path in FPGA. In addition, the proposed system adopts the hardware-software co-design methodology for an energy efficiency and less computational complexity. The extensive experimentations are carried out using CASIA video datasets with ARTIX-7 FPGA boards (number) and various algorithms centric parameters such as accuracy, sensitivity, specificity and architecture centric parameters such as the power, area and throughput are analyzed. These results are then compared with the existing pruned CNN architectures such as CNN-Prunner in which the proposed architecture has been shown 25% better performance than the existing architectures.

A Compact Hardware Implementation of CCA-Secure Key Exchange Mechanism CRYSTALS-KYBER on FPGA

Post-quantum cryptosystems should be prepared before the advent of powerful quantum computers to ensure information secure in our daily life. In 2016 a post-quantum standardization contest was launched by National Institute of Standards and Technology (NIST), and there have been lots of works concentrating on evaluation of these candidate protocols, mainly in pure software or through hardware-software co-design methodology on different platforms. As the contest progresses to third round in July 2020 with only 7 finalists and 8 alternate candidates remained, more dedicated and specific hardware designs should be considered to illustrate the intrinsic property of a certain protocol and achieve better performance. To this end, we present a standalone hardware design of CRYSTALS-KYBER, amodule learning-with-errors (MLWE) based key exchange mechanism (KEM) protocol within the 7 finalists on FPGA platform. Through elaborate scheduling of sampling and number theoretic transform (NTT) related calculations, decent performance is achieved with limited hardware resources. The way that Encode/Decode and the tweaked Fujisaki-Okamoto transform are implemented is demonstrated in detail. Analysis about minimizing memory footprint is also given out. In summary, we realize the adaptive chosen ciphertext attack (CCA) secure Kyber with all selectable module dimension k on the smallest Xilinx Artix-7 device. Our design computes key-generation, encapsulation (encryption) and decapsulation (decryption and reencryption) phase in 3768/5079/6668 cycles when k = 2, 6316/7925/10049 cycles when k = 3, and 9380/11321/13908 cycles when k = 4, consuming 7412/6785 LUTs, 4644/3981 FFs, 2126/1899 slices, 2/2 DSPs and 3/3 BRAMs in server/client with 6.2/6.0 ns critical path delay, outperforming corresponding high level synthesis (HLS) based designs or hardware-software co-designs to a large extent.

Fully Integrated Analog Machine Learning Classifier Using Custom Activation Function for Low Resolution Image Classification

This paper presents fully-integrated analog neural network classifier architecture for low resolution image classification that eliminates memory access. We design custom activation functions using single-stage common-source amplifiers, and apply a hardware-software co-design methodology to incorporate knowledge of the custom activation functions into the training phase to achieve high accuracy. Performing all computations entirely in the analog domain eliminates energy cost associated with memory access and data movement. We demonstrate our classifier on multinomial classification task of recognizing down-sampled handwritten digits from MNIST dataset. Fabricated in 65nm CMOS process, the measured energy consumption for down-sampled MNIST dataset is 173pJ/classification, which is $3\times $ better than state-of-the-art. The prototype IC achieves mean classification accuracy of 81.3% even after down-sampling the original MNIST images by 96% from $28\times 28$ pixels to $5\times 5$ pixels.

A Fully-Integrated Analog Machine Learning Classifier for Breast Cancer Classification

We propose a fully integrated common-source amplifier based analog artificial neural network (ANN). The performance of the proposed ANN with a custom non-linear activation function is demonstrated on the breast cancer classification task. A hardware-software co-design methodology is adopted to ensure good matching between the software AI model and hardware prototype. A 65 nm prototype of the proposed ANN is fabricated and characterized. The prototype ANN achieves 97% classification accuracy when operating from a 1.1 V supply with an energy consumption of 160 fJ/classification. The prototype consumes 50 μ W power and occupies 0.003 mm 2 die area.

Hardware and software codesign methodology for implementing algorithms of person follower robotic system

Service sector is expecting more innovations in the field of robotics and automation due to manpower shortage, changes in society and increased level of affordability to the people. This paper presents development of an intelligent service robot to monitor activity of an elder person or differently abled person. In particular, this paper presents development of 'Person Follower Algorithms' and their implementation using hardware–software codesign methodology. This work also includes usage of adaptive neural network-based fuzzy inference system (ANFIS) for implementing a robotic task. The intelligent service robot is developed by integrating an IP camera with a NI single board rapid input output (sbRIO) which has steering ultrasonic sensor. The sbRIO is chosen to take the advantage of existing system and it is suitable for HW–software codesign. The efficacy of algorithms is validated by conducting a set of experiments in our research laboratory.

ACA-SDS: Adaptive Crypto Acceleration for Secure Data Storage in Big Data

In the era of big data, the demand for secure data storage is rapidly increasing. To accelerate the complex encryption computation, both specific instructions and hardware accelerators are adopted in a large number of scenarios. However, the hardware accelerators are not so effective especially for small volume data due to the induced invocation costs, while the AES-NI (Intel®advanced encryption standard new instructions) is not so energy efficiency for big data. To satisfy the diversity performance/energy requirements for intensive data encryptions, a collaborative solution is proposed in this paper. We proposed a feasible hardware-software co-design methodology based on the stack file system eCryptfs, with quick assist technology, which is named adaptive crypto acceleration for secure data storage (ACA-SDS). ACA-SDS is able to choose the optimal encryption solution dynamically according to file operation modes and request characters. Adjustable parameters, such as $\alpha $ , $\beta $ , and M are provided in our scheme to provide a better adaptability and tradeoff choices for encryption computation. Our evaluation shows that ACA-SDS can get 15%–25% performance improvement for big-data blocks compared with only software or hardware accelerations. Furthermore, our methodology provides a wide range of practical design concepts for the further research in this field.

Reconfigurable hardware-software codesign methodology for protein identification.

In this paper we propose an on-the-fly reconfigurable hardware-software codesign based reconfigurable solution for real-time protein identification. Reconfigurable string matching is performed in the disciplines of protein identification and biomarkers discovery. With the generation of plethora of sequenced data and number of biomarkers for several diseases, it is becoming necessary to have an accelerated processing and on-the-fly reconfigurable system design methodology to bring flexibility to its usage in the medical science community without the need of changing the entire hardware every time with the advent of new biomarker or protein. The proteome database of human at UniProtKB (Proteome ID up000005640) comprising of 42132 canonical and isoform proteins with variable database-size are used for testing the proposed design and the performance of the proposed system has been found to compare favorably with the state-of-the-art approaches with the additional advantage of real-time reconfigurability.

A New Parallel VLSI Architecture for Real-Time Electrical Capacitance Tomography

This paper presents a fixed-point reconfigurable parallel VLSI hardware architecture for real-time Electrical Capacitance Tomography (ECT). It is modular and consists of a front-end module which performs precise capacitance measurements in a time multiplexed manner using Capacitance to Digital Converter (CDC) technique. Another FPGA module performs the inverse steps of the tomography algorithm. A dual port built-in memory banks store the sensitivity matrix, the actual value of the capacitances, and the actual image. A two dimensional (2D) core multi-processing elements (PE) engine intercommunicates with these memory banks via parallel buses. A Hardware-software codesign methodology was conducted using commercially available tools in order to concurrently tune the algorithms and hardware parameters. Hence, the hardware was designed down to the bit-level in order to reduce both the hardware cost and power consumption, while satisfying real-time constraint. Quantization errors were assessed against the image quality and bit-level simulations demonstrate the correctness of the design. Further simulations indicate that the proposed architecture achieves a speed-up of up to three orders of magnitude over the software version when the reconstruction algorithm runs on 2.53 GHz-based Pentium processor or DSP Ti's Delphino TMS320F32837 processor. More specifically, a throughput of 17.241 Kframes/sec for both the Linear-Back Projection (LBP) and modified Landweber algorithms and 8.475 Kframes/sec for the Landweber algorithm with 200 iterations could be achieved. This performance was achieved using an array of [2 × 2] × [2 × 2] processing units. This satisfies the real-time constraint of many industrial applications. To the best of the authors’ knowledge, this is the first embedded system which explores the intrinsic parallelism which is available in modern FPGA for ECT tomography.

An ANP-Based Practical Quality Model for a Secure Embedded System with Sensor Network

The process of creating secure embedded systems with sensor network is highly challenging and complex, particularly from a technical viewpoint. A secure embedded system is used for a specific purpose and operation, and needs hardware-software codesign methodology. As such, there are many considerations in terms of system design when the system developer creates or constructs a secure embedded system with sensor network. However, there is a lack of research into quality models in the area of secure embedded systems in sensor network. This paper seeks to redress this issue by presenting a quality model for a secure embedded system with sensor network. Each quality for the secure embedded system is constructed according to DeLone and McLean's success information system, and has subcriteria according to their characteristics. The present research also focuses on making a quality model network which considers the correlation between the qualities' attributes.

HW/SW co-design of reconfigurable hardware-based genetic algorithm in FPGAs applicable to a variety of problems

This paper describes the implementation of a reconfigurable hardware-based genetic algorithm (HGA) accelerator using the hardware-software (HW/SW) co-design methodology. This HGA is coupled with a unique TRNG that extracts random jitters from a phase lock loop (PLL) to ensure proper GA operation. It is then applied and benchmarked with several case studies, which include the optimization of a simple fitness function, a constrained Michalewicz function, and the tuning of parameters in finger-vein biometrics. A HGA solution is necessary in systems that demand high performance during the optimization process. However, implementations that are completely designed in hardware will result in a very rigid architecture, making it difficult to reconfigure the system for use in different applications. This paper aims to solve this issue by proposing a HGA design that provides reconfigurability and flexibility by moving problem-dependent processes into software. The prototyping platform used is an Altera Stratix II EP2S60 FPGA prototyping board with a clock frequency of 50 MHz. The HW/SW co-design technique is applied, and system partitioning is done based on aspects such as system constraints, operational intensity, process sequencing, hardware logic utilization, and reconfigurability. Experimental results show that the proposed HGA outperforms equivalent software implementations compiled with an open-sourced C++ GA component library (GAlib) running on the same prototyping platform by 102 times at most. In the final case study, the application of the proposed HGA in tunable parameter optimization in finger-vein biometrics improved the matching rate, reducing the equal error rate (EER) value from 1.004% down to 0.101%.

Hardware-Software Codesign of an Embedded Multiple-Supply Power Management Unit for Multicore SoCs Using an Adaptive Global/Local Power Allocation and Processing Scheme

Power dissipation has become a critical design constraint for the growth of modern multicore systems due to increasing clock frequencies, leakage currents, and system parasitics. To overcome this urgent crisis, this article presents an embedded platform for on-chip power management of a multicore System-on-Chip (SoC). The design involves the development of two key components, from the hardware to the software level. From the hardware perspective, a multiple-supply power management unit is proposed and is implemented using a Single-Inductor Multiple-Output (SIMO) DC-DC converter. To dynamically respond to the sensed instantaneous power demands and to accurately control the power delivery to the processor cores, the power management unit employs a software-defined adaptive global/local power allocation feedback controller. The proposed controller is designed using the hardware-software codesign methodology to uniquely control the SIMO converter during various operation scenarios. This is achieved using several embedded software control algorithms that operate synergetically to ensure efficient and reliable system operation. The hardware-software codesign technique also allows the SIMO controller to be integrated with future microprocessor cores. Therefore, by employing the vast amount of on-chip resources, the converter can perform effective power processing to provide the most power-optimal voltages at the hardware level. Such an embedded power management module leads to an integrated, power-aware, and autonomous SoC design that is independent of additional external hardware control, thereby reducing on-chip area and system complexity. In this design, each power output from the SIMO converter provides a step-up/down voltage conversion, thereby enabling a wide range of variable supply voltage. An adaptive global/local power allocation control algorithm is employed to significantly improve Dynamic Voltage and Frequency Scaling (DVFS) tracking speed and line/load regulation, while still retaining low cross-regulation. Designed with a 180nm CMOS process, the converter precisely provides three independently variable power outputs from 0.9 V to 3.0 V, with a total power range from 33 mW to 900 mW. A very fast load transient response of 3.25 μ s is achieved, in response to a 67.5-mA full-step load current change. The design thus provides a cost-effective power management solution to achieve a robust, fast-transient, DVFS-compatible multicore SoC.

Hardware-software co-design for various Parallel applications using the Concept of Dynamic Partial Reconfiguration at FPGA Partitions

In this paper an effective hardware design methodology for the devices like mobile phones, digital cameras, etc is described. In those devices only few applications are running at given time. So it requires only few hardware blocks to be active. This design approach is based on the idea of configuring and programming the hardware of active application whenever required at a single Field Programmable Gate Array (FPGA) chip. It requires effective hardware-software controller to configured required hardware for active application. In case of multiple applications running in-parallel, it is necessary to configure all the hardware required for these applications to be configured independently. To support this feature, the proposed design methodology introduces the concept of FPGA partitioning to configure these active parallel hardware designs where new designs can be configured at free un-configured partitions using partial configuration without disturbing the hardware of running application. Using this approach single FPGA chip can be configured dynamically for active application(s) only instead of configuring hardware design for all active and in-active applications thereby reducing the overall hardware, cost, size, power consumption and enhancing battery life. This paper explains about redesigning FPGA architecture to introduce FPGA Partitions, Partial & fast programming and Hardware-Software codesign methodology suitable for the devices which are running applications in parallel. D.S.Ravi Kumar Member Technical Staff, VLSI Engineer, Qualcore Logic ltd, Habsiguda, Hyderabad, A.P, India500 007 P. Naveen Kumar Senior Asst. Professor Dept of Electronics & Communication Engg, University College of Engg., Osmania University (A), Hyderabad, A.P., India -500007 The full text of the article is not available in the cache. Kindly refer the IJCA digital library at www.ijcaonline.org for the complete article. In case, you face problems while downloading the full-text, please send a mail to editor at editor@ijcaonline.org

PeaCE

Existent hardware-software (HW-SW) codesign tools mainly focus on HW-SW cosimulation to build a virtual prototyping environment that enables software design and system verification without need of making a hardware prototype. Not only HW-SW cosimulation, but also HW-SW codesign methodology involves system specification, functional simulation, design-space exploration, and hardware-software cosynthesis. The PeaCE codesign environment is the first full-fledged HW-SW codesign environment that provides seamless codesign flow from functional simulation to system synthesis. Targeting for multimedia applications with real-time constraints, PeaCE specifies the system behavior with a heterogeneous composition of three models of computation and utilizes features of the formal models maximally during the whole design process. It is also a reconfigurable framework in the sense that third-party design tools can be integrated to build a customized tool chain. Experiments with industry-strength examples prove the viability of the proposed technique.

Slicing-based Hardware/Software Co-design Methodology From Functional Specifications

Program slicing is a software analysis technique and generates System Dependence Graphs (SDGs) by which dependences among program statements can be identified. In this paper, we propose a new hardware-software co-design methodology based on the static and partially dynamic dependence analysis with SDG. We start with any combinations of C, C++, and SpecC descriptions so that flexible functional specifications of the HW/SW systems can be made. First of all, the input descriptions are analyzed and verified with the SDG generated from the input descriptions. Actual analyses and verifications are based on static ones but partially with dynamic ones as well, and fairly large descriptions can be processed. After these analyses, we divide the system into hardware and software parts by optimizing the design descriptions and introducing parallelism if necessary. In this HW/SW partitioning, SDG generated from C / C++ / SpecC design descriptions is fully utilized to extract / convert / pack the HW parts from the entire descriptions. This flexibility of HW/SW partitioning is one of the main differences from previous HW/SW partitioning methods. The extracted HW parts are further optimized and then converted into RTL descriptions by existing behavioral synthesis tools. As the last step, the generated RTL descriptions together with SW parts are compared to the original descriptions in order to make sure that they are logically equivalent. Also, designer-specified properties may be model checked with these final design descriptions. These equivalence checking and model checking can be realized by first translating the HW/SW design descriptions into FSM type representations. The translated FSM type representations are further processed by existing formal verifiers. We present the proposed HW/SW co-design methodology with an illustrating example as well as actual application to real designs and demonstrate the usefulness of our approach.

IMPLEMENTATION OF HETEROGONOUS EMBEDDED MICROSYSTEMS

To design heterogonous embedded microsystems using hardware-software codesign methodology, there is required formulated, mathematic model that describes complete system functionality, its properties and configuration. This paper presents and describes some aspects of a new formal model (based on Petri nets) for such microsystems and few selected examples of implementation. The behavioural specification of heterogonous embedded microsystems is represented as a timed, hierarchical Petri net extended with programming constructs and exception handling.

A hardware-software codesign methodology for DSP applications

The authors describe a systematic, heterogeneous design methodology using the Ptolemy framework for simulation, prototyping, and software synthesis of systems containing a mixture of hardware and software components. They focus on signal-processing systems in which the hardware typically consists of custom data paths, finite-state machines (FSMs), glue logic and programmable processors. The software is one or more embedded programs running on the programmable components.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>