D-wash – A dynamic workload aware adaptive cache coherance protocol for multi-core processor system

Abstract

In today's world, multi-processor plays the vital role in designing supercomputer, mobile phones and other wearable embedded systems. To handle power and latency issues in multicore processors, this paper proposes the workload aware adaptive cache coherence protocol in which works on the principle of the workload characterization that ranges from snooping to directory based mechanism. In this protocol, workload is characterized as low workloads and heavy workloads in which the snooping is adopted for heavy types whereas low workloads employs the directory protocol. The proposed protocol adapts dynamically cache coherence and its interconnection in the multi-processor adopting low latency and energy. For the evaluation different benchmarks such as IoMT (Internet of Medical Things) are utilized and implemented in Zync-SoC using hardware-software codesign methodology. Various parameters such as energy, latency and throughput are calculated and analyzed. Experimental results shows that the proposed protocol has achieved the 50% reduction in latency, 40% reduction in energy when compared with the other existing protocols.