Hardware Simulation Research Articles

Deep Q-Learning-Based Dynamic Management of a Robotic Cluster

The ever-increasing demands for autonomy and precision have led to the development of heavily computational multi-robot system (MRS). However, numerous missions exclude the use of robotic cloud. Another solution is to use the robotic cluster to locally distribute the computational load. This complex distribution requires adaptability to come up with a dynamic and uncertain environment. Classical approaches are too limited to solve this problem, but recent advances in reinforcement learning and deep learning offer new opportunities. In this paper we propose a new Deep Q-Network (DQN) based approaches where the MRS learns to distribute tasks directly from experience. Since the problem complexity leads to a curse of dimensionality, we use two specific methods, a new branching architecture, called Branching Dueling Q-Network (BDQ), and our own optimized multi-agent solution and we compare them with classical Market-based approaches as well as with non-distributed and purely local solutions. Our study shows the relevancy of learning-based methods for task mapping and also highlight the BDQ architecture capacity to solve high dimensional state space problems. <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Note to Practitioners</i> —A lot of applications in industry like area exploration and monitoring can be efficiently delegated to a group of small-size robots or autonomous vehicles with advantages like reliability and cost in respect of single-robot solutions. But autonomy requires high and increasing compute-intensive tasks such as computer-vision. On the other hand small robots have energy constraints, limited embedded computing capacities and usually restricted and/or unreliable communications that limit the use of cloud resources. An alternative solution to cope with this problem consists in sharing the computing resources of the group of robots. Previous work was a proof of concept limited to the parallelisation of a single specific task. In this paper we formalize a general method that allows the group of robots to learn on the field how to efficiently distribute tasks in order to optimize the execution time of a mission under energy constraint. We demonstrate the relevancy of our solution over market-based and non-distributed approaches by means of intensive simulations. This successful study is a necessary first step towards distribution and parallelisation of computation tasks over a robotic cluster. The next steps, not tested yet, will address hardware in the loop simulation and finally a real-life mission with a group of robots.

Performance Analysis of Bus Voltage in Distribution Network with High Penetration of PV Controlled via Data-Driven Approach

Integration of large-scale distributed photovoltaic (PV) generation resources can lead to technical challenges, particularly voltage rise caused by PVs power injection at the time of high solar radiation profile and low load demand. Reactive power control of PV inverters can help mitigate the voltage rise, which arises just for a short duration due to high incident solar radiation. There is a possibility to control functions on these PV inverters based on the rating of the PV inverter. For one-second resolution, local data-driven voltage sensitivity estimation is applied to update the control functions such as volt-var and volt-watt on the PV inverters so as to regulate the bus voltage. Different forms of solar radiation profiles, transient varying, smooth varying, and worst operating scenario corresponding to the minimum load at the time of high PV generation, are included. The study is demonstrated for different PV penetration levels. The voltage analysis on buses is performed using power hardware (PV emulator) in the loop simulation, at one of the buses in the network, while the remaining PVs are being controlled using volt-var control (VVC)/volt-watt control (VWC) methods. The applied approach confirms to maintaining bus voltage within limits even against a very short transient time instant of solar radiation profile.

Distributed collaborative optimal economic dispatch of integrated energy system based on edge computing

A distributed collaborative optimal dispatching strategy for the integrated energy system (IES), based on edge computing and consistency algorithm, is proposed in this paper. To solve the optimal dispatching problem of the IES coupled with electricity, heat, and gas, a cloud-edge-device architecture is constructed. A distributed group consensus algorithm (DGCA) is designed with two consistency protocols. The first protocol defines three groups of consistency variables, represented by the incremental cost of electricity, heat, and gas, respectively. The output estimation deviation of each component is used as a feedback. The second protocol considers the output estimation deviation of the three components as the consistency variables. The coupling variables of the two consistency protocols tend to be consistent, which can obtain the optimal output of each unit and achieve the optimal operation of the system. Furthermore, the proposed strategy accounts for transmission loss during transmission. Finally, through the hardware in the loop simulation based on the edge intelligent terminal (EIT), the effectiveness and feasibility of the strategy are verified, considering different cases.

A Channel Rendezvous Algorithm for Multi-Unmanned Aerial Vehicle Networks Based on Average Consensus.

Realizing the distributed adaptive network construction of multi-UAV networks is an urgent challenge, as they lack a reliable common control channel and can only maintain a limited sensing range in crowded electromagnetic environments. Multi-unmanned aerial vehicle (UAV) networks are gaining popularity in many fields. In order to address these issues, this paper proposes a multi-UAV network channel rendezvous algorithm based on average consistency. The goal of the algorithm is to adjust the communication channels of each UAV to converge on the same channel, since the communication link of the multi-UAV network is broken due to interference. The proposed memory-based average consistency (MAC) algorithm utilizes the network adjacency matrix as prior information. Furthermore, for the case where the adjacency matrix is unknown, this paper also proposes the Multi-Radio Average Consensus (MRAC) algorithm, which achieves a beneficial trade-off between rendezvous performance and hardware cost. Simulation results demonstrate that the proposed MAC and MRAC algorithms provide superior network convergence time and scalability in networks of different densities. Finally, a hardware simulation platform based on a multi-UAV network was designed using a software-defined radio platform, and experimental simulations were performed to prove the effectiveness of the MAC algorithm in a real environment.

Development Steps of Avionics and Flight Control System of Flight Vehicle

The success of a research is highly dependent on the method adopted, especially research related to dangerous and expensive matters which will certainly require special handling in the development or maintenance steps. One of them is research related to space technology such as aviation and rocketry technology, which is very dependent on the design model of the flying vehicle and, in general, will always use simulation to ensure that the entire system being built is carried out safely and can be implemented properly according to plan. In the development of the prototype flying vehicle, especially the development of the avionics and flight control system, the vehicle will go through sequential simulation steps from Software in the Loop Simulation (SILS), Hardware in the Loop Simulation (HILS), and Ready-to-Fly System (RTFS). In this paper, the simulation steps will be described with the intention of facilitating integration and testing of each sub-system being developed, testing the control strategy applied or eliminating bugs if something goes wrong. In the end, with a series of flying vehicle simulations, it can be developed quickly and cost-effectively, including saving human resources.&#x0D;

Edge Real-Time Object Detection and DPU-Based Hardware Implementation for Optical Remote Sensing Images

The accuracy of current deep learning algorithms has certainly increased. However, deploying deep learning networks on edge devices with limited resources is challenging due to their inherent depth and high parameter count. Here, we proposed an improved YOLO model based on an attention mechanism and receptive field (RFA-YOLO) model, applying the MobileNeXt network as the backbone to reduce parameters and complexity, adopting the Receptive Field Block (RFB) and Efficient Channel Attention (ECA) modules to improve the detection accuracy of multi-scale and small objects. Meanwhile, an FPGA-based model deployment solution was proposed to implement parallel acceleration and low-power deployment of the detection algorithm model, which achieved real-time object detection for optical remote sensing images. We implement the proposed DPU and Vitis AI-based object detection algorithms with FPGA deployment to achieve low power consumption and real-time performance requirements. Experimental results on DIOR dataset demonstrate the effectiveness and superiority of our RFA-YOLO model for object detection algorithms. Moreover, to evaluate the performance of the proposed hardware implementation, it was implemented on a Xilinx ZCU104 board. Results of the experiments for hardware and software simulation show that our DPU-based hardware implementation are more power efficient than central processing units (CPUs) and graphics processing units (GPUs), and have the potential to be applied to onboard processing systems with limited resources and power consumption.

Engine modelling architecture study for hybrid electric vehicle diagnosis application

Model-based control, calibration, and diagnosis are widely used in hybrid electric vehicles (HEVs) studies. For the real-time application, the contradiction lies in the model accuracy and fast response. This problem is particularly evident in engine modeling due to its complexity. In this study, three types of engine model architectures were studied for HEV Hardware In the Loop Simulation (HILS) diagnosis application. It shows that in terms of the real-time factor, the MAP model, obtaining all engine outputs only by looking up maps, has the best real-time performance. Both Mean Value Model (MVM) and Fast Running Model (FRM), with less than 3% steady-state error and preserving the engine's dynamic characteristics, have better real-time performance than the detailed model. What is more, the real-time performance of MVM is about 14% faster than that of FRM. MVM-based and FRM-based vehicle models were verified respectively in the HILS for the fault classification using support vector machine (SVM) and for the engine's misfire fault diagnosis. Since the MVM combines multiple detailed cylinders into a single mean value cylinder through neural network training, the MVM is typically used in diagnosis situations where fast computation speed is especially important and the detailed characterization of engine processes is considered relatively unimportant, such as vehicle-level fault diagnosis applications involving control system design, thermal management system fault, and power system fault, etc. Since the FRM reduces cylinder calculations by using the “cylinder translation method”, which preserves the working process within a single-cylinder cycle, it can also be used for fault diagnosis applications requiring engine performance with a crank-angle resolution, such as cylinder pressure diagnostics, combustion diagnostics, and timing control of valve and fuel injection, etc.

Establishment of Real-Time Simulation Test Environment for Electric Propulsion System of Unmanned Aerial Vehicle Using KDECAN Communication

This paper proposes the construction of a real-time simulation testing environment for the electric propulsion systems of unmanned aerial vehicles (UAVs) using a real-time simulator and KDECAN communication equipment. The proposed real-time simulation environment enables the testing of flight controllers and control algorithms using real-time control communication commands that are identical to those used during actual flight. The KDECAN protocol is analyzed and utilized in the proposed real-time simulation environment for control communication. A reduced-size lift–cruise UAV with eight lift motors (for takeoff) and one cruise motor (for cruising) is used as the target hardware for real-time simulation. This is used to verify the construction of the real-time simulation environment. The final goal of this work is to construct a real-time simulation environment for the stable application of propeller-driven devices, and the findings confirm the independent operation of the lift and cruise motors in the constructed testing environment. Additionally, the real-time monitoring of the state of the electronic speed controllers is verified, suggesting that the testing environment can be utilized as a verification tool for the control algorithms and system design data of electric propulsion systems in actual devices in the future.

DL BASED IOT ENERGY AUDIT ANALYTICS FOR DETECTING AND IDENTIFYING CYBER-PHYSICAL ATTACKS

Internet of Things (IoT) are vulnerable to both cyber and physical attacks. Therefore, a cyber-physical security system against different kinds of attacks is in high demand. Traditionally, attacks are detected via monitoring system logs. However, the system logs, such as network statistics and file access records, can be forged. Furthermore, existing solutions mainly target cyberattacks. This paper proposes the first energy auditing and analytics based IoT monitoring mechanism. To our best knowledge, this is the first attempt to detect and identify IoT cyber and physical attacks based on energy auditing. Using the energy meter readings, we develop a dual deep learning (DL) model system, which adaptively learns the system behaviors in a normal condition. Unlike the previous single DL models for energy disaggregation, we propose a disaggregation-aggregation architecture. The innovative design makes it possible to detect both cyber and physical attacks. The disaggregation model analyzes the energy consumptions of system subcomponents, e.g., CPU, network, disk, etc., to identify cyber-attacks, while the aggregation model detects the physical attacks by characterizing the difference between the measured power consumption and prediction results. Using energy consumption data only, the proposed system identifies both cyber and physical attacks. The system and algorithm designs are described in detail. In the hardware simulation experiments, the proposed system exhibits promising performances.

Reconfigurable linear feedback shift register for wireless communication and coding

&lt;p&gt;Linear feedback shift register (LFSR) is the basic building block of the communication system used in different coding, error detection and correction codes, such as gold, low-density parity check (LDPC), polar, and turbo codes. There are simple shift register-based n-bit counters with a few XOR gates that behave pseudo-randomly. The LFSR is used in chip hardware for high-speed operations, error control, and the generation of pseudo-random numbers. The hardware chip design and performance estimation of the LFSR is the problem for specific communication system. The motivation of the work is to generate the Gold code sequence by the integration of two LFSR. The article proposes the hardware chip design and simulation of two 5-bit LFSR modules used for the gold sequence generator applicable for the communication systems. The novelty of the work is that the design is scalable and can be extended based on the requirements of the systems which is synthesized and experimentally verified on the Zynq-7000 field programmable gate array (FPGA) board. The concept of this design is programmable and can be extended to n-bit based on the applications. The work is supported, and formulated using very high speed integrated circuit hardware description language (VHDL) programming in Xilinx ISE 14.7 software.&lt;/p&gt;

Hardware Design and Simulation of Boost Converter Suitable for PV Applications

Abstract: In order to power today's most advanced electronic devices efficiently and quickly produce extremely useful devices through software interfacing, new techniques must be developed as the size, utility, and complexity of these devices rise. In order to step-up DC voltages, the boost converter that is the focus of this paper will be modelled. The pulse width modulation pulses that are applied to power switches are produced by the Arduino. The software runs on the microcontroller and includes a boot loader for common programming languages. C is the programming language used. As a result, creating PWM triggering signals is less complicated. Instead of using traditional methods, an efficient feedback system is used, depending on the application, to obtain the desired DC voltages. Even though using a linear regulator is the simplest way to control the DC supply voltage, they are less efficient in terms of power consumption and have fewer uses. With the right feedback, Arduino-based DC converters have a high efficiency (95%) rate

Hardware in the Loop Simulation for Bottle Sealing Process Virtualized on Unity 3D

This paper details the design and implementation of a virtualized bottle sealing plant using the Hardware in the Loop technique, for which it is divided into two parts: (i) Software consists of a virtualized environment in Unity 3D to visualize its behavior in real time; and (ii) Hardware was implemented through a PLC S7 1200 AC/DC/RLY (Programmable Logic Controller), which is responsible for the automation of the plant, programmed through the software TIA Portal V16 (Totally Integrated Automation Portal) and a control panel with buttons and indicator lights. The two developed parts communicate through bidirectional TCP/IP Ethernet, achieving a Server–Client architecture. For real-time monitoring and visualization, a SCADA (Supervisory Control and Data Acquisition) system implemented in InTouch is considered. In addition, the data acquisition is accomplished through the OPC (Open Platform Communication) server; the functionality of the OPC server is to transmit the information generated in an industrial plant at the enterprise level. This allows the process to execute its tasks of connectivity of automated processes and their supervision, as well as having scalability so that more tags can be included in other processes over time and ensure its operability.

A Streaming Data Processing Architecture Based on Lookup Tables

Processing in memory (PIM) is a new computing paradigm that stores the function values of some input modes in a lookup table (LUT) and retrieves their values when similar input modes are encountered (instead of performing online calculations), which is an effective way to save energy. In the era of the Internet of Things, the processing of massive data generated by the front-end requires low-power and real-time processing. This paper investigates an energy-efficient processing architecture based on table lookup in phase-change memory (PCM). This architecture replaces logical-based calculations with LUT lookups to minimize power consumption and operation latency. In order to improve the efficiency of table lookup, the RISC-V instruction set has included extended lookup and data stream transmission instructions. Finally, the system architecture is validated by hardware simulation, and the performance of computing the fast Fourier transform (FFT) application is evaluated. The proposed architecture effectively improves the execution efficiency and reduces the power consumption of data flow operations.

Agile Methods For Improved Cyber Operations Planning

Cyber Ranges provide an interactive simulated environment of hardware and software for simulation. This closed environment provides a safe and legal environment where cyber warfighters can refine their skills. They enable mock cyber mission rehearsal of operation playbooks. Simulated cyber capabilities in the cyber range parallel the intelligence, surveillance, and reconnaissance (ISR), Order of Battle (OOB), and battle damage assessment (BDA) in a closed, safe environment for experimentation. Scrum has been used in collegial cyber competitions with success because it has allowed Capture-the-Flag cyber games to create quicker simulations. Defense Innovation Units (DIUs) are using agile Scrum processes to numerous warfighting areas in order to make them more agile. This research argues that the agile software development processes could be used to optimize the planning and execution of offensive, defensive, and operation and maintenance (O&amp;M) of cyber warfare simulations within cyber ranges. O&amp;M can be done quicker, new exploitable modules can be includer more rapidly, and the capability can be reconstituted to the appropriate skill level for the next set of trainees quicker. The White team as maintainers of the networks, systems, applications and cyber tools select the CVE exploits and spend an enormous amount of time installing and configuring these capabilities for the next set of trainees. Quite often, there are different skill levels which require multiple builds and the ability to refresh the cyber range with varying levels of cyber trainee complexity. This requirement to restore the cyber range quickly with a variety of builds, varying levels of difficulty, and ensure the experiential learning is maximized with the best availability lends to agile methods such as Scrum could lend to improvements with cyber operations. This research will illustrate how a cyber range could leverage agile Scrum processes to provide an improved cyber range environment quicker and with more capabilities.

Design and Analysis of a Processing-in-DIMM Join Algorithm: A Case Study with UPMEM DIMMs

Modern dual in-line memory modules (DIMMs) support processing-in-memory (PIM) by implementing in-DIMM processors (IDPs) located near memory banks. PIM can greatly accelerate in-memory join, whose performance is frequently bounded by main-memory accesses, by offloading the operations of join from host central processing units (CPUs) to the IDPs. As real PIM hardware has not been available until very recently, the prior PIM-assisted join algorithms have relied on PIM hardware simulators which assume fast shared memory between the IDPs and fast inter-IDP communication; however, on commodity PIM-enabled DIMMs, the IDPs do not share memory and demand the CPUs to mediate inter-IDP communication. Such discrepancies in the architectural characteristics make the prior studies incompatible with the DIMMs. Thus, to exploit the high potential of PIM on commodity PIM-enabled DIMMs, we need a new join algorithm designed and optimized for the DIMMs and their architectural characteristics. In this paper, we design and analyze Processing-In-DIMM Join (PID-Join), a fast in-memory join algorithm which exploits UPMEM DIMMs, currently the only publicly-available PIM-enabled DIMMs. The DIMMs impose several key challenges on efficient acceleration of join including the shared-nothing nature and limited compute capabilities of the IDPs, the lack of hardware support for fast inter-IDP communication, and the slow IDP-wise data transfers between the IDPs and the main memory. PID-Join overcomes the challenges by prototyping and evaluating hash, sort-merge, and nested-loop algorithms optimized for the IDPs, enabling fast inter-IDP communication using host CPU cache streaming and vector instructions, and facilitating fast rank-wise data transfers between the IDPs and the main memory. Our evaluation using a real system equipped with eight UPMEM DIMMs and 1,024 IDPs shows that PID-Join greatly improves the performance of in-memory join over various CPU-based in-memory join algorithms.

The Concept of Constructing a Stand to Test the SpaceWire Onboard Equipment with Possibility of Software and Hardware Simulation of Reconfigurable Topology of the Spacecraft Onboard Network

The Concept of Constructing a Stand to Test the SpaceWire Onboard Equipment with Possibility of Software and Hardware Simulation of Reconfigurable Topology of the Spacecraft Onboard Network

ACBN: Approximate Calculated Batch Normalization for Efficient DNN On-Device Training Processor

Batch normalization (BN) has been established as a very effective component in deep learning, largely helping accelerate the convergence of deep neural network (DNN) training. Nevertheless, its hardware architecture has not received much attention in the field of DNN on-device training processors. Several previous designs incur either high off-chip memory traffic or high circuit complexity, and hence have deficiencies in terms of hardware efficiency and performance. This article proposes approximately calculated BN (ACBN) to achieve a much better tradeoff between hardware efficiency and performance for DNN on-device training processors. The accuracy and convergence rate of the proposed ACBN have been extensively evaluated using four typical DNN models. Compared with the state-of-the-art reference design, the hardware simulation results show the proposed ACBN can at least reduce floating point operations by 22.2% and save external memory access by 33.3% on average. Moreover, the proposed ACBN introduces 63.6% data sparsity for the backward propagation of BN layers of VGG16 on average. To the best of our knowledge, we are the first to introduce data sparsity for the backward propagation of BN layers. The ACBN module is implemented on Zynq UltraScale <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$+$</tex-math> </inline-formula> ZCU102 system-on-chip (SoC) field-programmable gate array (FPGA), and the results show that the implementation of ACBN hardware module saves 33.9% look-up table (LUT), 49.4% flip-flop (FF), 75% digital signal processor (DSP), and reduces the power by 12.4% compared with the reference design while achieving better performance.

Analytical Redundancy for Variable Cycle Engine Based on Variable-Weights-Biases Neural Network

Due to the complex nature of a variable cycle engine (VCE), which has numerous control variables and working modes across a broad flight envelope, coupled with the whole engine’s degradation, the analytical redundancy method based on component-level models may not provide an accurate estimation of the sensors. Variable-weights-biases neural network (VWB Net) is proposed to construct VCE’s analytical redundancy. Unlike conventional networks whose weights and biases are fixed, VWB Net’s variable-weights and variable-biases are functions of input which greatly increase its nonlinear mapping capability by integrating input information. Variable-biases can also be used to eliminate the error between actual sensor output and estimated value quickly at the terminal node. Compared with the BP network and Dense net, VWB Net has fewer parameters, faster calculation speed, and higher accuracy. Digital simulation results of VCE parameter estimation demonstrate that VWB Net’s average relative errors are under 0.27% with calculation and parameter efficiency at least 166 times higher than that of Dense net. Hardware in the loop simulation further verifies VWB Net’s estimation accuracy and real-time calculation.

GNSS Data/Pilot Combining with Extended Integrations for Carrier Tracking.

Modern Global Navigation Satellite System (GNSS) signals are usually made of two components: a pilot and a data channel. The former is adopted to extend the integration time and improve receiver sensitivity, whereas the latter is used for data dissemination. Combining the two channels allows one to fully exploit the transmitted power and further improve receiver performance. The presence of data symbols in the data channel, however, limits the integration time in the combining process. When a pure data channel is considered, the integration time can be extended using a squaring operation, which removes the data symbols without affecting phase information. In this paper, Maximum Likelihood (ML) estimation is used to derive the optimal data-pilot combining strategy and extend the integration time beyond the data symbol duration. In this way, a generalized correlator is obtained as the linear combination of the pilot and data components. The data component is multiplied by a non-linear term, which compensates for the presence of data bits. Under weak signal conditions, this multiplication leads to a form of squaring, which generalizes the squaring correlator used in data-only processing. The weights of the combination depend on the signal amplitude and noise variance that need to be estimated. The ML solution is integrated into a Phase Lock Loop (PLL) and used to process GNSS signals with data and pilot components. The proposed algorithm and its performance are characterized from a theoretical point of view, using semi-analytic simulations and through the processing of GNSS signals generated using a hardware simulator. The derived method is compared with other data/pilot combining strategies with extended integrations showing the advantages and drawbacks of the different approaches.

Energy Efficiency of Opportunistic Refreshing for Gain-Cell Embedded DRAM

On-die memories, which are traditionally implemented by SRAM, stop functioning properly when the supply voltage is scaled down aggressively; hence, embedded DRAMs (eDRAMs) are used instead. Opportunistic refreshing was proved to eliminate the performance loss incurred by the eDRAM refreshing must. We show here that Gain-Cell eDRAM (GCeDRAM) supplemented with opportunistic refreshing consumes significantly smaller power and energy than SRAM. Analysis supported by hardware simulations demonstrate that the same design point achieves maximum performance and minimum energy. Replacement of the data memory in the ultra-low power processor PULPino from SRAM to opportunistically refreshed GCeDRAM yielded 30% energy savings in the memory, which translated into 7% savings in the entire processor.