Network Hardware Research Articles

An AER-based spiking convolution neural network system for image classification with low latency and high energy efficiency

Spiking neural network is used to solve the problems of power consumption and computation requirement of the traditional artificial neural network. This paper proposes an event-driven multilayer spiking convolutional neural network (SCNN) hardware system for the image classification task. The proposed hardware system consists of a microcontroller unit (MCU) and an SCNN processor. Input images are temporally encoded to spike trains in the form of address event representation (AER) by MCU, and sent to the SCNN processor to execute AER-based spike-centric convolution in order to reduce redundant operations and get the classification result efficiently. By rearranging the storage structure of weights of synapses and membrane potential (MP) of spiking neurons, multi-channel parallel MP updating is realized to reduce latency. In addition, FIFOs are inserted between the spiking layers to construct a pipeline structure. The hardware architecture of the proposed system is implemented on the Xilinx ZYNQ-7000 platform. At the operating frequency of 100 MHz, the proposed SCNN processor has a speed of 400classifications/s and 80uJ/inference.

Security of software defined networks: evolution and challenges

<span>In software-defined networking (SDN), network traffic is managed by software controllers or application programming interfaces (APIs) rather than hardware components. It differs from traditional networks, which use switches and routers to control traffic. Using SDN, you can create and control virtual networks or traditional hardware networks. Furthermore, OpenFlow allows network administrators to control exact network behavior through centralized control of packet forwarding. For these reasons, SDN has advantages over certain security issues, unlike traditional networks. However, most of the existing vulnerabilities and security threats in the traditional network also impact the SDN network. This document presents the attacks targeting the SDN network and the solutions that protect against these attacks. In addition, we introduce a variety of SDN security controls, such as intrusion detection systems (IDS)/intrusion prevention system (IPS), and firewalls. Towards the end, we outline a conclusion and perspectives.</span>

High-Performance Neuromorphic Computing and Logic Operation Based on a Self-Assembled Vertically Aligned Nanocomposite SrTiO3:MgO Film Memristor.

Neuromorphic computing based on memristors capable of in-memory computing is promising to break the energy and efficiency bottleneck of well-known von Neumann architectures. However, unstable and nonlinear conductance updates compromise the recognition accuracy and block the integration of neural network hardware. To this end, we present a highly stable memristor with self-assembled vertically aligned nanocomposite (VAN) SrTiO3:MgO films that achieve excellent resistive switching with low set/reset voltage variability (4.7%/-5.6%) and highly linear conductivity variation (nonlinearity = 0.34) by spatially limiting the conductive channels at the vertical interfaces. Various synaptic behaviors are simulated by continuously modulating the conductance. Especially, convolutional image processing using diverse crossbar kernels is demonstrated, and the artificial neural network achieves an overwhelming recognition accuracy of up to 97.50% for handwritten digits. Even under the perturbation of Poisson noise (λ = 10), 6% Salt and Pepper noise, and 5% Gaussian noise, the high recognition accuracies are retained at 95.43%, 94.56%, and 95.97%, respectively. Importantly, the logic memory function is proven experimentally based on the nonvolatile properties. This work provides a material system and design idea to achieve high-performance neuromorphic computing and logic operation.

Real-Time AI-Driven Fall Detection Method for Occupational Health and Safety

Fall accidents in industrial and construction environments require an immediate reaction, to provide first aid. Shortening the time between the fall and the relevant personnel being notified can significantly improve the safety and health of workers. Therefore, in this work, an IoT system for real-time fall detection is proposed, using the ASSIST-IoT reference architecture. Empowered with a machine learning model, the system can detect fall accidents and swiftly notify the occupational health and safety manager. To train the model, a novel multimodal fall detection dataset was collected from ten human participants and an anthropomorphic dummy, covering multiple types of fall, including falls from a height. The dataset includes absolute location and acceleration measurements from several IoT devices. Furthermore, a lightweight long short-term memory model is proposed for fall detection, capable of operating in an IoT environment with limited network bandwidth and hardware resources. The accuracy and F1-score of the model on the collected dataset were shown to exceed 0.95 and 0.9, respectively. The collected multimodal dataset was published under an open license, to facilitate future research on fall detection methods in occupational health and safety.

Quality of Service Management Solution Becomes a Software-Defined Network Challenge

The use of Software-Defined Networking (SDN) has created a huge leap in the management of computer networks. SDN offers flexibility and the ability to dynamically manage networks, but along with its advantages, it also brings significant challenges in managing quality of service (QoS). QoS is critical to maintaining performance and user experience in increasingly complex and distributed network environments. The research method uses Solution Development to address a quality of service (QoS) management challenge and solution in Software Defined Networking with the approach of designing and developing practical solutions to address QoS management issues and challenges in SDN environments. Control Separation and Data Plane are centralized network control at the SDN controller, while the data plane reside in the networks hardware, both capable of maintaining QoS and a challenges in SDN with a computer network approach that separates the control layer from the data layer, enabling more flexible and centralized network management. Research conclusions related to SDN Software Defined Networking quality of service management problems and solutions, focusing on the problem of separating management and data levels. The separations of control and data plane concept in SDN has great potential to improve flexibility, scalability and more efficient network management.

The Internet of Tomorrow Must Sleep More and Grow Old

Today, the ICT industry has a massive carbon footprint (a few percent of worldwide emissions) and one of the fastest growth rates. The Internet accounts for a large part of that footprint while being also energy inefficient; i.e. , the total energy cost per byte transmitted is very high. Thankfully, there are many ways to improve the current status; we discuss two relatively unexplored directions in this paper. Putting network devices to "sleep," i.e. , turning them off, is known to be an efficient vector to save energy; we argue that harvesting this potential requires new routing protocols, better suited to devices switching on/off often, and revising the corresponding hardware/software co-design. Moreover, we can reduce the embodied carbon footprint by using networking hardware longer, and we argue that this could even be beneficial for reliability! We sketch our first ideas in these directions and outline practical challenges that we (as a community) need to address to make the Internet more sustainable.

Complex-valued trainable activation function hardware using a TCO/silicon modulator

Artificial neural network-based electro-optic chipsets constitute a very promising platform because of its remarkable energy efficiency, dense wavelength parallelization possibilities and ultrafast modulation speeds, which can accelerate computation by many orders of magnitude. Furthermore, since the optical field carries information in both amplitude and phase, photonic hardware can be leveraged to naturally implement complex-valued neural networks (CVNNs). Operating with complex numbers may double the internal degrees of freedom as compared with real-valued neural networks, resulting in twice the size of the hardware network and, thus, increased performance in the convergence and stability properties. To this end, the present work revolves on the concept of CVNNs by offering a design, and simulation demonstration, for an electro-optical dual phase and amplitude modulator implemented by integrating a transparent conducting oxide (TCO) in a silicon waveguide structure. The design is powered by the enhancement of the optical-field confinement effect occurring at the epsilon-near-zero (ENZ) condition, which can be tuned electro-optically in TCOs. Operating near the ENZ resonance enables large changes on the real and imaginary parts of the TCO’s permittivity. In this way, phase and amplitude (dual) modulation can be achieved in single device. Optimal design rules are discussed in-depth by exploring device’s geometry and voltage-dependent effects of carrier accumulation inside the TCO film. The device is proposed as a complex-valued activation function for photonic neural systems and its performance tested by simulating the training of a photonic hardware neural network loaded with our custom activation function.

Development of Augmented Reality-Based Mobile App Learning Media for Computer Network Hardware Material

The objective of this research is to create a mobile app-based augmented reality learning media for computer network hardware. The specific aims are to describe the application model design, application functionality, feasibility, and effectiveness of using augmented reality-based mobile app learning media on computer network hardware. The research methodology employed in this study is Research and Development (R&D). The development stages include research, data collection, planning, draft product development, product validation, revision based on product validation results, field testing, revision based on field testing results, final product refinement, and dissemination. Furthermore, to assess the improvement in learning outcomes, the Independent Sample T Test statistical method is used. The results obtained in this research show a significant difference in the experimental class compared to the control class, where the average score in the experimental class is higher. Therefore, it can be concluded that learning computer network hardware material using augmented reality has successfully improved student learning outcomes.
 Keywords: Learning Media, Augmented Reality, Mobile Apps, Computer Network Hardware.

Improving Worst-case TSN Communication Times of Large Sensor Data Samples by Exploiting Synchronization

Higher levels of automated driving also require a more sophisticated environmental perception. Therefore, an increasing number of sensors transmit their data samples as frame bursts to other applications for further processing. As a vehicle has to react to its environment in time, such data is subject to safety-critical latency constraints. To keep up with the resulting data rates, there is an ongoing transition to a Time-Sensitive Networking (TSN)-based communication backbone. However, the use of TSN-related industry standards does not match the automotive requirements of large timely sensor data transmission, nor it offers benefits on time-critical transmissions of single control data packets. By using the full data rate of prioritized IEEE 802.1Q Ethernet, giving time guarantees on large data samples is possible, but with strongly degraded results due to data collision. Resolving such collisions with time-aware shaping comes with significant overhead. Hence, rather than optimizing the parameters of the existing protocol, we propose a system design that synchronizes the transmission times of sensor data samples. This limits network protocol complexity and hardware requirements by avoiding tight time synchronization and time-aware shaping. We demonstrate that individual sensor data samples are transmitted without significant interference, exclusively at full Ethernet data rate. We provide a synchronous event model together with a straightforward response time analysis for synchronous multi-frame sample transmissions. The results show that worst-case latencies of such sample communication, in contrast to non-synchronized approaches, are close to their theoretical minimum as well as to simulative results while keeping the overall network utilization high.

Demonstration of an AI-driven workflow for autonomous high-resolution scanning microscopy

Modern scanning microscopes can image materials with up to sub-atomic spatial and sub-picosecond time resolutions, but these capabilities come with large volumes of data, which can be difficult to store and analyze. We report the Fast Autonomous Scanning Toolkit (FAST) that addresses this challenge by combining a neural network, route optimization, and efficient hardware controls to enable a self-driving experiment that actively identifies and measures a sparse but representative data subset in lieu of the full dataset. FAST requires no prior information about the sample, is computationally efficient, and uses generic hardware controls with minimal experiment-specific wrapping. We test FAST in simulations and a dark-field X-ray microscopy experiment of a WSe2 film. Our studies show that a FAST scan of <25% is sufficient to accurately image and analyze the sample. FAST is easy to adapt for any scanning microscope; its broad adoption will empower general multi-level studies of materials evolution with respect to time, temperature, or other parameters.

Information Communication Technology Tools for Animal Husbandry Technology Dissemination

In the Indian economy, the livestock sector contributes 4.9% of the overall GDP, accounting for around 30.13 per cent of the country's agricultural GDP. India has the worlds largest livestock population, but the average animal productivity is low; yet demand for livestock products is rising steadily, and customers’ awareness of quality has also increased. Therefore, it is necessary to refocus the production system by figuring out what information cattle farmers currently need. The animal husbandry department can only meet some livestock farmers' information needs. A multi-stakeholder online network across the livestock value chain is required to meet these information needs. Systems with ICT capabilities are better suited to deal with these problems. Radio, television, mobile, fixed, computer and network hardware and software, satellite systems, and video conferencing are all considered part of information and communication technology (ICT), a broad term covering any communication device or application. These include delivering information in the form of audio, data, video, and images, among other things. It is very beneficial for boosting the economy, creating jobs, developing rural areas, and reducing poverty. In modern times, ICT has become essential to the development of cattle. This article discusses using ICT technologies to spread animal husbandry technology among Indian farmers.

Design and Research of a Field Bus Control System Laboratory for Metal Mining, Beneficiation and Metallurgy

Fieldbus control systems play a pivotal role in industries such as mining, beneficiation, and metallurgy, facilitating precise process control. However, diverse process conditions and applications often lead to challenges during system implementation. The prevalence of process control projects underscores the need for dedicated control system laboratories to address these problems. Our research delves into the complexities of process control systems, focusing on mainstream brands such as Siemens, Rockwell, and Emerson, involving analysis of network architectures, software, and hardware configurations. Through rigorous testing of real equipment systems, we uncover prevalent issues in practical control system applications. These findings guide the resolution of technical challenges faced in project control, concurrently enhancing the design and debugging prowess of engineering professionals. We also anticipate the trajectory of intelligent manufacturing, embracing collaborative manufacturing aspects in networked environments. This research establishs a robust foundation for the forthcoming generation of control network technologies specific to metal mining, beneficiation, and metallurgy.

Offloading Machine Learning to Programmable Data Planes: A Systematic Survey

The demand for machine learning (ML) has increased significantly in recent decades, enabling several applications, such as speech recognition, computer vision, and recommendation engines. As applications become more sophisticated, the models trained become more complex while also increasing the amount of data used for training. Several domain-specific techniques can be helpful to scale machine learning to large amounts of data and more complex models. Among the methods employed, of particular interest is offloading machine learning functionality to the network infrastructure, which is enabled by the use of emerging programmable data plane hardware, such as SmartNICs and programmable switches. As such, offloading machine learning to programmable network hardware has attracted considerable attention from the research community in the last few years. This survey presents a study of programmable data planes applied to machine learning, also highlighting how in-network computing is helping to speed up machine learning applications. In this article, we provide various concepts and propose a taxonomy to classify existing research. Next, we systematically review the literature that offloads machine learning functionality to programmable data plane devices, classifying it based on our proposed taxonomy. Finally, we discuss open challenges in the field and suggest directions for future research.

Evaluation of error components in rainfall retrieval from collocated commercial microwave links

Abstract. Opportunistic rainfall sensing using commercial microwave links (CMLs) operating in telecommunication networks has the potential to complement conventional rainfall monitoring; however, the diversity of sensors and their errors are difficult to handle. This analysis empirically evaluates errors in CML observations that manifest discrepancies between collocated sensors without reference to rainfall measurements. Collocated CMLs are evaluated as independent rainfall sensors and enable us to assess the effect of hardware homogeneity and measurement consistency using CML observations at 12 sites within a real telecommunication network in Prague. The evaluation considers 33 rainfall events distinguishing between stratiform and convective rainfall types in the period of 2014–2016, monitored at 1 min temporal resolution. Collocated CMLs of identical and different frequencies are evaluated, and different rainfall types are discussed. The collocated CMLs are in excellent agreement. The inherent error in rain-induced attenuation for paired independent CMLs is 0.4 dB. The high correlation of the rainfall intensity measurements between the collocated sensors was obtained in a range of 0.96 to 0.99, and the root mean square error ranges from 0.4 to 1.7 mm h−1. This confirms the homogeneous behaviour of the hardware in a real network. Therefore, the data of CMLs of the same characteristics can be processed with identical parameters for rainfall retrieval models.

Programmable Energy-Efficient Analog Multilayer Perceptron Architecture Suitable for Future Expansion to Hardware Accelerators

A programmable, energy-efficient analog hardware implementation of a multilayer perceptron (MLP) is presented featuring a highly programmable system that offers the user the capability to create an MLP neural network hardware design within the available framework. In addition to programmability, this implementation provides energy-efficient operation via analog/mixed-signal design. The configurable system is made up of 12 neurons and is fabricated in a standard 130 nm CMOS process occupying approximately 1 mm2 of on-chip area. The system architecture is analyzed in several different configurations with each achieving a power efficiency of greater than 1 tera-operations per watt. This work offers an energy-efficient and scalable alternative to digital configurable neural networks that can be built upon to create larger networks capable of standard machine learning applications, such as image and text classification. This research details a programmable hardware implementation of an MLP that achieves a peak power efficiency of 5.23 tera-operations per watt while consuming considerably less power than comparable digital and analog designs. This paper describes circuit elements that can readily be scaled up at the system level to create a larger neural network architecture capable of improved energy efficiency.

Broadcast Propagation Time in SpaceFibre Networks with Various Types of Spatial Redundancy

Various methods of spatial redundancy can be used in local networks based on the SpaceFibre standard for fault mitigation of network hardware and physical communication channels. Usually, a network developer chooses the method of spatial redundancy according to the number of failures that have to be mitigated, the time required for restoring the normal operation of the network, required overheads and hardware costs. The use of different spatial redundancy mechanisms can cause changes in the structure of the links between network nodes, in case of failure and subsequent mitigation. In turn, this may cause changes in the broadcast transmission paths and the temporal characteristics of their delivery from the source to the receivers. This article focuses on the change in the propagation time of broadcasts in SpaceFibre networks with spatial redundancy. Broadcast propagation rules significantly differ from data-packet propagation rules. Broadcast distribution time is very important for many applications, because broadcasts are generally used to send urgent messages, in particular for time synchronization. Various formal methods have been used to evaluate the propagation characteristics of the broadcast. A method for estimating broadcast propagation time along the shortest routes is proposed. In addition, we provide a formal method to estimate the number of failures, which occurred in the network during the broadcast propagation. This method is based on timed Petri nets; one of its features is the ability to calculate broadcast transmission delays. In addition, as an alternative solution, we propose a method for estimating delays based on time automata theory.

Toolflow for the algorithm-hardware co-design of memristive ANN accelerators

The capabilities of artificial neural networks are rapidly evolving, so are the expectations for them to solve ever more challenging tasks in numerous everyday situations. Larger, more complex networks and the need to execute them efficiently on edge devices are the two counteracting requirements of this trend. Novel devices and computation techniques show promising characteristics to address this challenge. A huge design space covering different combinations of neural networks and hardware architectures using these technologies needs to be explored. An efficient design flow is, therefore, crucial for a good quality of service. This work reviews a wide range of simulation tools for novel memristive devices and analyzes their applicability for the design space exploration. A modular toolflow is proposed that shrinks down the large design space step-by-step using state-of-the-art optimization techniques and builds upon existing tools to find the best trade-offs between network accuracy and hardware requirements.

A High Performance Reconfigurable Hardware Architecture for Lightweight Convolutional Neural Network

Since the lightweight convolutional neural network EfficientNet was proposed by Google in 2019, the series of models have quickly become very popular due to their superior performance with a small number of parameters. However, the existing convolutional neural network hardware accelerators for EfficientNet still have much room to improve the performance of the depthwise convolution, squeeze-and-excitation module and nonlinear activation functions. In this paper, we first design a reconfigurable register array and computational kernel to accelerate the depthwise convolution. Next, we propose a vector unit to implement the nonlinear activation functions and the scale operation. An exchangeable-sequence dual-computational kernel architecture is proposed to improve the performance and the utilization. In addition, the memory architectures are designed to complete the hardware accelerator for the above computing architecture. Finally, in order to evaluate the performance of the hardware accelerator, the accelerator is implemented based on Xilinx XCVU37P. The results show that the proposed accelerator can work at the main system clock frequency of 300 MHz with the DSP kernel at 600 MHz. The performance of EfficientNet-B3 in our architecture can reach 69.50 FPS and 255.22 GOPS. Compared with the latest EfficientNet-B3 accelerator, which uses the same FPGA development board, the accelerator proposed in this paper can achieve a 1.28-fold improvement of single-core performance and 1.38-fold improvement of performance of each DSP.

OMPQ: Orthogonal Mixed Precision Quantization

To bridge the ever-increasing gap between deep neural networks' complexity and hardware capability, network quantization has attracted more and more research attention. The latest trend of mixed precision quantization takes advantage of hardware's multiple bit-width arithmetic operations to unleash the full potential of network quantization. However, existing approaches rely heavily on an extremely time-consuming search process and various relaxations when seeking the optimal bit configuration. To address this issue, we propose to optimize a proxy metric of network orthogonality that can be efficiently solved with linear programming, which proves to be highly correlated with quantized model accuracy and bit-width. Our approach significantly reduces the search time and the required data amount by orders of magnitude, but without a compromise on quantization accuracy. Specifically, we achieve 72.08% Top-1 accuracy on ResNet-18 with 6.7Mb parameters, which does not require any searching iterations. Given the high efficiency and low data dependency of our algorithm, we use it for the post-training quantization, which achieves 71.27% Top-1 accuracy on MobileNetV2 with only 1.5Mb parameters.

CNN Hardware Accelerator for Real-Time Bearing Fault Diagnosis

This paper introduces a one-dimensional convolutional neural network (CNN) hardware accelerator. It is crafted to conduct real-time assessments of bearing conditions using economical hardware components, implemented on a field-programmable gate array evaluation platform, negating the necessity to transfer data to a cloud-based server. The adoption of the down-sampling technique augments the visible time span of the signal in an image, thereby enhancing the accuracy of the bearing condition diagnosis. Furthermore, the proposed method of quaternary quantization enhances precision and shrinks the memory demand for the neural network model by an impressive 89%. Provided that the current signal data sampling rate stands at 64 K samples/s, the proposed design can accomplish real-time fault diagnosis at a clock frequency of 100 MHz. Impressively, the response duration of the proposed CNN hardware system is a mere 0.28 s, with the fault diagnosis precision reaching a remarkable 96.37%.