Network Hardware Research Articles

Development of Augmented Reality-Based Mobile App Learning Media for Computer Network Hardware Material

The objective of this research is to create a mobile app-based augmented reality learning media for computer network hardware. The specific aims are to describe the application model design, application functionality, feasibility, and effectiveness of using augmented reality-based mobile app learning media on computer network hardware. The research methodology employed in this study is Research and Development (R&D). The development stages include research, data collection, planning, draft product development, product validation, revision based on product validation results, field testing, revision based on field testing results, final product refinement, and dissemination. Furthermore, to assess the improvement in learning outcomes, the Independent Sample T Test statistical method is used. The results obtained in this research show a significant difference in the experimental class compared to the control class, where the average score in the experimental class is higher. Therefore, it can be concluded that learning computer network hardware material using augmented reality has successfully improved student learning outcomes.
 Keywords: Learning Media, Augmented Reality, Mobile Apps, Computer Network Hardware.

Improving Worst-case TSN Communication Times of Large Sensor Data Samples by Exploiting Synchronization

Higher levels of automated driving also require a more sophisticated environmental perception. Therefore, an increasing number of sensors transmit their data samples as frame bursts to other applications for further processing. As a vehicle has to react to its environment in time, such data is subject to safety-critical latency constraints. To keep up with the resulting data rates, there is an ongoing transition to a Time-Sensitive Networking (TSN)-based communication backbone. However, the use of TSN-related industry standards does not match the automotive requirements of large timely sensor data transmission, nor it offers benefits on time-critical transmissions of single control data packets. By using the full data rate of prioritized IEEE 802.1Q Ethernet, giving time guarantees on large data samples is possible, but with strongly degraded results due to data collision. Resolving such collisions with time-aware shaping comes with significant overhead. Hence, rather than optimizing the parameters of the existing protocol, we propose a system design that synchronizes the transmission times of sensor data samples. This limits network protocol complexity and hardware requirements by avoiding tight time synchronization and time-aware shaping. We demonstrate that individual sensor data samples are transmitted without significant interference, exclusively at full Ethernet data rate. We provide a synchronous event model together with a straightforward response time analysis for synchronous multi-frame sample transmissions. The results show that worst-case latencies of such sample communication, in contrast to non-synchronized approaches, are close to their theoretical minimum as well as to simulative results while keeping the overall network utilization high.

Demonstration of an AI-driven workflow for autonomous high-resolution scanning microscopy

Modern scanning microscopes can image materials with up to sub-atomic spatial and sub-picosecond time resolutions, but these capabilities come with large volumes of data, which can be difficult to store and analyze. We report the Fast Autonomous Scanning Toolkit (FAST) that addresses this challenge by combining a neural network, route optimization, and efficient hardware controls to enable a self-driving experiment that actively identifies and measures a sparse but representative data subset in lieu of the full dataset. FAST requires no prior information about the sample, is computationally efficient, and uses generic hardware controls with minimal experiment-specific wrapping. We test FAST in simulations and a dark-field X-ray microscopy experiment of a WSe2 film. Our studies show that a FAST scan of <25% is sufficient to accurately image and analyze the sample. FAST is easy to adapt for any scanning microscope; its broad adoption will empower general multi-level studies of materials evolution with respect to time, temperature, or other parameters.

Information Communication Technology Tools for Animal Husbandry Technology Dissemination

In the Indian economy, the livestock sector contributes 4.9% of the overall GDP, accounting for around 30.13 per cent of the country's agricultural GDP. India has the worlds largest livestock population, but the average animal productivity is low; yet demand for livestock products is rising steadily, and customers’ awareness of quality has also increased. Therefore, it is necessary to refocus the production system by figuring out what information cattle farmers currently need. The animal husbandry department can only meet some livestock farmers' information needs. A multi-stakeholder online network across the livestock value chain is required to meet these information needs. Systems with ICT capabilities are better suited to deal with these problems. Radio, television, mobile, fixed, computer and network hardware and software, satellite systems, and video conferencing are all considered part of information and communication technology (ICT), a broad term covering any communication device or application. These include delivering information in the form of audio, data, video, and images, among other things. It is very beneficial for boosting the economy, creating jobs, developing rural areas, and reducing poverty. In modern times, ICT has become essential to the development of cattle. This article discusses using ICT technologies to spread animal husbandry technology among Indian farmers.

Design and Research of a Field Bus Control System Laboratory for Metal Mining, Beneficiation and Metallurgy

Fieldbus control systems play a pivotal role in industries such as mining, beneficiation, and metallurgy, facilitating precise process control. However, diverse process conditions and applications often lead to challenges during system implementation. The prevalence of process control projects underscores the need for dedicated control system laboratories to address these problems. Our research delves into the complexities of process control systems, focusing on mainstream brands such as Siemens, Rockwell, and Emerson, involving analysis of network architectures, software, and hardware configurations. Through rigorous testing of real equipment systems, we uncover prevalent issues in practical control system applications. These findings guide the resolution of technical challenges faced in project control, concurrently enhancing the design and debugging prowess of engineering professionals. We also anticipate the trajectory of intelligent manufacturing, embracing collaborative manufacturing aspects in networked environments. This research establishs a robust foundation for the forthcoming generation of control network technologies specific to metal mining, beneficiation, and metallurgy.

Offloading Machine Learning to Programmable Data Planes: A Systematic Survey

The demand for machine learning (ML) has increased significantly in recent decades, enabling several applications, such as speech recognition, computer vision, and recommendation engines. As applications become more sophisticated, the models trained become more complex while also increasing the amount of data used for training. Several domain-specific techniques can be helpful to scale machine learning to large amounts of data and more complex models. Among the methods employed, of particular interest is offloading machine learning functionality to the network infrastructure, which is enabled by the use of emerging programmable data plane hardware, such as SmartNICs and programmable switches. As such, offloading machine learning to programmable network hardware has attracted considerable attention from the research community in the last few years. This survey presents a study of programmable data planes applied to machine learning, also highlighting how in-network computing is helping to speed up machine learning applications. In this article, we provide various concepts and propose a taxonomy to classify existing research. Next, we systematically review the literature that offloads machine learning functionality to programmable data plane devices, classifying it based on our proposed taxonomy. Finally, we discuss open challenges in the field and suggest directions for future research.

Evaluation of error components in rainfall retrieval from collocated commercial microwave links

Abstract. Opportunistic rainfall sensing using commercial microwave links (CMLs) operating in telecommunication networks has the potential to complement conventional rainfall monitoring; however, the diversity of sensors and their errors are difficult to handle. This analysis empirically evaluates errors in CML observations that manifest discrepancies between collocated sensors without reference to rainfall measurements. Collocated CMLs are evaluated as independent rainfall sensors and enable us to assess the effect of hardware homogeneity and measurement consistency using CML observations at 12 sites within a real telecommunication network in Prague. The evaluation considers 33 rainfall events distinguishing between stratiform and convective rainfall types in the period of 2014–2016, monitored at 1 min temporal resolution. Collocated CMLs of identical and different frequencies are evaluated, and different rainfall types are discussed. The collocated CMLs are in excellent agreement. The inherent error in rain-induced attenuation for paired independent CMLs is 0.4 dB. The high correlation of the rainfall intensity measurements between the collocated sensors was obtained in a range of 0.96 to 0.99, and the root mean square error ranges from 0.4 to 1.7 mm h−1. This confirms the homogeneous behaviour of the hardware in a real network. Therefore, the data of CMLs of the same characteristics can be processed with identical parameters for rainfall retrieval models.

Programmable Energy-Efficient Analog Multilayer Perceptron Architecture Suitable for Future Expansion to Hardware Accelerators

A programmable, energy-efficient analog hardware implementation of a multilayer perceptron (MLP) is presented featuring a highly programmable system that offers the user the capability to create an MLP neural network hardware design within the available framework. In addition to programmability, this implementation provides energy-efficient operation via analog/mixed-signal design. The configurable system is made up of 12 neurons and is fabricated in a standard 130 nm CMOS process occupying approximately 1 mm2 of on-chip area. The system architecture is analyzed in several different configurations with each achieving a power efficiency of greater than 1 tera-operations per watt. This work offers an energy-efficient and scalable alternative to digital configurable neural networks that can be built upon to create larger networks capable of standard machine learning applications, such as image and text classification. This research details a programmable hardware implementation of an MLP that achieves a peak power efficiency of 5.23 tera-operations per watt while consuming considerably less power than comparable digital and analog designs. This paper describes circuit elements that can readily be scaled up at the system level to create a larger neural network architecture capable of improved energy efficiency.

Broadcast Propagation Time in SpaceFibre Networks with Various Types of Spatial Redundancy

Various methods of spatial redundancy can be used in local networks based on the SpaceFibre standard for fault mitigation of network hardware and physical communication channels. Usually, a network developer chooses the method of spatial redundancy according to the number of failures that have to be mitigated, the time required for restoring the normal operation of the network, required overheads and hardware costs. The use of different spatial redundancy mechanisms can cause changes in the structure of the links between network nodes, in case of failure and subsequent mitigation. In turn, this may cause changes in the broadcast transmission paths and the temporal characteristics of their delivery from the source to the receivers. This article focuses on the change in the propagation time of broadcasts in SpaceFibre networks with spatial redundancy. Broadcast propagation rules significantly differ from data-packet propagation rules. Broadcast distribution time is very important for many applications, because broadcasts are generally used to send urgent messages, in particular for time synchronization. Various formal methods have been used to evaluate the propagation characteristics of the broadcast. A method for estimating broadcast propagation time along the shortest routes is proposed. In addition, we provide a formal method to estimate the number of failures, which occurred in the network during the broadcast propagation. This method is based on timed Petri nets; one of its features is the ability to calculate broadcast transmission delays. In addition, as an alternative solution, we propose a method for estimating delays based on time automata theory.

Toolflow for the algorithm-hardware co-design of memristive ANN accelerators

The capabilities of artificial neural networks are rapidly evolving, so are the expectations for them to solve ever more challenging tasks in numerous everyday situations. Larger, more complex networks and the need to execute them efficiently on edge devices are the two counteracting requirements of this trend. Novel devices and computation techniques show promising characteristics to address this challenge. A huge design space covering different combinations of neural networks and hardware architectures using these technologies needs to be explored. An efficient design flow is, therefore, crucial for a good quality of service. This work reviews a wide range of simulation tools for novel memristive devices and analyzes their applicability for the design space exploration. A modular toolflow is proposed that shrinks down the large design space step-by-step using state-of-the-art optimization techniques and builds upon existing tools to find the best trade-offs between network accuracy and hardware requirements.

A High Performance Reconfigurable Hardware Architecture for Lightweight Convolutional Neural Network

Since the lightweight convolutional neural network EfficientNet was proposed by Google in 2019, the series of models have quickly become very popular due to their superior performance with a small number of parameters. However, the existing convolutional neural network hardware accelerators for EfficientNet still have much room to improve the performance of the depthwise convolution, squeeze-and-excitation module and nonlinear activation functions. In this paper, we first design a reconfigurable register array and computational kernel to accelerate the depthwise convolution. Next, we propose a vector unit to implement the nonlinear activation functions and the scale operation. An exchangeable-sequence dual-computational kernel architecture is proposed to improve the performance and the utilization. In addition, the memory architectures are designed to complete the hardware accelerator for the above computing architecture. Finally, in order to evaluate the performance of the hardware accelerator, the accelerator is implemented based on Xilinx XCVU37P. The results show that the proposed accelerator can work at the main system clock frequency of 300 MHz with the DSP kernel at 600 MHz. The performance of EfficientNet-B3 in our architecture can reach 69.50 FPS and 255.22 GOPS. Compared with the latest EfficientNet-B3 accelerator, which uses the same FPGA development board, the accelerator proposed in this paper can achieve a 1.28-fold improvement of single-core performance and 1.38-fold improvement of performance of each DSP.

OMPQ: Orthogonal Mixed Precision Quantization

To bridge the ever-increasing gap between deep neural networks' complexity and hardware capability, network quantization has attracted more and more research attention. The latest trend of mixed precision quantization takes advantage of hardware's multiple bit-width arithmetic operations to unleash the full potential of network quantization. However, existing approaches rely heavily on an extremely time-consuming search process and various relaxations when seeking the optimal bit configuration. To address this issue, we propose to optimize a proxy metric of network orthogonality that can be efficiently solved with linear programming, which proves to be highly correlated with quantized model accuracy and bit-width. Our approach significantly reduces the search time and the required data amount by orders of magnitude, but without a compromise on quantization accuracy. Specifically, we achieve 72.08% Top-1 accuracy on ResNet-18 with 6.7Mb parameters, which does not require any searching iterations. Given the high efficiency and low data dependency of our algorithm, we use it for the post-training quantization, which achieves 71.27% Top-1 accuracy on MobileNetV2 with only 1.5Mb parameters.

CNN Hardware Accelerator for Real-Time Bearing Fault Diagnosis

This paper introduces a one-dimensional convolutional neural network (CNN) hardware accelerator. It is crafted to conduct real-time assessments of bearing conditions using economical hardware components, implemented on a field-programmable gate array evaluation platform, negating the necessity to transfer data to a cloud-based server. The adoption of the down-sampling technique augments the visible time span of the signal in an image, thereby enhancing the accuracy of the bearing condition diagnosis. Furthermore, the proposed method of quaternary quantization enhances precision and shrinks the memory demand for the neural network model by an impressive 89%. Provided that the current signal data sampling rate stands at 64 K samples/s, the proposed design can accomplish real-time fault diagnosis at a clock frequency of 100 MHz. Impressively, the response duration of the proposed CNN hardware system is a mere 0.28 s, with the fault diagnosis precision reaching a remarkable 96.37%.

FPGA Implementation of Keyword Spotting System Using Depthwise Separable Binarized and Ternarized Neural Networks.

Keyword spotting (KWS) systems are used for human-machine communications in various applications. In many cases, KWS involves a combination of wake-up-word (WUW) recognition for device activation and voice command classification tasks. These tasks present a challenge for embedded systems due to the complexity of deep learning algorithms and the need for optimized networks for each application. In this paper, we propose a depthwise separable binarized/ternarized neural network (DS-BTNN) hardware accelerator capable of performing both WUW recognition and command classification on a single device. The design achieves significant area efficiency by redundantly utilizing bitwise operators in the computation of the binarized neural network (BNN) and ternary neural network (TNN). In a complementary metal-oxide semiconductor (CMOS) 40 nm process environment, the DS-BTNN accelerator demonstrated significant efficiency. Compared with a design approach where BNN and TNN were independently developed and subsequently integrated as two separate modules into the system, our method achieved a 49.3% area reduction while yielding an area of 0.558 mm2. The designed KWS system, which was implemented on a Xilinx UltraScale+ ZCU104 field-programmable gate array (FPGA) board, receives real-time data from the microphone, preprocesses them into a mel spectrogram, and uses this as input to the classifier. Depending on the order, the network operates as a BNN or a TNN for WUW recognition and command classification, respectively. Operating at 170 MHz, our system achieved 97.1% accuracy in BNN-based WUW recognition and 90.5% in TNN-based command classification.

Lessons Learned in Change Management in Deploying Novel Informatics Solutions: Experience Implementing a Point-of-Care Patient Photography System with Radiography

We describe implementation of a point-of-care system for simultaneous acquisition of patient photographs along with portable radiographs at a large academic hospital. During the implementation process, we observed several technical challenges in the areas of (1) hardware—automatic triggering for photograph acquisition, camera hardware enclosure, networking, and system server hardware and (2) software—post-processing of photographs. Additionally, we also faced cultural challenges involving workflow issues, communication with technologists and users, and system maintenance. We describe our solutions to address these challenges. We anticipate that these experiences will provide useful insights into deploying and iterating new technologies in imaging informatics.

AI-On-Skin: Towards Enabling Fast and Scalable On-body AI Inference for Wearable On-Skin Interfaces

Existing artificial skin interfaces lack on-skin AI compute that can provide fast neural network inference for time-critical applications. In this paper, we propose AI-on-skin - a wearable artificial skin interface integrated with a neural network hardware accelerator that can be reconfigured to run diverse neural network models and applications. AI-on-skin is designed to scale to the entire body, comprising tiny, low-power, accelerators distributed across the body. We built 7 AI-on-Skin application prototypes and our user trials show AI-On-Skin achieving 20X and 50X speedup over off-body inference via Bluetooth and on-body centralized microprocessor based inference approach respectively. We also project the power performance of AI-on-skin with our accelerator fabricated as silicon chips instead of emulated on FPGAs and show 10X further power savings. To the best of our knowledge, AI-on-Skin is the first ever wearable prototype to demonstrate skin interfaces with on-body AI inference.

Predicting Network Hardware Faults through Layered Treatment of Alarms Logs.

Maintaining and managing ever more complex telecommunication networks is an increasingly difficult task, which often challenges the capabilities of human experts. There is a consensus both in academia and in the industry on the need to enhance human capabilities with sophisticated algorithmic tools for decision-making, with the aim of transitioning towards more autonomous, self-optimizing networks. We aimed to contribute to this larger project. We tackled the problem of detecting and predicting the occurrence of faults in hardware components in a radio access network, leveraging the alarm logs produced by the network elements. We defined an end-to-end method for data collection, preparation, labelling, and fault prediction. We proposed a layered approach to fault prediction: we first detected the base station that is going to be faulty and at a second stage, and using a different algorithm, we detected the component of the base station that is going to be faulty. We designed a range of algorithmic solutions and tested them on real data collected from a major telecommunication operator. We concluded that we are able to predict the failure of a network component with satisfying precision and recall.

Machine Learning-Based Anomaly Detection in NFV: A Comprehensive Survey.

Network function virtualization (NFV) is a rapidly growing technology that enables the virtualization of traditional network hardware components, offering benefits such as cost reduction, increased flexibility, and efficient resource utilization. Moreover, NFV plays a crucial role in sensor and IoT networks by ensuring optimal resource usage and effective network management. However, adopting NFV in these networks also brings security challenges that must promptly and effectively address. This survey paper focuses on exploring the security challenges associated with NFV. It proposes the utilization of anomaly detection techniques as a means to mitigate the potential risks of cyber attacks. The research evaluates the strengths and weaknesses of various machine learning-based algorithms for detecting network-based anomalies in NFV networks. By providing insights into the most efficient algorithm for timely and effective anomaly detection in NFV networks, this study aims to assist network administrators and security professionals in enhancing the security of NFV deployments, thus safeguarding the integrity and performance of sensors and IoT systems.

PTA: Finding Hard-to-Find Data Plane Bugs

Bugs in network hardware can cause tremendous problems. However, programmable network devices have the potential to provide greater visibility into the internal behavior of devices, allowing us to more quickly find and identify problems. In this paper, we provide a taxonomy of data plane bugs, and use the taxonomy to derive a Portable Test Architecture (PTA) which offers essential abstractions for testing on a variety of network hardware devices. PTA is implemented with a novel data plane design that (i) separates target-specific from target-independent components, allowing for portability, and (ii) allows users to write a test program once at compile time, but dynamically alter the behavior via runtime configuration. We report 12 diverse bugs on different hardware targets, and their associated software, exposed using PTA.

Metodologia utilizării software-ului specializat în procesul de studiere a rețelelor de calculatoare

The article proposes didactic and technical tools for studying the Computer Networks course, taught at university computer science majors. The Computer Networks course is essential for future computer science majors, but has a strong practical aspect and requires specialized network simulation software and hardware, often inaccessible to students.