Hardware Interrupt Research Articles

Kernel vs. User-Level Networking: Don't Throw Out the Stack with the Interrupts

This paper reviews the performance characteristics of network stack processing for communication-heavy server applications. Recent literature often describes kernel-bypass and user-level networking as a silver bullet to attain substantial performance improvements, but without providing a comprehensive understanding of how exactly these improvements come about. We identify and quantify the direct and indirect costs of asynchronous hardware interrupt requests (IRQ) as a major source of overhead. While IRQs and their handling have a substantial impact on the effectiveness of the processor pipeline and thereby the overall processing efficiency, their overhead is difficult to measure directly when serving demanding workloads. This paper presents an indirect methodology to assess IRQ overhead by constructing preliminary approaches to reduce the impact of IRQs. While these approaches are not suitable for general deployment, their corresponding performance observations indirectly confirm the conjecture. Based on these findings, a small modification of a vanilla Linux system is devised that improves the efficiency and performance of traditional kernel-based networking significantly, resulting in up to 45% increased throughput without compromising tail latency. In case of server applications, such as web servers or Memcached, the resulting performance is comparable to using kernel-bypass and user-level networking when using stacks with similar functionality and flexibility.

Kernel vs. User-Level Networking: Don't Throw Out the Stack with the Interrupts

This paper reviews the performance characteristics of network stack processing for communication-heavy server applications. Recent literature often describes kernel-bypass and user-level networking as a silver bullet to attain substantial performance improvements, but without providing a comprehensive understanding of how exactly these improvements come about. We identify and quantify the direct and indirect costs of asynchronous hardware interrupt requests (IRQ) as a major source of overhead. While IRQs and their handling have a substantial impact on the effectiveness of the processor pipeline and thereby the overall processing efficiency, their overhead is difficult to measure directly when serving demanding workloads. This paper presents an indirect methodology to assess IRQ overhead by constructing preliminary approaches to reduce the impact of IRQs. While these approaches are not suitable for general deployment, their corresponding performance observations indirectly confirm the conjecture. Based on these findings, a small modification of a vanilla Linux system is devised that improves the efficiency and performance of traditional kernel-based networking significantly, resulting in up to 45% increased throughput without compromising tail latency. In case of server applications, such as web servers or Memcached, the resulting performance is comparable to using kernel-bypass and user-level networking when using stacks with similar functionality and flexibility.

Security Analysis of Zigbee Protocol Implementation via Device-agnostic Fuzzing

Zigbee is widely adopted as a resource-efficient wireless protocol in the IoT network. IoT devices from manufacturers have recently been affected due to major vulnerabilities in Zigbee protocol implementations. Security testing of Zigbee protocol implementations is becoming increasingly important. However, applying existing vulnerability detection techniques such as fuzzing to the Zigbee protocol is not a simple task. Dealing with low-level hardware events still remains a big challenge. For the Zigbee protocol, which communicates over a radio channel, many existing protocol fuzzing tools lack a sufficient execution environment. To narrow the gap, we designed Z-Fuzzer , a device-agnostic fuzzing tool for detecting security flaws in Zigbee protocol implementations. To simulate Zigbee protocol execution, Z-Fuzzer leverages a commercial embedded device simulator with pre-defined peripherals and hardware interrupt setups to interact with the fuzzing engine. Z-Fuzzer generates more high-quality test cases with code-coverage heuristics. We compare Z-Fuzzer with advanced protocol fuzzing tools, BooFuzz and Peach fuzzer, on top of Z-Fuzzer’s simulation platform. Our findings suggest that Z-Fuzzer can achieve greater code coverage in Z-Stack, a widely used Zigbee protocol implementation. Compared to BooFuzz and Peach, Z-Fuzzer found more vulnerabilities with fewer test cases. Three of them have been assigned CVE IDs with high CVSS scores (7.5~8.2).

SMU Open-Source Platform for Synchronized Measurements.

The ramping trend of cheap and performant single board computers (SBC) is growingly offering unprecedented opportunities in various domains, taking advantage of the widespread support and flexibility offered by an operating system (OS) environment. Unfortunately, data acquisition systems implemented in an OS environment are traditionally considered not to be suitable for reliable industrial applications. Such a position is supported by the lack of hardware interrupt handling and deterministic control of timed operations. In this study, the authors fill this gap by proposing an innovative and versatile SBC-based open-source platform for CPU-independent data acquisition. The synchronized measurement unit (SMU) is a high-accuracy device able to perform multichannel simultaneous sampling up to 200 kS/s with sub-microsecond synchronization precision to a GPS time reference. It exhibits very low offset and gain errors, with a minimum bandwidth beyond 20 kHz, SNR levels above 90 dB and THD as low as −110 dB. These features make the SMU particularly attractive for the power system domain, where synchronized measurements are increasingly required for the geographically distributed monitoring of grid operating conditions and power quality phenomena. We present the characterization of the SMU in terms of measurement and time synchronization accuracy, proving that this device, while low-cost, guarantees performance compliant with the requirements for synchrophasor-based applications in power systems.

거친 환경에 최적화된 가속도계 무선 데이터 로깅모듈

A wireless data logging system connected with accelerometer was developed for measuring vibration in harsh environment where conventional vibration equipment could not be used, e.g., on deck of the battleship, surface of the submarine or airplane, etc. To minimize wired connections, the module used a battery to supply power, and the data was recorded by the module itself on the SD card. Data logging was carried out through Arduino. Because the voltage levels of the accelerometers were different, the internal circuits were adjusted by changing the voltage levels through level shifting. Data logging was optimized using the hardware interrupt and double buffering to maintain a constant sampling rate during data logging and to prevent loss of data. The vibration data obtained through the manufactured module was compared with data measured by LMS test to confirm the validity of the signal. It was also confirmed that the module measurement data was normal even during long-time measurements.

The Derivation of Defect Priorities and Core Defects through Impact Relationship Analysis between Embedded Software Defects

As embedded software is closely related to hardware equipment, any defect in embedded software can lead to major accidents. Thus, all defects must be collected, classified, and tested based on their severity. In the pure software field, a method of deriving core defects already exists, enabling the collection and classification of all possible defects. However, in the embedded software field, studies that have collected and categorized relevant defects into an integrated perspective are scarce, and none of them have identified core defects. Therefore, the present study collected embedded software defects worldwide and identified 12 types of embedded software defect classifications through iterative consensus processes with embedded software experts. The impact relation map of the defects was drawn using the decision-making trial and evaluation laboratory (DEMATEL) method, which analyzes the influence relationship between elements. As a result of analyzing the impact relation map, the following core embedded software defects were derived: hardware interrupt, external interface, timing error, device error, and task management. All defects can be tested using this defect classification. Moreover, knowing the correct test order of all defects can eliminate critical defects and improve the reliability of embedded systems.

On-Chip Analog Trojan Detection Framework for Microprocessor Trustworthiness

With the globalization of semiconductor industry, hardware security issues have been gaining increasing attention. Among all hardware security threats, the insertion of hardware Trojans is one of the main concerns. Meanwhile, many current Trojan detection solutions follow the assumption that the hardware Trojan itself should be composed of digital logic. This assumption is invalidated by recently proposed analog Trojans which are extremely small and can detect rare events. This paper proposes a runtime hardware Trojan detection method which is geared toward detecting such advanced Trojans. The principle of this method is to guard a set of concerned signals, and initiate a hardware interrupt request when abnormal toggling events occur in these guarded signals. To prove the effectiveness of this method, we design a processor based on ARMv7-A&R ISA, and insert an analog Trojan into the processor. We fabricated the design in an SMIC 130-nm process and demonstrate the effectiveness of the proposed methodology.

Embedded Systems: Teaching and Design Challenges for Nonhomogeneous Classes

The growth of technology leads the industry to move beyond and crosses the boundaries of its own disciplines. The changes from pure mechanical system, to electronics systems and the integration with control software brings new challenges to the engineers working in the industry and to the source shaped the engineers. As a result, institutes of higher education need to make the necessary changes to meet this continuing market demands. This work address the issue and describes a new systematic and an effective approach for teaching hardware based courses for large non-homogenous (Computer Science and Electronics students) class setting using existing e-learning system in the university to promote powerful, long-lasting learning outcomes. It is a blend of several approaches with an insightful goal to provoke deeper understanding in various topics in microprocessors and microcontrollers details, intended to teach the computer science students to learn low-level hardware interfacing, interrupt handling, and other microprocessors issues, as well as embedded systems through learning microcontrollers. Our methodology revolute around three steps: using visual simulators, incrementally weighted exercises, from easiest to hardest, and finally working on real hardware controllers. The proposed approaches developed for the course “Embedded Controller Technology”, but any other hardware based course can apply them. The approach comprises a 3-hour a week lecture and 2-hour a week laboratory, both taught in the 3rd semester. Imposing the approach leads to the overall improvement of the course quality: student satisfaction and interest, increased number of completed hardware projects and significant improvement in grade distribution and it has been observed that students feel better prepared to face the challenges to be found in their future professional activities.

Live-Out Register Fencing

This article introduces Live-Out Register Fencing (LoRF), a soft error correction mechanism that uses the novel Spill Register File as a container of checkpointing data. LoRF’s Spill Register File holds the values shared among basic blocks in the program, and, coupled with a new compilation strategy, LoRF allows for error correction in the same basic block where the error was detected. In LoRF, error correction is triggered by a hardware interrupt that restores the registers of a basic block from the Spill Register File. After these registers are restored, the basic block where the error was detected can just be re-executed, thus reducing the costs of error recovery. LoRF’s error correction policy eliminates the need for expensive architectural support for checkpointing and rollback, reducing the performance overhead of online soft error correction. LoRF relies on both a modified processor architecture and a corresponding compiler. The architecture was implemented in synthesizable VHDL, whereas the compiler was developed as an extension of the LLVM framework. Fault injection experiments support an error correction coverage of 99.35% and a mean performance overhead of 1.33 for the entire life cycle of an error from its occurrence to its elimination from the system.

Hardware support for memory protection in sensor nodes

With reference to the typical hardware configuration of a sensor node, we present the architecture of a memory protection unit (MPU) designed as a low-complexity addition to the microcontroller. The MPU is aimed at supporting memory protection and the privileged execution mode. It is connected to the system buses, and is seen by the processor as a memory-mapped input/output device. The contents of the internal MPU registers specify the composition of the protection contexts of the running program in terms of access rights for the memory pages. The MPU generates a hardware interrupt to the processor when it detects a protection violation. The proposed MPU architecture is evaluated from a number of salient viewpoints, which include the distribution, review and revocation of access permissions, and the support for important memory protection paradigms, including hierarchical contexts and protection rings.

Full Software CNC System Based on RTLinux

In order to meet the real-time performance of the full software CNC system, the full software CNC based on RTLinux is designed. Linux+RTLinux system is used as development platform, the timer parameter is changed by the method of hardware interrupt, and the real-time requirement of the CNC system is solved. The idea of modular design is used on CNC system to divide the function module, and the software design of the full software CNC system based on RTLinux is completed. C language is used as the main development language, the development of functional modules of the system management layer and the control layer is realized. Linear, circular interpolation function of CNC system can be realized.

저가의 소형 PCR 장치를 위한 펌웨어 설계 및 구현

In this paper, we design and implement a firmware for low-cost small PCR devices. To minimize machine code size, the proposed firmware controls real-time tasks simultaneously only with support of the hardware interrupt, but without support of the operating system program. The proposed firmware has the host-local structure in which the firmware receives operation commands from PC and sends operation results to PC through usb communication. We implement a low-cost small PCR device with the proposed firmware loaded on microchip PIC18F4550 chip, and verify that the implemented PCR device significantly reduces cost and volume size of existing commercial PCR devices with a similar performance.

Research of Comparison Circular Interpolation on WINCE

Up to now lots of CNC system used traditional DOS to realize real time control by hardware interrupt programming. To make computer numerical control system flexible and open can meet requirements of higher real-time. This paper used ARM9 processor S3C2410A with the RISC system of SAMSUNG Company, and realized precise interpolation of NC interpolation by the way of software on EVC platform with the aid of WinCE OS. Coupled with the motor drive module, it can achieve a simple NC function of four quadrant arc interpolation will be realized by programming used by point-by-point comparison method.

Design of Touch Screen Driver Based on Linux

This paper introduces the touch screen driver design based on Linux plays an important role in applications of touch screen. In order to further explore embedded touch screen driver design, and then optimize and improve existing drivers at practice level, this paper accomplished the design of touch screen driver using SPI interface and ADS7843 touch screen chip controller based on Samsung S3C2410s microprocessor. We designed the touch screen hardware interrupt program using the bottom half mechanism of the kernel timer, utilized 16 clock cycles of coordinate conversion sequences to achieve touch point based data acquisition and present the process of coordinate collection. The touch screen driver ran well on the UP-NETARM2410-S platform. The hardware design was verified to be simple and reliable while the corresponding software accomplished touch state detection and touch data conversion efficiently. The touch screen control method is simple, efficient and easy to realize.

Dynamic and adaptive SPM management for a multi-task environment

In this paper, we present a dynamic and adaptive scratchpad memory (SPM) management strategy targeting a multi-task environment. It can be applied to a contemporary embedded processor that maps the physically addressed SPM into a virtual space with the help of an integrated memory management unit (MMU). Based on mass-count disparity, we introduce a hardware memory reference sampling unit (MRSU) that samples the memory reference stream with very low probability. The captured address is considered as one of the memory addresses contained in a frequently referenced memory block. A hardware interruption is generated by the MRSU, and the identified frequently accessed memory block is placed into the SPM space by software. The software also modifies the page table so that the follow-up memory accesses to the memory block will be redirected to the SPM. With no dependence on compiler and profiling information, our proposed strategy is specifically adequate for SPM management in a multi-task environment. In such an environment, a real-time operating system (RTOS) is usually hosted, and the behavior of the memory accesses cannot be predicted by static analysis or profiling. We evaluate our SPM allocation strategy by running several tasks on a tiny RTOS with preemptive scheduling. Experimental results show that our approach can achieve 10% reduction in energy consumption on average, with 1% performance degradation at runtime compared with a cache-only reference system.

Integrating firewire peripheral interface with an ethernet custom network processor

Bandwidth demands on ubiquitous Ethernet have grown immensely, driven by the rapid expansion of real-time applications like audio/video streaming. In a related research, the authors designed a novel high-performance custom network processor chip using field programmable gate arrays (FPGAs). The main function of this chip (named SPEED) is to bypass the operating system processing of network protocol stack at the host computer by off-loading its networking functions to hardware. This simplification is not only required to fit in a hardware solution, but also it improves network performance. The novel chip utilizes the concept of Ethernet channels, where Ethernet frames are addressed in a multicast addressing scheme. In this article, we integrate the chip with a Firewire peripheral interface (FPI). A crucial function of the FPI design is to convert the IEEE 1394 isochronous traffic to the Ethernet frame format via two independent asynchronous write and read buffers. The FPI also manages the SPEED hardware interrupt signals in a bi-directional communication scheme. The goal of this research is to map isochronous Firewire packets into Ethernet frames by utilizing the SPEED Ethernet channel assignment capability. We used Verilog Hardware Description Language (HDL) to synthesize the FPI design. Since the FPI needs to support bi-directional communication, we also present a generic HDL model for bi-directional data sharing, which can be used in similar bi-directional applications. Initial performance measures show that the FPI consumes less that 0.15 W of power. Also we found that the synthesized design utilizes only 28% of the target chip resources. Hence it was possible to incorporate it with the SPEED design in the same FPGA chip. This low power consumption will lead to powering SPEED-FPI based network devices through the network cable and eliminate the process of regular electrical power outlet installations and maintenance. Thus, the SPEED-FPI system reduces the installation complexity, especially for large number of devices (e.g., surveillance cameras).

Digital firing and digital control of a photovoltaic inverter

A photovoltaic (PV) system is connected to the utility grid via a line-commutated thyristorized inverter. The inverter is controlled by a digital controller and fired by a digital firing technique using a microcomputer. This leads to a high firing resolution and synchronization, minimizing the hardware circuitry, and enhancing system reliability. Also we used two hardware interrupt requests to save more time for other tasks for the computer.

General purpose data acquisition and control via the IBM PC Centronics printer port

This paper describes a novel system for acquiring data and controlling equipment via the parallel port of an IBM PC or compatible. An inexpensive circuit and associated computer software are described which allow up to 256, eight-bit, digital input and output devices, together with eight hardware interrupt request lines, to be accessed via the Centronics parallel printer port. Programs can access the external devices via a software interrupt into a memory resident driver program. This allows all common programming languages to make use of the system. Data transfer speeds of over 40 000 reads/writes per second are achieved. .

Using PC system timer to time software execution

PC has a system timer which can be used to do software benchmarking (timing) or to time intervals during laboratory experiments. The timer 8253 4 which runs at 1·19318 MHz should theoretically be able to time intervals of 0·838095 μs at very high precision. In practice, its accuracy is affected by many factors including: interference from system memory refreshment, uncertainty in response to hardware interrupt and the delay caused by updating timer software. This paper is an attempt to evaluate the magnitude of these effects. The effect of the instruction prefetching and pipelining of 8088/80286/80386 processors is also discussed. It is found that in spite of its many limitations, the system timer can provide timing with a fairly high degree of accuracy if proper precautions are taken.

A simple Turbo Pascal 4.0 program for millisecond timing on the IBM PC/XT/AT

The ffiM PC has become the de facto standard computer for use in psychology laboratories, and Turbo Pascal is a very popular language for this purpose. Unfortunately, no simple millisecond timing program is available in Turbo Pascal. Heathcote (1988) presented a Turbo Pascal program for this purpose, but it is complex and adversely affects the time of day (TOD) clock. Other programs are available only in BASIC and in assembly language, and therefore they cannot be incorporated directly into Turbo Pascal programs (e.g., see Buhrer, Sparrer, & Weitkunat, 1987; Graves & Bradley, 1987, 1988). In the present paper, a program is described that performs millisecond interval timing for the ffiM PC family of computers simply, neatly, efficiently, and accurately, entirely within Turbo Pascal 4.0. Millisecond timing. On the ffiM PC, XT, and AT, as well as compatibles, system timing (e.g., RAM refresh and updating the TOD clock) is performed by the Intel 8253 timer/counter provided on the motherboard. Regardless of the computer (i.e., PC, XT, or AT) and central processor speed (i.e., 4.77, 6, 8, 10, or 20 MHz), the 8253 timer/counter always operates at 1,193,182 Hz, with one count for every cycle. In normal operation, the TOD clock is updated every 65,536 counts of the 8253 timerthat is, every 54.925 msec. One way to obtain millisecond timing is to program the 8253 timer to update the TOD clock every 1,193 counts (i.e., approximately every millisecond) and then count the number of times the TOD clock is updated during the timing interval. However, because the BIOS assumes that a TOD update occurs every 55 msec, the TOD clock will run 55 times too fast (see Biihrer et al., 1987, and Heathcote, 1988, for examples of this type of algorithm). The 8253 is initialized with an integer between 1 and 65,536, then it repeatedly counts down from this number to O. When the counter reaches 0, three things happen automatically: (1) hardware Interrupt 8 updates the TOD clock, (2) software Interrupt 28 (lC in Hexadecimal) is executed, and (3) the counter is reset to the initial number and the countdown continues. In normal operation, Interrupt 1C does nothing useful, but it can be modified