Hardware Implementation Of Algorithm Research Articles

Hardware Implementation of a Real-Time Data Processing Algorithm in Marine Engineering Data Acquisition

According to the architecture characteristics of the mass data acquisition system in marine seismic exploration, this paper designed a real-time data processing algorithm which can convert the collected time-sequence data to channel-sequence data. A hardware implementation of the algorithm based on FPGA+DDR SDRAM is developed to complete the whole conversion process. Here, FPGA is used to achieve time sequence data receiving, analyzing, preliminary processing and the interface to DDR SDRAM. Two DDR SDRAM’s are used in ping-pang mode to store time-sequence data and to cooperate with FPGA in realizing time-to-channel sequence data conversion. Test results showed that, after applying the algorithm to the FCI in high-precision marine seismic data acquisition and recording system, this arithmetic could realize caching collected data without redundancy and converting data from time sequence to channel sequence without dead time, besides, this algorithm also greatly improved the efficiency and reliability of data processing.

Manipulation of a Pneumatic Hyper-Redundant Actuator

Pneumatically controlled and actuated planar snake-like device has been developed. Each joint is controlled by hardware-implemented algorithm inspired by snake's lateral undulatory locomotion. Therefore the device progresses forward whenever the lateral movement is constrained, such as a winding groove by which the tip element is guided. Without lateral constraint, the device behaves like a elephant trunk. This paper focuses on the behavior as an manipulator. Endoscopic manipulation through a complicated cavity is demonstrated by experiments.

Errata: Hardware implementation algorithm and error analysis of high-speed fluorescence lifetime sensing systems using center-of-mass method

Errata: Hardware implementation algorithm and error analysis of high-speed fluorescence lifetime sensing systems using center-of-mass method

Hardware implementation algorithm and error analysis of high-speed fluorescence lifetime sensing systems using center-of-mass method

A new, simple, high-speed, and hardware-only integration-based fluorescence-lifetime-sensing algorithm using a center-of-mass method (CMM) is proposed to implement lifetime calculations, and its signal-to-noise-ratio based on statistics theory is also deduced. Compared to the commonly used iterative least-squares method or the maximum-likelihood-estimation-based, general purpose fluorescence lifetime imaging microscopy (FLIM) analysis software, the proposed hardware lifetime calculation algorithm with CMM offers direct calculation of fluorescence lifetime based on the collected photon counts and timing information provided by in-pixel circuitry and therefore delivers faster analysis for real-time applications, such as clinical diagnosis. A real-time hardware implementation of this CMM FLIM algorithm suitable for a single-photon avalanche diode array in CMOS imaging technology is now proposed for implementation on field-programmable gate array. The performance of the proposed methods has been tested on Fluorescein, Coumarin 6, and 1,8-anilinonaphthalenesulfonate in water/methanol mixture.

An efficient hardware-optimized compression algorithm for wireless capsule endoscopy image transmission

A dedicated image compression algorithm was developed for wireless capsule endoscopy (WCE). The proposed approach reduces the amount image data without compromising the image quality. This allows an increase in image throughput to improve the real-time vision capabilities of a WCE system. The algorithm is based on a normalized Haar-wavelet transformation, aiming at a hardware-optimized implementation in a low-power FPGA or telemetry ASIC for wireless capsule endoscopes. Taking advantage of the limited color content of endoscopic images, this solution uses the YCbCr color space combined with efficient recoding of the wavelet transformation data. In this way adequate compression ratios at decent image qualities can be achieved in a hardware efficient thus low power implementation, outperforming existing hardware implemented algorithms.

Design and Implementation of a Fuzzy-Modified Ant Colony Hardware Structure for Image Retrieval

In this paper, a hardware implementation of a fuzzy modified ant colony processor that is suitable for image retrieval is presented for the first time. The proposed method utilizes three different descriptors in a two stage fuzzy ant algorithm where the query image represents the nest and the database images represent the food. From the hardware point of view, only a small number of algorithms for hardware implementation have been reported in the image retrieval literature, since research focuses mainly on possible software solutions and the acceleration of existing algorithms. The proposed digital hardware structure is based on a sequence of pipeline stages, while parallel processing is also used in order to minimize computational times. It is capable of performing the extraction and comparison of features from (64times64)-pixel-size color images, although through a simple transformation it can be easily expanded to accommodate images of larger sizes. The architecture of the processor is generic; the units that perform the fuzzy inference can be used with different descriptors than the ones proposed here and can be utilized for other fuzzy applications. It was designed, compiled, and simulated using the Quartus Programmable Logic Development System by the Altera Corporation. The fuzzy processor exhibits a level of inference performance of 800 K fuzzy logic inferences per second with 24 rules, and can be used for real-time applications where the need for short processing times is of the utmost importance.

Peptide Mass Fingerprinting Using Field-Programmable Gate Arrays

The reconfigurable computing paradigm, which exploits the flexibility and versatility of field-programmable gate arrays (FPGAs), has emerged as a powerful solution for speeding up time-critical algorithms. This paper describes a reconfigurable computing solution for processing raw mass spectrometric data generated by MALDI-TOF instruments. The hardware-implemented algorithms for denoising, baseline correction, peak identification, and deisotoping, running on a Xilinx Virtex-2 FPGA at 180 MHz, generate a mass fingerprint that is over 100 times faster than an equivalent algorithm written in C, running on a Dual 3-GHz Xeon server. The results obtained using the FPGA implementation are virtually identical to those generated by a commercial software package MassLynx.

Efficient Modular Squaring Algorithms for Hardware Implementation in GF(p)

ABSTRACT Some of the most popular public key encryption algorithms use exponentiation as their core operation, which can be mostly broken into several modular squaring operations. In this paper, we present GF(p) modular squaring algorithms and efficiently implement them on hardware. We present different algorithms, two for squaring and one for reduction combined with the squaring, to provide a general modular squaring algorithm. The algorithms are implemented through datapaths that uses redundant Carry-Save Adders, making the computation time independent form the operands precision. The proposed algorithms are compared with each other as well as with the existing modular squaring algorithms. The experimental results are obtained by synthesizing the hardware designs for FPGA Virtex5 chip (xc5vlx50 – ff1153 technology), which showed interesting results and made our ideas very attractive.

Hardware acceleration of processing of mass spectrometric data for proteomics

High-resolution mass spectrometers generate large data files that are complex, noisy and require extensive processing to extract the optimal data from raw spectra. This processing is readily achieved in software and is often embedded in manufacturers' instrument control and data processing environments. However, the speed of this data processing is such that it is usually performed off-line, post data acquisition. We have been exploring strategies that would allow real-time advanced processing of mass spectrometric data, making use of the reconfigurable computing paradigm, which exploits the flexibility and versatility of Field Programmable Gate Arrays (FPGAs). This approach has emerged as a powerful solution for speeding up time-critical algorithms. We describe here a reconfigurable computing solution for processing raw mass spectrometric data generated by MALDI-ToF instruments. The hardware-implemented algorithms for de-noising, baseline correction, peak identification and deisotoping, running on a Xilinx Virtex 2 FPGA at 180 MHz, generate a mass fingerprint over 100 times faster than an equivalent algorithm written in C, running on a Dual 3 GHz Xeon workstation.

Arithmetic Precision of the Generalized Hebbian Algorithm for Hardware Implementation

Arithmetic Precision of the Generalized Hebbian Algorithm for Hardware Implementation

The hardware-based implementation of the colour palette generation stage of a colour image quantization algorithm

Many techniques have been proposed to quantize a digital colour image in order to reduce the representative number of colours to be suitable for presenting on different type of display screens. Most of the techniques are targeted for implementation on a general purpose multitasking computer with low restriction on resource utilization. The drawback of these techniques relies on the fact that they cannot fulfil the requirement of some applications with real-time constraint and limited resources. In this paper, the most suitable algorithm for hardware implementation is reviewed and the details of its implementation and experimentation which is focused on the colour palette generation stage are presented. The implementation given in this paper is for use in construction of colour palette image compression for real-time transferring of video data to an LED display board. It can also be adapted to use as a dedicated computer hardware for other real-time image compression applications.

AN FPGA IMPLEMENTATION OF THE GPRS ENCRYPTION ALGORITHM 3 (GEA3)

The General Packet Radio Service (GPRS) uses the GPRS Encryption Algorithm 3 (GEA3) for data encryption. In this paper, alternative hardware implementations of the GEA3 algorithm are described. GEA3 algorithm is based on the KASUMI block cipher. Various KASUMI block cipher hardware implementations have been examined in order to provide information about the required silicon area and throughput. In order to achieve a significant performance improvement, Double Edge Triggered pipeline technique is used. The S-BOXes, which are fundamental elements of the KASUMI cipher, have been implemented by using combinational logic and ROM memories. The proposed GEA3 algorithm hardware implementation achieves throughput up to 837Mbps, which is much faster comparing to the previous designs. The whole system is implemented and evaluated by using Field Programmable Gate Array (FPGA) devices.

The UCSC Kestrel parallel processor

The architectural landscape of high-performance computing stretches from superscalar uniprocessor to explicitly parallel systems, to dedicated hardware implementations of algorithms. Single-purpose hardware can achieve the highest performance and uniprocessors can be the most programmable. Between these extremes, programmable and reconfigurable architectures provide a wide range of choice in flexibility, programmability, computational density, and performance. The UCSC Kestrel parallel processor strives to attain single-purpose performance while maintaining user programmability. Kestrel is a single-instruction stream, multiple-data stream (SIMD) parallel processor with a 512-element linear array of 8-bit processing elements. The system design focuses on efficient high-throughput DNA and protein sequence analysis, but its programmability enables high performance on computational chemistry, image processing, machine learning, and other applications. The Kestrel system has had unexpected longevity in its utility due to a careful design and analysis process. Experience with the system leads to the conclusion that programmable SIMD architectures can excel in both programmability and performance. This work presents the architecture, implementation, applications, and observations of the Kestrel project at the University of California at Santa Cruz.

Experiences on developing computer vision hardware algorithms using Xilinx system generator

Computer vision is one of the areas where hardware-implemented algorithms perform clearly better than those implemented via software. Digital designers have so far optimized their designs by means of application specific integrated circuits (ASICs) or digital signal processors (DSPs). However, nowadays they are increasingly using field programmable gate arrays (FPGAs), powerful hardware devices combining the main advantages of ASICs and DSPs with the possibility of re-programming, which make them very attractive devices for rapid prototyping. This paper shows how the Xilinx system generator (XSG) environment can be used to develop hardware-based computer vision algorithms from a system level approach, which makes it suitable for developing co-design environments.

64-bit Block ciphers: hardware implementations and comparison analysis

A performance comparison for the 64-bit block cipher (Triple-DES, IDEA, CAST-128, MISTY1, and KHAZAD) FPGA hardware implementations is given in this paper. All these ciphers are under consideration from the ISO/IEC 18033-3 standard in order to provide an international encryption standard for the 64-bit block ciphers. Two basic architectures are implemented for each cipher. For the non-feedback cipher modes, the pipelined technique between the rounds is used, and the achieved throughput ranges from 3.0Gbps for IDEA to 6.9Gbps for Triple-DES. For feedback ciphers modes, the basic iterative architecture is considered and the achieved throughput ranges from 115Mbps for Triple-DES to 462Mbps for KHAZAD. The throughput, throughput per slice, latency, and area requirement results are provided for all the ciphers implementations. Our study is an effort to determine the most suitable algorithm for hardware implementation with FPGA devices.

Implementation of Fuzzy Systems using Micro Processors/Controllers

This paper presents an algorithm for implementation of fuzzy systems using inexpensive general-purpose hardware. The two major difficulties encountered in implementing fuzzy systems using 8/16 bit micro processors/controllers are: (i) handling floating point arithmetic and (ii) determination of membership values. Existing membership functions (mfs) do not satisfy, simultaneously, ease in optimization and low-end hardware implementation. Mfs, recently proposed by us [1], as negative powers of 2 satisfy these two contradicting requirements. The complete algorithm for hardware implementation of the best offline design solution is described. The worst-case execution time is computed as a function of the number of inputs (m) and the number of rules (c). The performance, applicability and limitations of the proposed algorithm are illustrated using a benchmark example. Optimized fuzzy model is coded and implemented using Intel 8XC196KC 16 bit fixed point microcontroller, and the results obtained are included.

Design and implementation of a fuzzy hardware structure for morphological color image processing

A hardware implementation of a fuzzy processor suitable for morphological color image processing applications is presented for the first time. From the hardware point of view, only a small number of algorithms for hardware implementation of soft gray-scale morphological filters have been reported in the literature, since research in mathematical morphology focuses mainly on possible extensions of the standard definitions (e.g., color and fuzzy mathematical morphology). The proposed digital hardware structure is based on a sequence of pipeline stages, and parallel processing is used in order to minimize computational times. It is capable of performing the basic morphological operations of standard and soft erosion/dilation for color images of 24-bit resolution. For the computation of morphological operations, a 3 /spl times/ 3-pixel image neighborhood and the corresponding structuring element are used. However, the system can be easily expanded to accommodate windows of larger sizes. The architecture of the processor is generic; the units that perform the fuzzy inference can be utilized for other fuzzy applications. It was designed, compiled, and simulated using the MAX+PLUS II Programmable Logic Development System by Altera Corporation. The fuzzy processor exhibits a level of inference performance of 601 KFLIPS with 54 rules, and can be used for real-time applications where the need for short processing times is of the utmost importance. The selection of a latest technology computer system (Pentium 4/3 GHz with SSE-2) can speed up image processing applications, but the time required still cannot be compared to the corresponding time using this hardware structure.

New membership functions for effective design and implementation of fuzzy systems

The paper proposes new membership functions (mfs) for fuzzy modeling. Existing mfs do not simultaneously satisfy ease in optimization and low-end hardware implementation. The proposed mfs satisfy the two contradicting requirements. The algorithm for hardware implementation is detailed. The performance and applicability of the proposed mfs are illustrated using two well-known benchmarks. Optimized fuzzy models are coded and implemented using the Intel 8XC196KC microcontroller. Results show that the proposed mfs simplify offline design and facilitate online implementation.

A low-power CAM design for LZ data compression

Low-power and high-performance data compressors play an increasingly important role in the portable mobile computing and wireless communication markets. Among lossless data compression algorithms for hardware implementation, LZ77 is one of the most widely used. For real-time communication, some hardware LZ compressors/decompressors have been proposed in the past. Content addressable memory (CAM) is widely considered as the most efficient architecture for pattern matching required by the LZ77 compression process. In this paper, we propose a low-power CAM-based LZ77 data compressor. By shutting down the power for unnecessary comparisons between the CAM words and the input symbol, the proposed CAM architecture consumes much lower power than the conventional ones without noticeable performance penalty. Moreover, using the proposed conditional comparison mechanism and the novel CAM cell with the NAND-type matching logic, on average we have close to two orders of improvement on power consumption, i.e., a reduction of more than 98 percent for 8-bit words. Speed is sacrificed if we use the NAND-type matching logic, but the NAND-type logic and the NOR-type logic can be combined to provide the best solution that balances power and delay. Our approach also can be applied to general-purpose CAMs which use the valid bits, so far as the proposed design techniques are adopted.

A real-time hardware implementation of the hough transform

The paper presents a hardware implementation of algorithms based on the Hough transform (HT) for real-time straight line detection. In particular, the basic HT on the edge points (EHT) and the Gradient-Weighted Hough transform (GWHT) for gray-level images are analyzed in detail and implemented on a pipelined architecture using Field Programmable Gate Arrays (FPGA). Algorithms execution times are compared with other hardware and software based systems in order to assess the efficiency of the presented approach. The paper shows how the achievable performance can meet the real-time requirements of an industrial inspection application.