Hardware Features Research Articles

Systematic review of memory assessment in virtual reality: evaluating convergent and divergent validity with traditional neuropsychological measures.

The evaluation of memory is a crucial aspect of both cognitive research and clinical applications, as it offers valuable insights into an individual's cognitive wellbeing and performance. Conventional neuropsychological assessments represent the established method for assessing different aspects of memory. Recent technological advancements, specifically in the field of virtual reality (VR), have introduced novel methods for evaluating memory. This systematic review aims to examine the current state of memory assessment using VR technologies, assessing the degree of convergence and divergence between VR-based memory assessments and conventional neuropsychological tests. A systematic review of the literature was conducted searching PubMed, PsycINFO, Web of Science databases, leading to the incorporation of 24 studies. Studies were grouped according to the examined memory domain (episodic, prospective, spatial domain). Convergence and divergence validity were examined for each, and information on software and hardware features was collected. This review demonstrates a notable alignment between VR-based memory assessments and conventional neuropsychological tests. Moreover, VR tasks have shown to exhibit associations with executive functions and overall cognitive performance. The inclusion of various ecological contexts, such as residential environments, commercial establishments, and simulated scenarios, serves to augment the ecological validity of memory evaluations conducted in VR. The findings indicate that VR assessments demonstrate a functional perspective by effectively capturing the dynamic relationship between memory, executive functions, and overall cognitive performance. Nevertheless, it is imperative to acknowledge and tackle certain constraints that may hinder the widespread adoption and utilization of VR tasks. These limitations encompass factors such as restricted accessibility to VR tasks and the presence of heterogeneity in VR hardware and software. The dynamic and ever-changing nature of VR technology presents a range of potential avenues for future investigation and utilization in the domain of memory evaluation.

Delay-guaranteed Mobile Augmented Reality Task Offloading in Edge-assisted Environment

With the introduction of Augmented Reality (AR) into mobile devices, it becomes a trend to develop mobile AR applications in various fields. However, the execution of AR task demands the extensive resources of computation, memory and storage, which makes it difficult for mobile terminals with constrained hardware resources to carry out AR applications within the limited delay. In response to this challenge, we propose a mobile AR offloading method under the edge-assisted environment. Firstly, we divide an AR task into consecutive subtasks, and then collect the features of hardware, software, configuration, and runtime environments from the edge servers to be offloaded. With the features, we construct an AR subtask Execution delay Prediction Bayesian Network (EPBN) to predict the execution delay of different subtasks on each edge platform. Based on the prediction, we model the task offloading as the NP-hard Traveling Salesman Problem (TSP), and then propose a PSO-GA based solution by adopting the heuristic algorithm of Particle Swarm Optimization (PSO) to encode the offloading strategy and using Genetic Algorithm (GA) for particle update. The extensive experiments prove that the average performances of EPBN outperform the others with 17.23%, 23.97%, and 20.67% on micro-P, micro-R, and micro-F1 respectively, and the PSO-GA ensures that the offloading latency is reduced by nearly 5% compared to the suboptimal algorithm.

Transcatheter Heart Valves—An Update on Types of Valves Available, Hardware Characteristics, and Patient Selection: An Indian Perspective

Transcatheter aortic valve implantation has taken the world by storm. The past decade saw expanding indications of Transcatheter aortic valve implantation to include patients at low surgical risk for surgical aortic valve replacement, patients with degenerated aortic bioprosthesis, and repurposing existing transcatheter aortic valves to treat pathology involving other valves. Also around the same time, various iterations of existing transcatheter heart valves and newly launched valves were made available for human use in India. This article highlights salient features of all the commercially available transcatheter heart valves in India. The article also provides a narrative to help a cardiologist choose a particular valve that would best suit the patient taking into account the valve design characteristics and features.

Comprehensive Swotting on Librem 5

The Librem5 is a privacy-focused smartphone that aims to provide users with a secure and open-source mobile computing experience. Developed by Purism, a company dedicated to creating products that prioritize user privacy and freedom, the Librem5 combines hardware and software features to protect user data and ensure transparency in mobile communications. This article provides an overview of Librem5's key characteristics, highlighting its emphasis on privacy, security, and open-source principles. The smartphone operates on a Linux-based operating system, which offers users complete control over their devices by allowing them to customize, modify, and inspect the underlying software. This approach ensures that users have full visibility into the code running on their devices, mitigating concerns regarding hidden vulnerabilities or unauthorized data collection.

Method of determination of integral and differential nonlinearities of ADC by three histograms during tests of diagnostic channels in complex magnetotherapy

One of the most important components of modern electronic systems in the fields of medical technology, automotive, 5G communications, etc. are microchips containing analog-to-digital converters (ADCs) on a single chip. Aging effects, environment and mechanical vibrations have a significant impact on the operation of electronic systems, so microcircuits need to be periodically verified, calibrated and even replaced. For this reason, in order to control metrological and technical characteristics of hardware and software of the "Multimag-M" complex, which contains diagnostic channels for measuring pulse wave, respiration process, blood pressure and blood oxygen saturation (saturation), it was proposed to introduce an automated block of control, testing and self-calibration into the structure of the chronomagnetotherapy complex [1]. Application of BIST (Build-in Self Test) - built-in means of self-testing is a promising approach to solving problems of reliability improvement of modern microcircuits [2]. Most of the known BIST methods of ADCs require on-chip highly linear test signal generator (TS) [3-4], which is the most complex block. The ability to test ADCs with a large number of digits is limited by the linearity of the TS generator and as the resolution of ADCs increases, it becomes a difficult task to provide linear TS generation on-chip. The aim of the work is to develop a method for determining the integral and differential nonlinearities of ADC independent of the linearity of the test signal. A method for determining the integral and differential nonlinearities of the ADC, taking into account the nonlinear component of the TS, is proposed. This is achieved by sequentially feeding to the input of the tested ADC a periodic TS of triangular shape, a level-shifted down TS and a level-shifted up TS. The first histogram of ADC codes distribution at absence of TS offset, and also the second and the third histograms at TS downward and upward shifting. Using the three linked histograms, the contribution of the nonlinear component of the TS to the integral nonlinearity for each ADC code is determined. Given the nonlinear component of the TS, the integral nonlinearity for each ADC code is further determined, and then the differential nonlinearity of the ADC is determined from the integral nonlinearity. In addition, the method determines the displacement voltages of the TS, which reduces the requirements for the accuracy of the displacement signal reference. The practical value of the research result lies in the application of the method reducing requirements to TS linearity at self-diagnostics and self-calibration of microcircuits containing ADCs will allow to reduce the complexity of crystal design.

A System for Mixed-Reality Holographic Overlays of Real-Time Rendered 3D-Reconstructed Imaging Using a Video Pass-through Head-Mounted Display-A Pathway to Future Navigation in Chest Wall Surgery.

Background: Three-dimensional reconstructions of state-of-the-art high-resolution imaging are progressively being used more for preprocedural assessment in thoracic surgery. It is a promising tool that aims to improve patient-specific treatment planning, for example, for minimally invasive or robotic-assisted lung resections. Increasingly available mixed-reality hardware based on video pass-through technology enables the projection of image data as a hologram onto the patient. We describe the novel method of real-time 3D surgical planning in a mixed-reality setting by presenting three representative cases utilizing volume rendering. Materials: A mixed-reality system was set up using a high-performance workstation running a video pass-through-based head-mounted display. Image data from computer tomography were imported and volume-rendered in real-time to be customized through live editing. The image-based hologram was projected onto the patient, highlighting the regions of interest. Results: Three oncological cases were selected to explore the potentials of the mixed-reality system. Two of them presented large tumor masses in the thoracic cavity, while a third case presented an unclear lesion of the chest wall. We aligned real-time rendered 3D holographic image data onto the patient allowing us to investigate the relationship between anatomical structures and their respective body position. Conclusions: The exploration of holographic overlay has proven to be promising in improving preprocedural surgical planning, particularly for complex oncological tasks in the thoracic surgical field. Further studies on outcome-related surgical planning and navigation should therefore be conducted. Ongoing technological progress of extended reality hardware and intelligent software features will most likely enhance applicability and the range of use in surgical fields within the near future.

The Effects of the Lubricant Properties and Surface Finish Characteristics on the Tribology of High-Speed Gears for EV Transmissions

Electric vehicle (EV) transmissions operate at high speeds. High-speed operation puts higher demands on bearings, seals, and gears. Bearings in EV transmissions are prone to electrically induced bearing damage and may exhibit signs of pitting and fluting. Surface-initiated rolling contact fatigue is another common problem gaining increased attention lately. Most EV transmissions require a coupling between an oil-lubricated gearbox to an electrical motor that runs with minimal lubrication at very high rpm. The high mechanical and thermal stresses the seals are exposed to under starved lubrication conditions have a detrimental impact on their service life. Hence, proper lubrication is critical. In general, EV transmission fluids call for a somewhat different spectrum of properties compared to conventional ATFs. Gear tribology simulations open new ways to the design and optimization of lubrication for EV transmissions. Additionally, such simulations can also provide valuable insights into the effects of different oil properties on cooling and lubrication efficiencies, thereby helping in matching the lubricant and hardware characteristics for optimal performance. In the present communication, we demonstrate the effects of different lubricants and surface finishing technologies on the tribology of high-speed gears using tribological tests and advanced thermal elastohydrodynamic (TEHD) simulations. The important roles of lubricity additives and surface finish optimization are highlighted in conjunction with a move towards ultralow viscosity EV transmission fluids.

Economic and Environmental Assessment of Technologies Optimizing the Execution of Long Trips for Electric Vehicles

Further advances in hardware and software features are needed to optimize battery and thermal management systems to allow for the execution of longer trips in electric vehicles. This paper assesses the economic and environmental impacts of the following features: eco-charging, eco-driving, smart fast charging, predictive thermal powertrain and cabin conditioning, and an advanced heat pump system. A Total Cost of Ownership (TCO) and externalities calculation is carried out on two passenger cars and one light commercial vehicle (LCV). The energy consumption data from the vehicles are based on experiments. The analysis shows more benefits for the LCV, while the smart fast-charging feature on the car shows a slight increase in TCO. However, negative results did not contribute significantly compared to the ability to install a smaller battery capacity for similar use.

Abstract 317: Using the Biomek NGeniuS Next Generation Library Prep System to automate the Illumina TruSight Oncology 500 assay

Abstract Cancer researchers using next generation sequencing (NGS) need reliable sample preparation methodologies that generate high-quality, sequence-ready libraries from often-challenging samples. This process can be aided using automated liquid handling systems. The Biomek NGeniuS Next Generation Library Prep System from Beckman Coulter Life Sciences is a reliable, easy-to-use, purpose-built liquid handler for NGS library preparation ideal for laboratories requiring more flexibility and less hands-on time. The user-friendly software requires no programming skills, making it easy to set up and run. Biomek NGeniuS Next Generation Library Prep System’s hardware features include an on-deck thermal cycler, gripper, temperature-controlled reagent storage, and high-density tip storage which reduces user interventions and enables more walkaway time. An extensive and growing library of complimentary demonstrated NGS sample prep protocols allows the user to select from a variety of applications for NGS workflows. One such workflow is Illumina TruSight Oncology 500 assay, which represents a comprehensive NGS assay targeting the full coding regions of 523 genes implicated in the pathogenesis of solid tumors. Using enrichment-based library preparation techniques for use with formalin-fixed, paraffin-embedded (FFPE) samples, the Illumina TruSight Oncology 500 assay, when running the DNA Only workflow, can detect single nucleotide variants (SNVs), indels, amplifications, and multinucleotide variants (MNVs) in a single sequencing run. The Illumina TruSight Oncology 500 assay also detects immunotherapy biomarkers for tumor mutational burden (TMB) and microsatellite instability (MSI) in DNA samples. The Illumina TruSight Oncology 500 assay also offers a combined RNA/DNA workflow that also allows for the assessment of fusion events. In this poster, we show the utility of the Biomek NGeniuS Next Generation Library Prep System to perform the Illumina TruSight Oncology 500 assay, which saves researchers valuable hands-on time and offers a highly streamlined setup process for users new to liquid handling automation. Confidential - Company Proprietary Citation Format: Zach Smith. Using the Biomek NGeniuS Next Generation Library Prep System to automate the Illumina TruSight Oncology 500 assay [abstract]. In: Proceedings of the American Association for Cancer Research Annual Meeting 2024; Part 1 (Regular Abstracts); 2024 Apr 5-10; San Diego, CA. Philadelphia (PA): AACR; Cancer Res 2024;84(6_Suppl):Abstract nr 317.

The Algorithms for Managing a Matrix-Based Warehouse Utilizing Standardized Transport and Storage Cells

The article explores the principles of organizing warehouse systems based on standardized transport and storage cells. It discusses the general hardware features of transport and storage cells that enable the movement of stored goods between them. The article presents a method for constructing a warehouse graph that takes into account possible directions for transferring containers with cargo between the transport and storage cells integrated into the warehouse structure, along with their common hardware characteristics. Key criteria used in determining the edge weights of the graph are described, including the basic cost of movement for each axis, cell wear and tear, cargo weight, fragility of the cargo, distance to the nearest available cells, and repairability. Algorithms are presented, the primary task of which is to determine the sequence of container movements between warehouse cells to facilitate loading and unloading operations. Simulation modeling of a warehouse with dimensions of 5×5×5 was conducted using the proposed algorithms, both with and without considering cell wear and tear parameters. The results of the simulation highlighted the significance of this criterion, allowing for extended warehouse servicing intervals and maximizing the time until the first failure.The study also investigates the possibility of optimizing the structure of such warehouse systems to meet various requirements. As part of this investigation, the structure was optimized for a warehouse with dimensions of 4×3×3.

Lightweight Arc Fault Detection Method Based on Adam-Optimized Neural Network and Hardware Feature Algorithm

Arc faults are the main cause of electrical fires according to national fire data statistics. Intensive studies of artificial intelligence-based arc fault detection methods have been carried out and achieved a high detection accuracy. However, the computational complexity of the artificial intelligence-based methods hinders their application for arc fault detection devices. This paper proposes a lightweight arc fault detection method based on the discrimination of a novel feature for lower current distortion conditions and the Adam-optimized BP neural network for higher distortion conditions. The novel feature is the pulse signal number per unit cycle, reflecting the zero-off phenomena of the arc current. Six features, containing the novel feature, are chosen as the inputs of the neural network, reducing the computational complexity. The model achieves a high detection accuracy of 99.27% under various load types recommended by the IEC 62606 standard. Finally, the proposed lightweight method is implemented on hardware based on the STM32 series microcontroller unit. The experimental results show that the average detection accuracy is 98.33%, while the average detection time is 45 ms and the average tripping time is 72–201 ms under six types of loads, which can fulfill the requirements of real-time detection for commercial arc fault detection devices.

A versatile, low-cost monitoring device suitable for non-intrusive load monitoring research purposes

Energy systems monitoring is a key factor in reducing global energy consumption. Although intrusive approaches can be adopted, Non-Intrusive Load Monitoring (NILM), which targets estimation of individual-appliance consumption from aggregated electricity measurements, is the main choice for retrofitting the plethora of non-smart electrical installations. Contemporary NILM requirements include high-frequency power-line sampling, efficient disaggregation algorithms that can, potentially, run locally, on the monitoring device, to offload the remote fog/cloud infrastructure, and various open datasets to allow the development of such algorithms. Towards all these directions, in this paper, a versatile monitoring device to support NILM research is presented. It offers high sampling frequency, sufficiency of local resources, and has been designed to be used in different environments (residential, commercial, industrial). Actually, it was deployed in all these environments, with multiple copies of it being used in two different industrial facilities for over two years. The developed device’s cost has been kept low, its accuracy has been experimentally verified to be sufficiently high, while its key hardware characteristics, in the context of NILM research, compare favorably with those of other devices in the literature. Along with the device, a residential, high-frequency dataset is also presented and made publicly available.

Analysis of EEG signals and data acquisition methods: a review

ABSTRACT Early illness diagnosis and prediction are important goals in healthcare in order to offer timely preventive measures. The best, least invasive, and most reliable way for identifying any neurological disorder is EEG analysis. If neurological disorders could somehow be predicted in advance, patients could be saved from their detrimental consequences. With promising new advancements in machine learning-based algorithms, Early and precise prediction might induce a radical shift. Here, we present a thorough analysis of cutting-edge AI methods for exploiting EEG data for Parkinson’s disease early warning symptoms detection, sleep apnoea, drowsiness, schizophrenia, motor imagery classification, and emotion recognition, among other conditions. All of the EEG signal analysis procedures used by different authors, such as hardware software data sets, channel, frequency, epoch, preprocessing, decomposition method, features, and classification, have been compared and analysed in detail. We will point out the difficulties, gaps and limitations in the current research and suggest future avenues of research.

Evaluation of Assembler and C Programming Languages on PIC16F877 Microcontroller

The programming of microcontrollers is essential for their correct operation, high computational efficiency, low-power solutions, and it is also key to get the most out of their capabilities with the hardware features that each of the microcontroller families has. There are different programming languages that can be used in microcontrollers, in this work we will focus on C and Assembler. C is one of the most widely used due to its efficiency and its ability to control the hardware directly. Assembly is a low-level language that allows more control over the instructions executed in the microcontroller, two songs have been implemented in assembler and C languages and the resources used for their execution on a Microchip PIC16F877 have been analyzed. The research results allow the developer to obtain results for a selection of the optimal hardware platform as well as the programming language according to the required memory utilization. Coding performed in MPLAB software with the asm and XC8 compilers, indicate that the C-code programs cover a larger amount of memory close to 4 times greater or higher.

Eight-channel signal synchronous acquisition system based on PCI and LabVIEW

In response to the multi-channel acquisition of the power grid simulator data collection system, this article builds a 8-channel signal synchronization acquisition system based on PCI-1706U and LabView, which introduces the characteristics of PCI-1706U hardware and LabView software DAQ system. A LabView DAQ program that uses the PCI-1706U to collect 8-way signal from the signal generator, complete the experiments of multi-channel synchronous acquisition and delayed start to collection, verify the feasibility and stability of the system, and analyzed the collected signals. Finally, the main work and innovation points of the thesis are summarized, and suggestions and outlook for future improvement are given. This study provides an effective implementation method based on PCI-1706U and LabView multi-channel signal synchronous acquisition system and delay acquisition function, with certain application value and promotion space.

Limitations in the electrochemical analysis of voltage transients.

Objective. Chronopotentiometric voltage transients (VTs) are used to assess the performance of bionic electrodes. The data obtained from VTs are used to define the safe operating conditions of clinical devices. Various approaches to analysing VTs have been reported, and a number of limitations in the accuracy of the measurements in relation to electrode size have been noted previously.Approach. The impact of electronic hardware and electrode configuration on VTs is discussed.Main results. The slew rate, rise time, sample time, minimum pulse length and waveform averaging characteristics of the electronic hardware, and electrode configuration will impact on VT measurement accuracy. Subsequently, activation and polarisation voltage measurements, and the definition of safe stimulation levels can be affected by the electronic hardware and electrode configuration.Significance. This article has identified some limitations in the previous literature related to the measurement and reporting of VTs and subsequent analysis of access and polarisation voltages. Furthermore, the commonly used Shannon plot used to define safe stimulation protocols does not correct for uncompensated resistance, account for electrode roughness or changes in electrode configuration. The creation of a safe stimulation plot which has been corrected for uncompensated resistance would generate more widely applicable stimulation guidelines for clinical devices used in different anatomical locations such as endovascular neural interfaces.

BigDEC: A multi-algorithm Big Data tool based on the [formula omitted]-mer spectrum method for scalable short-read error correction

Despite the significant improvements in both throughput and cost provided by modern Next-Generation Sequencing (NGS) platforms, sequencing errors in NGS datasets can still degrade the quality of downstream analysis. Although state-of-the-art correction tools can provide high accuracy to improve such analysis, they are limited to apply a single correction algorithm while also requiring long runtimes when processing large NGS datasets. Furthermore, current parallel correctors generally only provide efficient support for shared-memory systems lacking the ability to scale out across a cluster of multicore nodes, or they require the availability of specific hardware devices or features. In this paper we present a Big Data Error Correction (BigDEC) tool that overcomes all those limitations by: (1) implementing three different error correction algorithms based on the widely extended k-mer spectrum method; (2) providing scalable performance for large datasets by efficiently exploiting the capabilities of Big Data technologies on multicore clusters based on commodity hardware; (3) supporting two different Big Data processing frameworks (Spark and Flink) to provide greater flexibility to end users; (4) including an efficient, stream-based merge operation to ease downstream processing of the corrected datasets; and (5) significantly outperforming existing parallel tools, being up to 79% faster on a 16-node multicore cluster when using the same underlying correction algorithm. BigDEC is publicly available to download at https://github.com/UDC-GAC/BigDEC.

SwCUDA: Auto parallel code translation framework from CUDA to ATHREAD for new generation sunway supercomputer

Since specific hardware characteristics and low-level programming model are adapted to both NVIDIA GPU and new generation Sunway architecture, automatically translating mature CUDA kernels to Sunway ATHREAD kernels are realistic but challenging work. To address this issue, swCUDA, an auto parallel code translation framework is proposed. To that end, we create scale affine translation to transform CUDA thread hierarchy to Sunway index, directive based memory hierarchy and data redirection optimization to assign optimal memory usage and data stride strategy, directive based grouping-calculation-asynchronous-reduction (GCAR) algorithm to provide general solution for random access issue. swCUDA utilizes code generator ANTLR as compiler frontend to parse CUDA kernel and integrate novel algorithms in the node of abstracted syntax tree (AST) depending on directives. Automatically translation is performed on the entire Polybench suite and NBody simulation benchmark. We get an average 40x speedup compared with baseline on the Sunway architecture, average speedup of 15x compared to x86 CPU and average 27 percentage higher than NVIDIA GPU. Further, swCUDA is implemented to translate major kernels of the real world application Gromacs. The translated version achieves up to 17x speedup.

Cross-Feature Transfer Learning for Efficient Tensor Program Generation

Tuning tensor program generation involves navigating a vast search space to find optimal program transformations and measurements for a program on the target hardware. The complexity of this process is further amplified by the exponential combinations of transformations, especially in heterogeneous environments. This research addresses these challenges by introducing a novel approach that learns the joint neural network and hardware features space, facilitating knowledge transfer to new, unseen target hardware. A comprehensive analysis is conducted on the existing state-of-the-art dataset, TenSet, including a thorough examination of test split strategies and the proposal of methodologies for dataset pruning. Leveraging an attention-inspired technique, we tailor the tuning of tensor programs to embed both neural network and hardware-specific features. Notably, our approach substantially reduces the dataset size by up to 53% compared to the baseline without compromising Pairwise Comparison Accuracy (PCA). Furthermore, our proposed methodology demonstrates competitive or improved mean inference times with only 25–40% of the baseline tuning time across various networks and target hardware. The attention-based tuner can effectively utilize schedules learned from previous hardware program measurements to optimize tensor program tuning on previously unseen hardware, achieving a top-5 accuracy exceeding 90%. This research introduces a significant advancement in autotuning tensor program generation, addressing the complexities associated with heterogeneous environments and showcasing promising results regarding efficiency and accuracy.

An overview memristor based hardware accelerators for deep neural network

AbstractThe prevalence of artificial intelligence applications using artificial neural network architectures for functions such as natural language processing, text prediction, object detection, speech, and image recognition has significantly increased in today's world. The computational functions performed by artificial neural networks in classical applications require intensive and large‐scale data movement between memory and processing units. Various software and hardware efforts are being made to perform these operations more efficiently. Despite these efforts, latency in data traffic and the substantial amount of energy consumed in data processing emerge as bottleneck disadvantages of the Von Neumann architecture. To overcome this bottleneck problem, it is necessary to develop hardware units specific to artificial intelligence applications. For this purpose, neuro‐inspired computing chips are believed to provide an effective approach by designing and integrating a set of features inspired by neurobiological systems at the hardware level to address the problems arising in artificial intelligence applications. The most notable among these approaches is memristor‐based neuromorphic computing systems. Memristors are seen as promising devices for hardware‐level improvement in terms of speed and energy because they possess non‐volatile memory and exhibit analog behavior. They enable effective storage and processing of synaptic weights, offering solutions for hardware‐level development. Taking into account these advantages of memristors, this study examines the research conducted on artificial neural networks and hardware that can directly perform deep learning functions and mimic the biological brain, which is different from classical systems in today's context.