Hardware Expense Research Articles

DuDoCFNet: Dual-Domain Coarse-to-Fine Progressive Network for Simultaneous Denoising, Limited-View Reconstruction, and Attenuation Correction of Cardiac SPECT.

Single-Photon Emission Computed Tomography (SPECT) is widely applied for the diagnosis of coronary artery diseases. Low-dose (LD) SPECT aims to minimize radiation exposure but leads to increased image noise. Limited-view (LV) SPECT, such as the latest GE MyoSPECT ES system, enables accelerated scanning and reduces hardware expenses but degrades reconstruction accuracy. Additionally, Computed Tomography (CT) is commonly used to derive attenuation maps ( μ -maps) for attenuation correction (AC) of cardiac SPECT, but it will introduce additional radiation exposure and SPECT-CT misalignments. Although various methods have been developed to solely focus on LD denoising, LV reconstruction, or CT-free AC in SPECT, the solution for simultaneously addressing these tasks remains challenging and under-explored. Furthermore, it is essential to explore the potential of fusing cross-domain and cross-modality information across these interrelated tasks to further enhance the accuracy of each task. Thus, we propose a Dual-Domain Coarse-to-Fine Progressive Network (DuDoCFNet), a multi-task learning method for simultaneous LD denoising, LV reconstruction, and CT-free μ -map generation of cardiac SPECT. Paired dual-domain networks in DuDoCFNet are cascaded using a multi-layer fusion mechanism for cross-domain and cross-modality feature fusion. Two-stage progressive learning strategies are applied in both projection and image domains to achieve coarse-to-fine estimations of SPECT projections and CT-derived μ -maps. Our experiments demonstrate DuDoCFNet's superior accuracy in estimating projections, generating μ -maps, and AC reconstructions compared to existing single- or multi-task learning methods, under various iterations and LD levels. The source code of this work is available at https://github.com/XiongchaoChen/DuDoCFNet-MultiTask.

Stepwise Attention-Guided Multiscale Fusion Network for Lightweight and High-Accurate SAR Ship Detection

Many exceptional deep learning networks have demonstrated remarkable proficiency in general object detection tasks. However, the challenge of detecting ships in synthetic aperture radar (SAR) imagery increases due to the complex and various nature of these scenes. Moreover, sophisticated large-scale models necessitate substantial computational resources and hardware expenses. To address these issues, a new framework is proposed called a stepwise attention-guided multiscale feature fusion network (SAFN). Specifically, we introduce a stepwise attention mechanism designed to selectively emphasize relevant information and filter out irrelevant details of objects in a step-by-step manner. Firstly, a novel LGA-FasterNet is proposed, which incorporates a lightweight backbone FasterNet with lightweight global attention (LGA) to realize expressive feature extraction while reducing the model’s parameters. To effectively mitigate the impact of scale and complex background variations, a deformable attention bidirectional fusion network (DA-BFNet) is proposed, which introduces a novel deformable location attention (DLA) block and a novel deformable recognition attention (DRA) block, strategically integrating through bidirectional connections to achieve enhanced features fusion. Finally, we have substantiated the robustness of the new framework through extensive testing on the publicly accessible SAR datasets, HRSID and SSDD. The experimental outcomes demonstrate the competitive performance of our approach, showing a significant enhancement in ship detection accuracy compared to some state-of-the-art methods.

Monocular Depth Estimation Based on Dilated Convolutions and Feature Fusion

Depth estimation represents a prevalent research focus within the realm of computer vision. Existing depth estimation methodologies utilizing LiDAR (Light Detection and Ranging) technology typically obtain sparse depth data and are associated with elevated hardware expenses. Multi-view image-matching techniques necessitate prior knowledge of camera intrinsic parameters and frequently encounter challenges such as depth inconsistency, loss of details, and the blurring of edges. To tackle these challenges, the present study introduces a monocular depth estimation approach based on an end-to-end convolutional neural network. Specifically, a DNET backbone has been developed, incorporating dilated convolution and feature fusion mechanisms within the network architecture. By integrating semantic information from various receptive fields and levels, the model’s capacity for feature extraction is augmented, thereby enhancing its sensitivity to nuanced depth variations within the image. Furthermore, we introduce a loss function optimization algorithm specifically designed to address class imbalance, thereby enhancing the overall predictive accuracy of the model. Training and validation conducted on the NYU Depth-v2 (New York University Depth Dataset Version 2) and KITTI (Karlsruhe Institute of Technology and Toyota Technological Institute) datasets demonstrate that our approach outperforms other algorithms in terms of various evaluation metrics.

An adapted model predictive control MPPT for validation of optimum GMPP tracking under partial shading conditions

The energy generation efficiency of photovoltaic (PV) systems is compromised by partial shading conditions (PSCs) of solar irradiance with many maximum power points (MPPs) while tracking output power. Addressing this challenge in the PV system, this article proposes an adapted hybrid control algorithm that tracks the global maximum power point (GMPP) by preventing it from settling at different local maximum power points (LMPPs). The proposed scheme involves the deployment of a 3 × 3 multi-string PV array with a single modified boost converter model and an adapted perturb and observe-based model predictive control (APO-MPC) algorithm. In contrast to traditional strategies, this technique effectively extracts and stabilizes the output power by predicting upcoming future states through the computation of reference current. The boost converter regulates voltage and current levels of the whole PV array, while the proposed algorithm dynamically adjusts the converter's operation to track the GMPP by minimizing the cost function of MPC. Additionally, it reduces hardware costs by eliminating the need for an output current sensor, all while ensuring effective tracking across a variety of climatic profiles. The research illustrates the efficient validation of the proposed method with accurate and stable convergence towards the GMPP with minimal sensors, consequently reducing overall hardware expenses. Simulation and hardware-based outcomes reveal that this approach outperforms classical techniques in terms of both cost-effectiveness and power extraction efficiency, even under PSCs of constant, rapidly changing, and linearly changing irradiances.

SYNTHESIS OF VHDL-MODEL OF A FINITE STATE MACHINE WITH DATAPATH OF TRANSITIONS

Context. The problem of building a program model of a finite state machine with datapath of transitions using VHDL language is considered. The model synthesis process is identified with the synthesis of this type of finite state machine, since the built model can be used both for the analysis of the device’s behavior and for the synthesis of its logic circuit in the FPGA basis. The object of the research is the automated synthesis of the logic circuit of the finite state machine with the datapath of transitions, based on the results of which numerical characteristics of the hardware expenses for the implementation of the state machine circuit can be obtained. This makes it possible to evaluate the effectiveness of using this structure of the finite state machine when implementing a given control algorithm.
 Objective. Development and research of a VHDL model of a finite state machine with datapath of transitions for the analysis of the behavior of the state machine and the quantitative assessment of hardware expenses in its logic circuit.
 Method. The research is based on the structural diagram of a finite state machine with datapath of transitions. The synthesis of individual blocks of the structure of the state machine is carried out according to a certain procedure by the given graph-scheme of the con-trol algorithm. It is proposed to present the result of the synthesis in the form of a VHDL description based on the fixed values of the states codes of the state machine. The process of synthesizing the datapath of transitions, the block of formation of codes of transitions operations and the block of formation of microoperations is demonstrated. VHDL description of that blocks is carried out in a synthesizable style, which allows synthesis of the logic circuit of the finite state machine based on FPGA with the help of modern CAD and obtaining numerical characteristics of the circuit, in particular, the value of hardware expenses. To analyze the correctness of the synthesized circuit, the process of developing the behavioral component of the VHDL model, the function of which is the generation of input signals of the finite state machine, is considered. The classical combination of the synthesizable and behavioral parts of the model allows presenting the results of the synthesis of a finite state machine with datapath of transitions as a separate project that can be used as a structural component of the designed digital system.
 Results. Using the example of an abstract graph-scheme of the control algorithm, a VHDL model of a finite state machine with datapath of transitions was developed. With the help of CAD AMD Vivado, a synthesis of the developed model was carried out and behavioral modeling of the operation of the finite state machine circuit was carried out. The results of the circuit synthesis made it possible to obtain the value of hardware expenses when implementing the circuit in the FPGA basis. According to the results of behavioral modeling, time diagrams were obtained, which testify to the correctness of the implementation of the functions of transitions and outputs of the synthesized state machine.
 Conclusions. In traditional VHDL models of finite state machines, the states do not contain specific codes and are identified using literals. This allows CAD to encode states at its own discretion. However, this approach is not suitable for describing a finite state machine with datapath of transitions. The transformation of states codes using a set of arithmetic and logic operations requires the use of fixed values of states codes, which determines the specifics of the VHDL model proposed in this paper. This and similar models can be used, in particular, in the study of the effectiveness of a finite state machine according to the criterion of hardware expenses in the device circuit.

TEST GRAPH-SCHEMES OF THE ALGORITHMS OF FINITE STATE MACHINES WORK FOR ASSESSING THE EFFICIENCY OF AUTOMATED SYNTHESIS IN XILINX VIVADO CAD

Context. The problem of evaluating the effectiveness of the automated design of a microprogram finite state machine with the operational transformation of state codes using Xilinx Vivado CAD is considered. The object of the research was graph-schemes of control algorithms implemented by finite state machine and able to prove the effectiveness of the principle of operational transformation of state codes in comparison with standard synthesis methods built into the CAD, in the context of hardware expenses optimization.
 Objective. Development and research of graph-schemes of control algorithms in order to substantiate the effectiveness of the application of structure of the finite state machine with datapath of transitions in comparison with the built-in methods of synthesizing finite state machines in Xilinx Vivado CAD in the basis of programmable logic devices.
 Method. The research is based on the hypothetical assumption that the Xilinx Vivado CAD has built-in methods of automated design of the circuit of a finite state machine, the effectiveness of which, according to the criterion of hardware expenses, exceeds other known methods of optimizing hardware expenses in the finite state machine circuit. In order to refute this hypothesis, it is proposed to prove that in some cases known methods of hardware expenses optimization in the finite state machine circuit are more effective in comparison with the methods built into CAD. In this work, as a well-known optimization method, the method of operational transformation of state codes, which corresponds to the structure of a finite state machine with datapath of transitions, is chosen. The effectiveness of this method is demonstrated on the example of several test graph-schemes of algorithms, the structure of which is abstract and artificially adapted to the chosen optimization method. The adaptation of the selected graph-schemes of the algorithms consists in the fact that a relatively small number of transition operations is required for their implementation with the help of a finite state machine with datapath of transitions. This contributes to the simplification of the circuit of the finite state machine and the reduction of hardware costs for its implementation. At the same time, the test graph-schemes of the algorithms have the possibility of scaling, which allows to automate the construction of VHDL models of the corresponding finite state machines for graph-schemes of different sizes and to evaluate the optimization of hardware expenses for finite state machines of different complexity.
 Results. Using the example of several graph-schemes of algorithms, it is demonstrated that in some cases none of the finite state machine synthesis methods built into the Xilinx Vivado CAD is able to surpass the method of operational transformation of state codes according to the criterion of hardware expenses for the implementation of a finite state machine circuit. At the same time, a several-fold gain in hardware expenses can be achieved, which indicates the expediency of using this method under certain conditions. The formal definition of such conditions for the considered and other known optimization methods is a separate unsolved scientific problem.
 Conclusions. The conducted experiments confirmed that in some cases, the known methods of synthesis of finite state machines allow to obtain circuits with lower hardware expenses than when using the methods of synthesis of finite state machines contained in Xilinx Vivado CAD. This testifies to the general expediency of using existing and developing new methods of hardware expenses optimization in the circuit of the finite state machines and the current relevance of the theory of the synthesis of digital automata as a scientific direction.

Design of A High-Precision Component-Type Vertical Pendulum Tiltmeter Based on FPGA.

This paper presents a high-precision component-type vertical pendulum tiltmeter based on an FPGA (Field Programmable Gate Array) that improves the utility and reliability of geophysical field tilt observation instruments. The system is designed for rapid deployment and offers flexible and efficient adaptability. It comprises a pendulum body, a triangular platform, a locking motor and sealing cover, a ratiometric measurement bridge, a high-speed ADC, and an FPGA embedded system. The pendulum body is a plumb-bob-type single-suspension wire vertical pendulum capable of measuring ground tilt in two orthogonal directions simultaneously. It is installed on a triangular platform, sealed as a whole, and equipped with a locking motor to withstand a free-fall impact of 2 m. The system utilizes a differential capacitance ratio bridge in the measurement circuit, replacing analog circuits with high-speed AD sampling and FPGA digital signal processing technology. This approach reduces hardware expenses and interferences from active devices. The system also features online compilation functionality for flexible measurement parameter settings, high reliability, ease of use, and rapid deployment without the need for professional technical personnel. The proposed tiltmeter holds significant importance for further research in geophysics.

Deep Learning Model to Denoise Luminescence Images of Silicon Solar Cells.

Luminescence imaging is widely used to identify spatial defects and extract key electrical parameters of photovoltaic devices. To reliably identify defects, high-quality images are desirable; however, acquiring such images implies a higher cost or lower throughput as they require better imaging systems or longer exposure times. This study proposes a deep learning-based method to effectively diminish the noise in luminescence images, thereby enhancing their quality for inspection and analysis. The proposed method eliminates the requirement for extra hardware expenses or longer exposure times, making it a cost-effective solution for image enhancement. This approach significantly improves image quality by >30% and >39% in terms of the peak signal-to-noise ratio and the structural similarity index, respectively, outperforming state-of-the-art classical denoising algorithms.

Joint beamforming and phase-shifting design for energy efficiency in RIS-assisted MISO communication with statistical CSI

The emergence of more and more computation-intensive applications has imposed higher requirements in spectrum and energy efficiency (EE) for internet of things (IoT) wireless networks. Massive multiple-input multiple-output (MIMO) is utilized to gain spectral efficiency as an important part of wireless systems. However, the power expansion from hardware lowers the massive MIMO performance remarkably. Reconfigurable intelligent surface (RIS) technology can solve this problem well since it can not only provide higher array gain but also reduce energy depletion and hardware expense. In this article, we study joint optimization about beam-forming, RIS phase shift, and energy harvesting of IoT devices for maximizing EE of the multiple-input single-input downlink system with multiple IoT devices and an energy harvesting device. Different from existing works focusing on ergodic capacity with known statistic channel information of BS-RIS-device, we suppose that statistics information of RIS-device is known. Mathematically, the joint optimization problem is cast into a challenging non-convex one. To this end, based on successive convex approximation, we convert the original problem into two parts and then provide two heuristic schemes to tackle them, respectively. Next, an iterative scheme integrated by two heuristic algorithms is proposed to earn feasible solution in polynomial time. Finally, the proposed scheme is verified to be effective by simulations.

An Effective Kalman Based Hybrid Beamforming for Millimeter Wave Massive MIMO System by Using 2D Overlapped Partially Connected Sub-Array Structure

In 5G mobile communication networks, millimeter-wave (mmWave) technology plays a key role. To deal with the problem of path loss that happens in the mmWave band, competent beamforming employing a large antenna array is required. Fully digital beamforming approaches currently require separate radio frequency chains (RF chains) for each antenna, which adds to the computational complexity and hardware expense. In a multi-user environment, fully digital beamforming suffers from a larger antenna array layout, whereas analog beamforming solutions are prone to numerous performance concerns. Hybrid beamforming, on the other hand, offers a promising solution for multi-user mmWave communication. This work proposes a two-dimensional overlapping partially connected (2D-OPC) sub-array structure to reduce the antenna structure's hardware complexity and cost. The suggested technique comprises several sub-arrays that are overlapped in 2D space in the form of a Uniform Planar Array (UPA). The suggested scheme's performance is assessed using Kalman-based hybrid beamforming, which exhibits a considerable increase in spectral efficiency when compared to existing hybrid beamforming techniques. The suggested technique, which uses Kalman based hybrid beamforming and 2D-OPC provides 3.14% and 4.96% improvement over the MMSE hybrid beamforming and ZF pre-coding technique respectively.

Hybrid PLC and LoRaWAN Smart Metering Networks: Modeling and Optimization

The evolution toward the so-called smart grid (SG) needs to be supported by robust and cost-efficient advanced metering infrastructure. This article focuses on technology selection and gateway placement in hybrid SGs, wherein each smart meter (SM) is equipped with either a power line communication or a long-range wide area network protocol node to connect to its serving gateway. The latter is endowed with both technologies. In particular, we introduce an analytical framework to characterize the performance–cost tradeoffs using a multicriteria optimization approach. For each technology, a set of performance objective functions (i.e., sum-rate and max–min) has been derived based on the ergodic capacity, whereas the cost is represented by SG hardware expenses. Then, the nondominated sorting genetic algorithm-II has been exploited using an appropriate chromosome structure to provide the suitable access technology for each SM along with the optimal number and the placement of the serving GWs. Extensive numerical simulations have shown that hybrid solutions provide a good interplay between performance and investment costs, spurring the need to redefine the conventional SG designs traditionally operating in single communication technologies.

An Improved Modulation Method for Suppressing High Frequency Common-Mode Voltage in SiC Motor Drive System

High-frequency common-mode voltage generated by inverters causes severe negative effects, particularly in silicon carbide (SiC) Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs)-driven motors. Additionally, common suppression strategies would increase hardware expenses or sacrifice the switching speed of SiC devices. This article proposes an improved no-zero vector modulation strategy to suppress high-frequency common-mode voltage without increasing the cost of hardware. In this method, only nonzero vectors are utilized to reduce common-mode voltage. Firstly, the influence of different switching states on the characteristics of SiC MOSFETs has been studied by double-pulse tests, which explains why zero vectors will cause more serious voltage oscillations. Secondly, common-mode voltage suppression failure caused by the high-frequency dead zone effect has been analyzed in detail. Based on traditional Active Zero State Pulse Width Modulation (AZSPWM), complementary device conduction logic and dead-zone compensation methods are proposed. In switching moments, different turn-on logic is selected to ensure that only one switch acts, and different dead zone compensation methods are selected to deal with the common-mode suppression failure, which effectively avoids high-frequency common-mode voltage spikes. Finally, simulation and experimental results verify that the improved modulation algorithm can effectively suppress high-frequency common-mode voltage.

FastCFI: Real-time Control-Flow Integrity Using FPGA without Code Instrumentation

Control-Flow Integrity (CFI) is an effective defense technique against a variety of memory-based cyber attacks. CFI is usually enforced through software methods, which entail considerable performance overhead. Hardware-based CFI techniques can largely avoid performance overhead, but typically rely on code instrumentation, forming a non-trivial hurdle to the application of CFI. Taking advantage of the tradeoff between computing efficiency and flexibility of FPGA, we develop FastCFI, an FPGA-based CFI system that can perform fine-grained and stateful checking without code instrumentation. We also propose an automated Verilog generation technique that facilitates fast deployment of FastCFI, and a compression algorithm for reducing the hardware expense. Experiments on popular benchmarks confirm that FastCFI can detect fine-grained CFI violations over unmodified binaries. When using FastCFI on prevalent benchmarks, we demonstrate its capability to detect fine-grained CFI violations in unmodified binaries, while incurring an average of 0.36% overhead and a maximum of 2.93% overhead.

The Rational Selection of the Modules of the Values for the Processors in the System of the Residual Classes

Considered there is a set of systems of modules for 32-bit and 64-bit processors in the residual number system (RNS). The conducted substantiation of the selection criteria of values of the modules with a minimum of hardware expenses tabular implementation of RNS processor; minimum hardware expenses in the implementation of RNS processor in the binary logic which is the same type of module channels. Considered there are various systems of modules in the amount of 25 sets for 32- bit and 22 sets for 64-bit processors. The conducted investigations determine the effectiveness of the use of all sets under the consideration systems of modules in terms of each of criteria. The present analysis of the results selected the best criteria according to the systems of modules for each of the processors.

Implementation of Fpga-based Pseudo-random Words Generator

A hardware implementation of pseudo-random bit generator based on FPGA chips, which use the principle of reconfigurability that allows the modernization of their algorithms and on-line replacement of the internal structure (reconfiguration) in the process of functioning have been considered in the paper. Available DSP blocks embedded into the structure of FPGA chips allow efficient hardware implementation of the pseudorandom bit generator through the implementation of the basic operations of multiplication with accumulation on the gate level. Using CAD ISE 14.02 Foundation and VHDL language three types of pseudo-random bit generators have been implemented on Spartan series chip 6SLX4CSG225-3, for which time and hardware expenses are represented. Using the simulating system ModelSim SE 10.1c, timing diagrams of simulation for these structures have been obtained.

High Performance SiGe HBT Performance Variability Learning by Utilizing Neural Networks and Technology Computer Aided Design

Process sensitivity and variation, such as layer thicknesses, etch dimensions and doping levels are all process parameters that should be well understood when assessing their impact on end of process wafer quality and device performance. Improvements in uniformity of electrical device performance is often not taken into major consideration until a certain maturity level of a technology is reached. In this work, use of technology computer aided design (TCAD) and process compact models (PCM) developed from neural networks demonstrate their utility in process- parameter variation understanding in earlier stages of technology development. A TCAD simulation was built and calibrated to match key electrical performance metrics of an experimental high performance SiGe HBT in 130nm BiCMOS technology, which was the device of focus in this study. Figure 1 includes a TCAD cross section of the device1. Neural net techniques, a machine-learning methodology, the development and deployment of which has grown significantly over the last three decades, is used to expand the scope of TCAD to process variability2-3.The aforementioned calibrated TCAD deck was used to generate training data for the neural network process compact model in place of hardware data. Key process features, as listed in table 1 were a few of the process conditions that were varied from nominal values to characterize the variation in resulting electrical performance. Figure 2 includes a 1D schematic view of the epitaxial layers of the HBT, highlighting some of the process features varied in simulation. The neural network was trained using a data analysis suite using three hidden layers with 16 neurons each to get a best fit to the training data input and output values.The foundation of this approach was a TCAD simulation calibrated to match performance of the nominal HBT device of focus. Key AC and Gummel performance parameters had good agreement with hardware data as illustrated in Figure 3a and b. Thousands of individual TCAD simulations with combinations of varied process feature values were then executed to generate neural network training data in lieu of hardware data- utilizing reported standard deviations of each process parameter. The trends and sensitivity of this data was then reflected in the process compact model, which would provide results for large-scale calculation and analysis. Beta was the electrical parameter of focus in this study, where its changes in process variation (mean and standard deviation) were predicted by the trained PCM. The agreement with hardware electrical parameter Beta with respect to Boron dose in Figure 4 demonstrates how use of calibrated TCAD as a basis can empower prediction of large-scale hardware results without the extent of hardware expense. Use of this tool can be extended to simulate and analyze larger populations than what would be feasible for hardware (in several thousands) to predict the effect of process input changes on uniformity of electrical parameters. Figure 5 demonstrates how the changes in standard deviation of Beta can be predicted as a function of Boron dose variation-through generation of large simulated populations by the PCM.The resulting work on a state-of-the-art SiGe BiCMOS technology demonstrates how specific simulation tools, like TCAD-trained process compact models can be leveraged for enhanced process understanding and improvement. The data generated from these tools can supplement or replace hardware and corresponding data, saving in development costs and associated hours in manpower. They can also enable earlier and more agile decision-making about key production metrics throughout the technology development process. Calibrated TCAD infrastructure, coupled with neural-net technology have potential to fulfill pivotal roles through the timelines of technology development, rather than just being utilized when a technology is mature.

Clock-Centric Serial Links for the Synchronization of Distributed Readout Systems

Detector readout systems for medium to large scale physics experiments, and instruments in some other fields as well, are generally composed of multiple front-end digitizer boards distributed over a certain area. Often, this hardware has to be synchronized to a common reference clock with minimal skew and low jitter. Today's mainstream solutions to precise clock distribution and deterministic latency messaging rely on the capabilities of high speed serial transceivers (a.k.a. SerDes) embedded in modern Field Programmable Gate Arrays (FPGAs). An alternative option uses distinct clock and data links. This can potentially reach higher synchronization accuracy, at significant hardware expenses. This work reports some first steps to explore a third scheme for clock and synchronous message distribution. Like the standard approach, the same media is used to convey clock and data, but instead of using today's "data-centric" links where the recovered clock is only a by-product of a SerDes, this paper defines and investigates "clock-centric" links where, at the opposite, a clock is carried by the link, and synchronous data are embedded into it by a modulation technique. After defining the concepts and principles of data-centric links, experimental studies are presented. Finally, the merits and limitations of the proposed approach are discussed.

A Probabilistic Prediction-Based Fixed-Width Booth Multiplier for Approximate Computing

In order to gain substantial circuit performance improvement in terms of power, speed and area cost, approximate computing is ideally applied in many error-resilient DSP and multimedia applications by relaxing the requirements of exact computation. Fixed-width multipliers are intensively used in those applications, which makes them a good demonstration for approximation through dynamic range reduction. In this paper, a probabilistic prediction based fixed-width Booth multiplier has been proposed. The error compensation function is derived from the probabilistic analysis on the partial products obtained from Booth encoding. By slightly modifying the partial product array with dedicated partitioning, a simple compensation circuit is thus formulated. Compared with the previous works, the proposed design exhibits the best performance-accuracy tradeoff. It achieves at least 27% reduction on the area-energy-delay-error product compared with the other multipliers among various operand lengths. Additionally, the evaluation on 2-Dimensional discrete cosine transform (DCT) circuits indicates that our proposed fixed-width Booth multiplier is applicable for lossy applications with a considerable reduction on hardware expenses and power dissipation while maintaining decent output quality.

The FAST Pump, a low-cost, easy to fabricate, SLA-3D-printed peristaltic pump for multi-channel systems in any lab.

With the increasing interest in high throughput screening and parallel assays, laboratories around the world inevitably find themselves in need of driving a multitude of fluid lines to facilitate their large scale studies. The comparatively low cost and no-fluid-contact design of peristaltic pumps make them the go-to systems for such ventures, but using commercially available pumping systems this still becomes a costly endeavor at typically $250-$1000 per pump line. Here we have developed an alternative, a peristaltic pump that can be fabricated in most research laboratories using 3D-printing and readily available off-the-shelf parts. The pump features 8 parallel channels with linear ranges spanning from 0.7µL/min to 6mL/min. The pump can be fabricated and assembled by anyone with access to a 3D-printer at a cost of less than $45 per channel and is driven by a stepper motor that connects directly to any computer. This device has the potential to be disruptive in areas such as drug screening and assay development, as well as lab-on-a-chip applications and cell cultivation, where it significantly reduces hardware expenses and allows for construction of more comprehensive fluidic systems at a fraction of current costs.

Improved Model Predictive Control for High-Power Current-Source Rectifiers Under Normal and Distorted Grid Conditions

This article proposes an improved model predictive control (MPC) method for high-power current-source rectifiers (CSR). Instead of introducing the virtual impedance based active damping notion into MPC framework, the predefined cost function directly takes grid-side current and capacitor voltage as the regulating objectives to suppress the $LC$ resonance and grid current distortions. The relationship and differences between the proposed cost function and its form with active damping function are analyzed in detail under normal grid conditions. Moreover, the number of discrete candidate vectors during each predictive horizon in the proposed scheme is reduced from nine to five by considering the constraint of switching states transition. Therefore the computational burden is relieved compared with conventional MPC under normal grid conditions. Finally, in order to keep sinusoidal grid current for CSR even working under severe distorted supply voltage, specific harmonic orders of grid current suppression items are added into the proposed cost function subsequently. The performance of proposed methods at low switching frequency ( $\leq$ 1 kHz) under normal and distorted grid conditions are tested through both simulation and experiments. For the implementation of all MPC methods, capacitor voltage is estimated by an observer to save hardware expense instead of using transducers.