Efficient Hardware Research Articles

Investigating the Performance of Gammatone Filters and Their Applicability to Design Cochlear Implant Processing System

Commercially available cochlear implants are designed to aid profoundly deaf people in understanding speech and environmental sounds. A typical cochlear implant uses a bank of bandpass filters to decompose an audio signal into a set of dynamic signals. These filters’ critical center frequencies f0 imitate the human cochlea’s vibration patterns caused by audio signals. Gammatone filters (GTFs), with two unique characteristics: (a) an appropriate “pseudo resonant” frequency transfer function, mimicking the human cochlea, and (b) realizing efficient hardware implementation, could demonstrate them as unique candidates for cochlear implant design. Although GTFs have recently attracted considerable attention from researchers, a comprehensive exposition of GTFs is still absent in the literature. This paper starts by enumerating the impulse response of GTFs. Then, the magnitude spectrum, |H(f)|, and bandwidth, more specifically, the equivalent rectangular bandwidth (ERB) of GTFs, are derived. The simulation results suggested that optimally chosen filter parameters, e.g., critical center frequencies,f0; temporal decay parameter, b; and order of the filter, n, can minimize the interference of the filter bank frequencies and very likely model the filter bandwidth (ERB), independent of f0b. Finally, these optimized filters are applied to delineate a filter bank for a cochlear implant design based on the Clarion processor model.

Efficient number theoretic transform accelerator for CRYSTALS-Kyber

<p>The national institute of standards and technology (NIST) has presented its draft of the module-lattice-based key-encapsulation mechanism standard (MLBKEMS), choosing cryptographic suite for algebraic lattices (CRYSTALS)- Kyber as the base encryption. Existing hardware implementations of modern cryptography will need to process the new standard efficiently. The primary process in CRYSTALS-Kyber key-encapsulation mechanism (KEM) is the number theoretic transform (NTT), which requires heavy computing power. This paper contributes an efficient hardware accelerator for NTT and inverse NTT (INTT) by CRYSTAL-Kyber parameters. The proposed design utilizes the K-RED algorithm for reducing polynomial multiplication. It also incorporates the BrentKung method for efficient modular addition and subtraction operation with an address generator to control the sequences of computation. On the Xilinx Artix 7 field programmable gate array (FPGA), our design achieves 262 MHz clock speed, utilizing only 1405 LUTs.</p>

Reinforcement Learning-Driven Bit-Width Optimization for the High-Level Synthesis of Transformer Designs on Field-Programmable Gate Arrays

With the rapid development of deep-learning models, especially the widespread adoption of transformer architectures, the demand for efficient hardware accelerators with field-programmable gate arrays (FPGAs) has increased owing to their flexibility and performance advantages. Although high-level synthesis can shorten the hardware design cycle, determining the optimal bit-width for various transformer designs remains challenging. Therefore, this paper proposes a novel technique based on a predesigned transformer hardware architecture tailored for various types of FPGAs. The proposed method leverages a reinforcement learning-driven mechanism to automatically adapt and optimize bit-width settings based on user-provided transformer variants during inference on an FPGA, significantly alleviating the challenges related to bit-width optimization. The effect of bit-width settings on resource utilization and performance across different FPGA types was analyzed. The efficacy of the proposed method was demonstrated by optimizing the bit-width settings for users’ transformer-based model inferences on an FPGA. The use of the predesigned hardware architecture significantly enhanced the performance. Overall, the proposed method enables effective and optimized implementations of user-provided transformer-based models on an FPGA, paving the way for edge FPGA-based deep-learning accelerators while reducing the time and effort typically required in fine-tuning bit-width settings.

An efficient versatile video coding motion estimation hardware

Versatile Video Coding (VVC) is the latest video coding standard. It provides higher compression efficiency than the previous video coding standards at the cost of significant increase in computational complexity. Motion estimation (ME) is the most time consuming and memory intensive module in VVC encoder. Therefore, in this paper, we propose an efficient VVC ME hardware. It is the first VVC ME hardware in the literature. It has real time performance with small hardware area. This efficiency is achieved by using a 64 × 64 systolic processing element array to support maximum coding tree unit (CTU) size of 128 × 128 and by using a novel memory-based sum of absolute differences (SAD) adder tree to calculate SADs of 128 × 128 CTUs. The proposed VVC ME hardware reduces memory accesses significantly by using an efficient data reuse method. It can process up to 30 4 K (3840 × 2160) video frames per second.

Coupled Ferroelectric-Photonic Memory in a Retinomorphic Hardware for In-Sensor Computing.

The development of all-in-one devices for artificial visual systems offers an attractive solution in terms of energy efficiency and real-time processing speed. In recent years, the proliferation of smart sensors in the growth of Internet-of-Things (IoT) has led to the increasing importance of in-sensor computing technology, which places computational power at the edge of the data-flow architecture. In this study, a prototype visual sensor inspired by the human retina is proposed, which integrates ferroelectricity and photosensitivity in two-dimensional (2D) α-In2Se3 material. This device mimics the functions of photoreceptors and amacrine cells in the retina, performing optical reception and memory computation functions through the use of electrical switching polarization in the channel. The gate-tunable linearity of excitatory and inhibitory functions in photon-induced short-term plasticity enables to encode and classify 12000 images in the Mixed National Institute of Standards and Technology (MNIST) dataset with remarkable accuracy, achieving ≈94%. Additionally, in-sensor convolution image processing through a network of phototransistors, with five convolutional kernels electrically pre-programmed into the transistors is demonstrated. The convoluted photocurrent matrices undergo straightforward arithmetic calculations to produce edge and feature-enhanced scenarios. The findings demonstrate the potential of ferroelectric α-In2Se3 for highly compact and efficient retinomorphic hardware implementation, regardless of ambipolar transport in the channel.

Divide-and-conquer-based RDO-free CU Partitioning for 8K Video Compression

8K (7689×4320) ultra-high definition (UHD) videos are growing popular with the improvement of human visual experience demand. Therefore, the compression of 8K UHD videos has become a top priority in the third-generation audio video coding standard (AVS3). However, as an important part of the coding standard promotion, the real-time hardware implementation for AVS3-based 8K UHD video intra coding is severely hindered, especially in the coding unit (CU) partition stage. To break through the limitation, this article proposes a divide-and-conquer-based rate-distortion-optimization-free (RDO-free) CU partitioning algorithm for efficient hardware implementation. Aimed at the complex CU partition in AVS3, we separately design a lightweight optimization for original partitioning rules to improve division efficiency and a decision tree-based RDO-free CU decision framework to eliminate the latency caused by the waiting for rate-distortion cost calculation in RDO strategy. Afterward, a divide-and-conquer-based hardware-friendly gradient difference calculating approach is devised to accelerate the learning feature extracting speed. To ensure that the proposed algorithm is sufficient to support the real-time CU partition for 8K videos, we also develop a hardware architecture based on FPGA. Experimental results illustrate that the software coding performance of our algorithm is significantly ahead of the efficient implementation uAVS3e for AVS3 and the reference software HM-16.20 for High Efficiency Video Coding (HEVC), even though there is 9.96% loss on BD-Rate Y. Considering its importance for the hardware implementation of AVS3-based 8K real-time encoder, the coding loss is acceptable. Moreover, the hardware simulation results on VU440 FPGA with Vivado 2019 show that our algorithm can support 61.12 frames per second (fps) CU partition for 8K UHD videos with only 0.00%, 0.00%, 1.01%, and 7.78% consumption of BRAM_18K, DSP48E, FF, and LUT, respectively. Additionally, with dual-path parallelism, 122.24 fps also can be implemented with controllable resource utilization, which achieves the state-of-the-art performance.

Eco-Energy Sensor Networks

This project perpetual environmentally powered sensor networks aims to develop a system for harvesting energy from the renewable environmental energy source using the embedded systems technology. Utilizing environmental energy sources holds great appeal as a power supply for low- power wireless sensor networks.This has become a major problem now a days as the proposed system involves human intervention. This project is aiming to pinpoint the best hardware selections that align with the requirements of a particular application. The primary goal is to optimize the hardware to precisely cater to the needs and demands of the given application. The primary design obstacle involves minimizing stress on storage components while maintaining a straightforward hardware and software structure. This design is a smart system that integrates streamlined, efficient hardware with robust software. This system will actively oversee the power subsystem to ensure continuous operation

High-Throughput MPSoC Implementation of Sparse Bayesian Learning Algorithm

In the field of sparse signal reconstruction, sparse Bayesian learning (SBL) has excellent performance, which is accompanied by extremely high computational complexity. This paper presents an efficient SBL hardware and software (HW&SW) co-implementation method using the ZYNQ series MPSoC (multiprocessor system-on-chip). Firstly, considering the inherent challenges in parallelizing iterative algorithms like SBL, we propose an architecture based on the iterative calculations implemented on the PL side (FPGA) and the iteration control and input management handled by the PS side (ARM). By adopting this structure, we can take advantage of task-level pipelines on the FPGA side, effectively utilizing time and space resources. Secondly, we utilize LDL decomposition to perform the inversion of the Hermitian matrix, which not only exhibits the lowest computational complexity and requires fewer computational resources but also achieves a higher level in the parallel pipeline mechanism compared with other alternative methods. Furthermore, the algorithm conducts iterations sequentially, utilizing the parameters derived from the previous dataset as prior information for initializing the subsequent dataset’s initial values. This approach helps to reduce the number of iterations required. Finally, with the help of Vitis HLS 2022.2 and Vivado tools, we successfully accomplished the development of a hardware design language and its implementation on the ZYNQ UltraScale+ MPSoC ZCU102 platform. Meanwhile, we have solved a direction of arrival (DOA) estimation problem using horizontal line arrays to verify the practical feasibility of the method.

Robust security model utilizing 4D hyper-digital chaotic sequence for joint-polar coding and SCMA scheme-based IoT applications

The rapid growth of Internet of Things (IoT) devices, driven by the emergence of 5G technology, necessitates faster and more secure connections for real-time data transfer. To address this, a combined approach called JPC-SCMA, which involves integrating Polar Code (PC) with sparse code multiple access (SCMA), is proposed to ensure efficient and reliable communication while minimizing errors. PC enhance hardware efficiency and throughput in 5G networks, serving as effective channel coding. SCMA enables users to decode shared resource communications, but this method introduces security concerns, especially for untrusted users. This study introduces a novel security technique for JPC-SCMA in IoT systems. It employs lightweight cipher-based security methods and a 4D-hyperdigital chaotic key generator to create necessary key sets. Simulation results confirm the effectiveness of the proposed secure system, achieving zero Bit Error Rate (BER) at SNR = 9 with a small SNR penalty (1.5 dB at 10−4 BER) compared to the less secure system. The security model generates a robust key space (∼10220 bits), thwarting exhaustive attacks. Model efficiency is validated through metrics such as Entropy, Similarity, correlation, Number of Pixel Changes Rate, and stands for Unified Average Change Intensity, especially when transmitting multiple digital images.

PARALLEL AND DISTRIBUTED COMPUTING TECHNOLOGIES FOR AUTONOMOUS VEHICLE NAVIGATION

Context. Autonomous vehicles are becoming increasingly popular, and one of the important modern challenges in their development is ensuring their effective navigation in space and movement within designated lanes. This paper examines a method of spatial orientation for vehicles using computer vision and artificial neural networks. The research focused on the navigation system of an autonomous vehicle, which incorporates the use of modern distributed and parallel computing technologies.
 Objective. The aim of this work is to enhance modern autonomous vehicle navigation algorithms through parallel training of artificial neural networks and to determine the optimal combination of technologies and nodes of devices to increase speed and enable real-time decision-making capabilities in spatial navigation for autonomous vehicles.
 Method. The research establishes that the utilization of computer vision and neural networks for road lane segmentation proves to be an effective method for spatial orientation of autonomous vehicles. For multi-core computing systems, the application of parallel programming technology, OpenMP, for neural network training on processors with varying numbers of parallel threads increases the algorithm’s execution speed. However, the use of CUDA technology for neural network training on a graphics processing unit significantly enhances prediction speeds compared to OpenMP. Additionally, the feasibility of employing PyTorch Distributed Data Parallel (DDP) technology for training the neural network across multiple graphics processing units (nodes) simultaneously was explored. This approach further improved prediction execution times compared to using a single graphics processing unit.
 Results. An algorithm for training and prediction of an artificial neural network was developed using two independent nodes, each equipped with separate graphics processing units, and their synchronization for exchanging training results after each epoch, employing PyTorch Distributed Data Parallel (DDP) technology. This approach allows for scalable computations across a higher number of resources, significantly expediting the model training process.
 Conclusions. The conducted experiments have affirmed the effectiveness of the proposed algorithm, warranting the recommendation of this research for further advancement in autonomous vehicles and enhancement of their navigational capabilities. Notably, the research outcomes can find applications in various domains, encompassing automotive manufacturing, logistics, and urban transportation infrastructure. The obtained results are expected to assist future researchers in understanding the most efficient hardware and software resources to employ for implementing AI-based navigation systems in autonomous vehicles. Prospects for future investigations may encompass refining the accuracy of the proposed parallel algorithm without compromising its efficiency metrics. Furthermore, there is potential for experimental exploration of the proposed algorithm in more intricate practical scenarios of diverse nature and dimensions.

An efficient Grain-80 stream cipher with unrolling features to enhance the throughput on hardware platform

<span>The stream cipher is a fundamental component of symmetric cryptography and offers unique implementation speed and scalability advantages. Additionally, the complexity of the cipher algorithm deployment environment forces new, appropriate designs and challenges on the already-existing cipher algorithms. To increase throughput, an efficient Grain-80 stream cipher with unrolling features is designed in this manuscript. The Grain-80 cipher uses an 80-bit key, and a 64-bit initialization vector (IV) and contains two feedback shift registers (linear and non-linear) and an output function. The register balancing and unrolling features of the proposed Grian-80 cipher combine to increase throughput while requiring little additional hardware. Low latency, fast throughput, excellent efficiency, and reduced attack susceptibility are all features of the unrolling architecture. The proposed Grain-80 cipher utilizes <1% chip area and operates at 542.7 MHz on Artix-7 field programmable gate array (FPGA). The proposed Grain-80 cipher improves the operating frequency by 14.85% over conventional Grain-80 cipher. The Grain-80 cipher obtains the throughput of 4.35 Gbps and 8.69 Gbps for unrolling factors 8 and 16, respectively. Lastly, the proposed Grain-80 cipher is compared with existing Grain-80 ciphers with improved throughput and hardware efficiency.</span>

Overview of the HL-LHC Upgrade for the CMS Level-1 Trigger

The High-Luminosity LHC will open an unprecedented window on the weak-scale nature of the universe, providing high-precision measurements of the standard model as well as searches for new physics beyond the standard model. Such precision measurements and searches require informationrich datasets with a statistical power that matches the high-luminosity provided by the Phase-2 upgrade of the LHC. Efficiently collecting those datasets will be a challenging task, given the harsh environment of 200 proton-proton interactions per LHC bunch crossing. For this purpose, CMS is designing an efficient data-processing hardware trigger (Level-1) that will include tracking information and high-granularity calorimeter information. Trigger data analysis will be performed through sophisticated algorithms such as particle flow reconstruction, including widespread use of Machine Learning. The current conceptual system design is expected to take full advantage of advances in FPGA and link technologies over the coming years, providing a high-performance, lowlatency computing platform for large throughput and sophisticated data correlation across diverse sources.

An efficient reconfigurable FIR filter design with coefficient optimization using a modified bacterial foraging optimization algorithm

ABSTRACT The digital filters play a significant role in the field of digital signal processing (DSP). The finite impulse response (FIR) filter is an attractive choice because of the ease of design and good stability. The digital filters have a wide variety of applications such as signal processing, control systems, telecommunication, etc. They are better than the analogue filters due to their performance. In recent times, software radios have achieved attention owing to requirements for integrated and reconfigurable communication systems. Hence, reconfigurations have emerged as a significant problem in the designs of FIRs. To match the frequencies of DSP applications, higher-order FIRs are required. If length of filters rises, addition and multiplication operations also increase. This paper proposes an efficient hardware design of RFIR that employs modified bacterial foraging optimizations (MBFOs) and common sub-expression eliminations (CSEs) in its executions. MBFOs output restricted counts of filter coefficients with sums of signed-power-of-two (SPT) terms while maintaining the quality of filtered responses. On obtaining coefficients, eliminations are executed by CSEs where hardware complexities are determined in terms of adders. Model sim software validated RFIRs using the Verilog code. The proposed design of RFIRs was compared with existing designs in terms of power usages, frequencies and areas.

Enhancing Real-time Simultaneous Localization and Mapping with FPGA-based EKF-SLAM's Hardware Architecture

Simultaneous Localization and Mapping enable a mobile robot that is exploring an uncharted environment to localize itself and calculate its path within the map. In the context of green technologies and applications, there is a growing need for efficient SLAM solutions that not only provide accurate localization and mapping but also minimize power consumption. EKF-SLAM is a SLAM solution based on the Extended Kalman Filter, it is well known In the domain of robotics for its ability to handle non-linear models, its ability to handle noise related to the sensors, and its extremely high degree of precision. To guarantee real-time performance, the EKF-SLAM implementation requires a high-performance hardware architecture. In light of this challenge, researchers are thinking about using parallel processing platforms like FPGAs, which can provide the required level of performance and meet strict constraints on physics, computing capacity, and electrical power. This study describes a hardware architecture's implementation design for EKF-SLAM on an FPGA platform. The entire design is built on the Cyclone 2 FPGA, which has a maximum speed of 114 MHz and 18577 LUTs, creating a highly efficient hardware architecture.

A High Efficiency Hardware Implementation of S-Boxes Based on Composite Field for Advanced Encryption Standard

A High Efficiency Hardware Implementation of S-Boxes Based on Composite Field for Advanced Encryption Standard

An Empirical Investigation on Employing Machine Learning for Balancing Home Agent Loads in Next Generation IP Mobility

Mobile IPv6 is a key technology to enable the mobility of devices on next-generation internet protocol networks. Home agents provide simple services to registered mobile nodes. In addition, the use of multiple domestic operators for load-balancing devices faces problems of synchronization and signalling overhead. Thus, most of the existing load balancing methods present a significant delay in the transmission of data packets. The machine learning approach provides an efficient hardware storage solution for balancing the load of the home agent by improving the state-work schedule. It provides a method for dynamic load balancing based on the research-consumption system. Thus, the present paper investigates the use of machine learning, specifically reinforcement learning, to enhance home agent load balancing in next-generation IP traffic. The reinforcement learning-based home agent decisions, guided by mobile node speed and registration queries, reduce latency, improve network performance, and provide dynamic solutions. The proposed method significantly reduces the delay for packet delivery by balancing the home agent load with the incorporation of reward parameters. The empirical investigation found a remarkable improvement in network reliability, as manifested by a 2.31% increase in packet delivery ratio compared to systems with existing methods.

Efficient Hardware Realization of SC Polar Decoders Using Compound Pipelined Processing Units and Auxiliary Registers

Efficient Hardware Realization of SC Polar Decoders Using Compound Pipelined Processing Units and Auxiliary Registers

A Compact and Efficient Hardware Accelerator for RNS-CKKS En/Decoding and En/Decryption

A Compact and Efficient Hardware Accelerator for RNS-CKKS En/Decoding and En/Decryption

Area-Time Efficient Hardware Implementation for Binary Ring-LWE Based Post-Quantum Cryptography

Area-Time Efficient Hardware Implementation for Binary Ring-LWE Based Post-Quantum Cryptography

Dynamic Probabilistic Pruning: A General Framework for Hardware-Constrained Pruning at Different Granularities.

Unstructured neural network pruning algorithms have achieved impressive compression ratios. However, the resulting-typically irregular-sparse matrices hamper efficient hardware implementations, leading to additional memory usage and complex control logic that diminishes the benefits of unstructured pruning. This has spurred structured coarse-grained pruning solutions that prune entire feature maps or even layers, enabling efficient implementation at the expense of reduced flexibility. Here, we propose a flexible new pruning mechanism that facilitates pruning at different granularities (weights, kernels, and feature maps) while retaining efficient memory organization (e.g., pruning exactly k -out-of- n weights for every output neuron or pruning exactly k -out-of- n kernels for every feature map). We refer to this algorithm as dynamic probabilistic pruning (DPP). DPP leverages the Gumbel-softmax relaxation for differentiable k -out-of- n sampling, facilitating end-to-end optimization. We show that DPP achieves competitive compression ratios and classification accuracy when pruning common deep learning models trained on different benchmark datasets for image classification. Relevantly, the dynamic masking of DPP facilitates for joint optimization of pruning and weight quantization in order to even further compress the network, which we show as well. Finally, we propose novel information-theoretic metrics that show the confidence and pruning diversity of pruning masks within a layer.