Efficient Hardware Research Articles

A Study on the Design Procedure of Re-Configurable Convolutional Neural Network Engine for FPGA-Based Applications

Convolutional neural networks (CNNs) have become a primary approach in the field of artificial intelligence (AI), with wide range of applications. The two computational phases for every neural network are; the training phase and the testing phase. Usually, testing is performed on high-processing hardware engines, however, the training part is still a challenge for low-power devices. There are several neural accelerators; such as graphics processing units and field-programmable-gate-arrays (FPGAs). From the design perspective, an efficient hardware engine at the register-transfer level and efficient CNN modeling at the TensorFlow level are mandatory for any type of application. Hence, we propose a comprehensive, and step-by-step design procedure for a re-configurable CNN engine. We used TensorFlow and Keras libraries for modeling in Python, whereas the register-transfer-level part was performed using Verilog. The proposed idea was synthesized, placed, and routed for 180 nm complementary metal-oxide semiconductor technology using synopsis design compiler tools. The proposed design layout occupies an area of 3.16 × 3.16 mm2. A competitive accuracy of approximately 96% was achieved for the Modified National Institute of Standards and Technology (MNIST) and Canadian Institute for Advanced Research (CIFAR-10) datasets.

Efficient Hardware Accelerator Design of Non-Linear Optimization Correlative Scan Matching Algorithm in 2D LiDAR SLAM for Mobile Robots.

Simultaneous localization and mapping (SLAM) is the major solution for constructing or updating a map of an unknown environment while simultaneously keeping track of a mobile robot's location. Correlative Scan Matching (CSM) is a scan matching algorithm for obtaining the posterior distribution probability for the robot's pose in SLAM. This paper combines the non-linear optimization algorithm and CSM algorithm into an NLO-CSM (Non-linear Optimization CSM) algorithm for reducing the computation resources and the amount of computation while ensuring high calculation accuracy, and it presents an efficient hardware accelerator design of the NLO-CSM algorithm for the scan matching in 2D LiDAR SLAM. The proposed NLO-CSM hardware accelerator utilizes pipeline processing and module reusing techniques to achieve low hardware overhead, fast matching, and high energy efficiency. FPGA implementation results show that, at 100 MHz clock, the power consumption of the proposed hardware accelerator is as low as 0.79 W, while it performs a scan match at 8.98 ms and 7.15 mJ per frame. The proposed design outperforms the ARM-A9 dual-core CPU implementation with a 92.74% increase and 90.71% saving in computing speed and energy consumption, respectively. It has also achieved 80.3% LUTs, 84.13% FFs, and 20.83% DSPs saving, as well as an 8.17× increase in frame rate and 96.22% improvement in energy efficiency over a state-of-the-art hardware accelerator design in the literature. ASIC implementation in 65 nm can further reduce the computing time and energy consumption per scan to 5.94 ms and 0.06 mJ, respectively, which shows that the proposed NLO-CSM hardware accelerator design is suitable for resource-limited and energy-constrained mobile and micro robot applications.

Replicated Simulated Annealing with a Global-Best Reference for Efficient Hardware Implementation

Replicated Simulated Annealing with a Global-Best Reference for Efficient Hardware Implementation

Efficient Cryptographic Hardware for Safety Message Verification in Internet of Connected Vehicles

An important security requirement in automotive networks is to authenticate, sign, and verify thousands of short messages per second by each vehicle. This requirement mandates the use of a high speed Elliptic Curve Cryptography (ECC) hardware. The Residue Number Systems (RNS) provide a natural parallelism and carry-free operations that could speed-up long integer arithmetics of cryptographic algorithms. In this article, we propose a high-speed RNS Montgomery modular reduction units with parallel computing to reduce the latency of the field modular operations. We propose a fully RNS-based ECC scalar multiplication co-processor for NIST-P256r1 and Brainpool256r1 standard curves and improved the scalar multiplication speed using NAF and DBC numbering systems. Compared to the literature, our scheme provides faster computation without compromising the security level. The performance of our fully RNS-ECC point multiplication meets the requirements of the automotive industry.

VHDL implementation of circular shifting‐partial transmit sequence in MIMO OFDM systems

SummaryOne of the basic issues in orthogonal frequency‐division multiplexing (OFDM) frameworks is the peak‐to‐average power ratio (PAPR). There are several PAPR reduction methods available. The partial transmit sequence (PTS) technique is considered one of the superior techniques for overcoming this issue. In this study, an efficient VHSIC hardware description language VHDL implementation of the PTS design utilising roundabout circular shifting CS was planned. The proposed structured method was designed as a real‐time prototype circuit over a field programmable gate array (FPGA) utilising the VHDL language. The implementation results of the prototype circuit in terms of the resources used in the FPGA using the Xilinx synthesis tool on the Virtex‐5 board for SISO, 2 × 2 MIMO and 4 × 4 MIMO models for N‐IFFT 64 and 256 points are presented. The structured framework effectively combined to be a compact framework with low intricacy and high speed. Testing of the implemented circuit verified its functionality. A comparison of our proposed CS‐PTS scheme with previously used PTS schemes, such as the subblock scheme, showed that our proposed method is superior in terms of hardware complexity reduction.

Ultrafast Near-Ideal Phase-Change Memristive Physical Unclonable Functions Driven by Amorphous State Variations.

There is an ever-increasing demand for next-generation devices that do not require passwords and are impervious to cloning. For traditional hardware security solutions in edge computing devices, inherent limitations are addressed by physical unclonable functions (PUF). However, realizing efficient roots of trust for resource constrained hardware remains extremely challenging, despite excellent demonstrations with conventional silicon circuits and archetypal oxide memristor-based crossbars. An attractive, down-scalable approach to design efficient cryptographic hardware is to harness memristive materials with a large-degree-of-randomness in materials state variations, but this strategy is still not well understood. Here, the utilization of high-degree-of-randomness amorphous (A) state variations associated with different operating conditions via thermal fluctuation effects is demonstrated, as well as an integrated framework for in memory computing and next generation security primitives, viz., APUF, for achieving secure key generation and device authentication. Near ideal uniformity and uniqueness without additional initial writing overheads in weak memristive A-PUF is achieved. In-memory computing empowers a strong exclusive OR (XOR-) and-repeat A PUF construction to avoid machine learning attacks, while rapid crystallization processes enable large-sized-key reconfigurability. These findings pave the way for achieving a broadly applicable security primitive for enhancing antipiracy of integrated systems and product authentication in supply chains.

B[formula omitted]N[formula omitted]: Resource efficient Bayesian neural network accelerator using Bernoulli sampler on FPGA

A resource efficient hardware accelerator for Bayesian neural network (BNN) named B2N2, Bernoulli random number based Bayesian neural network accelerator, is proposed. As neural networks expand their application into risk sensitive domains where mispredictions may cause serious social and economic losses, evaluating the NN’s confidence on its prediction has emerged as a critical concern. Among many uncertainty evaluation methods, BNN provides a theoretically grounded way to evaluate the uncertainty of NN’s output by treating network parameters as random variables. By exploiting the central limit theorem, we propose to replace costly Gaussian random number generators (RNG) with Bernoulli RNG which can be efficiently implemented on hardware since the possible outcome from Bernoulli distribution is binary. We demonstrate that B2N2 implemented on Xilinx ZCU104 FPGA board consumes only 465 DSPs and 81661 LUTs which corresponds to 50.9% and 14.3% reductions compared to Gaussian-BNN (Hirayama et al., 2020) implemented on the same FPGA board for fair comparison. We further compare B2N2 with VIBNN (Cai et al., 2018), which shows that B2N2 successfully reduced DSPs and LUTs usages by 50.9% and 57.9%, respectively. Owing to the reduced hardware resources, B2N2 improved energy efficiency by 7.50% and 57.5% compared to Gaussian-BNN (Hirayama et al., 2020) and VIBNN (Cai et al., 2018), respectively.

SCA: Search-Based Computing Hardware Architecture with Precision Scalable and Computation Reconfigurable Scheme.

Deep neural networks have been deployed in various hardware accelerators, such as graph process units (GPUs), field-program gate arrays (FPGAs), and application specific integrated circuit (ASIC) chips. Normally, a huge amount of computation is required in the inference process, creating significant logic resource overheads. In addition, frequent data accessions between off-chip memory and hardware accelerators create bottlenecks, leading to decline in hardware efficiency. Many solutions have been proposed to reduce hardware overhead and data movements. For example, specific lookup-table (LUT)-based hardware architecture can be used to mitigate computing operation demands. However, typical LUT-based accelerators are affected by computational precision limitation and poor scalability issues. In this paper, we propose a search-based computing scheme based on an LUT solution, which improves computation efficiency by replacing traditional multiplication with a search operation. In addition, the proposed scheme supports different precision multiple-bit widths to meet the needs of different DNN-based applications. We design a reconfigurable computing strategy, which can efficiently adapt to the convolution of different kernel sizes to improve hardware scalability. We implement a search-based architecture, namely SCA, which adopts an on-chip storage mechanism, thus greatly reducing interactions with off-chip memory and alleviating bandwidth pressure. Based on experimental evaluation, the proposed SCA architecture can achieve 92%, 96% and 98% computational utilization for computational precision of 4 bit, 8 bit and 16 bit, respectively. Compared with state-of-the-art LUT-based architecture, the efficiency can be improved four-fold.

Thermal Sensor Placement for Multicore Systems Based on Low-Complex Compressive Sensing Theory

As the complexity of the multicore system grows, the large workload diversity results in serious thermal problems. In a practical way, the number of placed thermal sensors is usually limited due to the manufacturing cost. In recent years, the compressive sensing (CS) theory is proven as an efficient way to reconstruct the original signal by using fewer sampling data. However, due to the high computational complexity during the signal reconstruction, the CS theory is not appropriate to apply to the real-time temperature monitoring in the current multicore system. In this article, we propose a grid-based sensor placement approach to placement the number-limited thermal sensors on the target multicore system. On the other hand, we adopt the matrix inversion bypass (MIB) property to reduce the computational complexity of two widely used signal reconstruction approaches in CS theory [i.e., the orthogonal matching pursuit (OMP) and stagewise OMP (StOMP)]. Due to the characteristic of random sampling in CS theory, the complexity of thermal sensor placement for multicore systems can be reduced significantly. In addition, the proposed MIB-based temperature reconstruction method helps to satisfy the requirement of real-time temperature estimation. The experimental results show that the proposed approach can reduce 57%–93% average full-system temperature reconstruction error compared with the previous non-CS-based approaches. Besides, we can also reduce 22%–41% computing latency compared with the current CS-based reconstruction algorithm. Due to the MIB-based operation, we can bypass the matrix inversion operation for temperature reconstruction. Therefore, the hardware overhead of the temperature reconstruction unit can be reduced significantly. Compared with the conventional approaches, we can reduce 24%–87% area overhead and improve 50%–220% hardware efficiency.

PACA: A Pattern Pruning Algorithm and Channel-Fused High PE Utilization Accelerator for CNNs

In recent years, convolutional neural networks (CNNs) have achieved significant advancements in various fields. However, the computation and storage overheads of CNNs are overwhelming for Internet-of-Things devices. Both network pruning algorithms and hardware accelerators have been introduced to empower CNN inference at the edge. Network pruning algorithms reduce the size and computational cost of CNNs by regularizing unimportant weights to zeros. However, existing works lack intrakernel structured types to tradeoff between sparsity and hardware efficiency, and the index storage for irregularly pruned networks is significant. Hardware accelerators leverage the sparsity of pruned CNNs to improve energy efficiency. However, their process element (PE) utilization rate is low because of uneven sparsity among input convolutional kernels. To overcome these problems, we propose PACA: a Pattern pruning Algorithm and Channel-fused high PE utilization Accelerator for CNNs. It includes three parts: a pattern pruning algorithm to explore the intrakernel sparsity type and reduce the index storage, a channel-fused hardware architecture to reduce the PEs’ idle rate and improve the performance, and a heuristic and taboo search-based smart fusion scheduler to analyze the idle PE problem and schedule the channel fusion in hardware. To demonstrate the effectiveness of PACA, we have implemented the software parts by Python and the hardware architecture by RTL codes. Experimental results on various datasets show that compared with an existing work, PACA can reduce the index storage overhead by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3.47\times $ </tex-math></inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$5.63\times $ </tex-math></inline-formula> with 3.85–9.12 average patterns, and it can improve the hardware performance by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.01\times $ </tex-math></inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$5.53\times $ </tex-math></inline-formula> because of PEs’ idle rate reduction.

Efficient Neuromorphic Hardware Through Spiking Temporal Online Local Learning

Local learning schemes have shown promising performance in spiking neural networks (SNNs) training and are considered a step toward more biologically plausible learning. Despite many efforts to design high-performance neuromorphic systems, a fast and efficient on-chip training algorithm is still missing, which limits the deployment of neuromorphic systems in many real-time applications. This work proposes a scalable, fast, and efficient spiking neuromorphic hardware system with on-chip local learning capability. We introduce an effective hardware-friendly local training algorithm compatible with sparse temporal input coding and binary random classification weights. The algorithm is demonstrated to deliver competitive accuracy in different tasks. The proposed digital system explores spike sparsity in communication, parallelism in vector–matrix operations and process-level dataflow, and locality of training errors, which leads to low cost and fast training speed. The system is optimized under various performance metrics. Taking into consideration energy, speed, resources, and accuracy, the proposed method shows around <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10\times $ </tex-math></inline-formula> efficiency over a recent work with a direct feedback alignment (DFA) method and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4.5\times $ </tex-math></inline-formula> efficiency over the spike-timing-dependent plasticity (STDP) method. Moreover, our hardware architecture can easily scale up with the network size at a linear rate. Thus, our method has demonstrated great potential for use in various applications, especially those demanding low latency.

Memristive Fast-Canny Operation for Edge Detection

Memristor-based in- memory computing paradigm is a promising path for edge detection in image preprocessing on end devices that reduces the computational pressure on data centers. However, the implementation of the well-performing Canny operator for edge detection faces challenges in terms of computational time and area overhead when mapped to memristor arrays. In this work, we proposed an efficient memristive one-step implementation of a fast-Canny operator. Exploiting the associative property of multiplication, the conventional Canny operator consisting of Gaussian and Sobel operators is converted into a fast-Canny operator and mapped to an array of nine parallel memristors. Then, the output currents are the final pixels of the edge image. To verify the feasibility of the method, successful edge detection with high accuracy (OIS = 0.73) is achieved in device-aware simulation under device variation (<50%) and image noise ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sigma $ </tex-math></inline-formula> = 6%). Additionally, the implementation of the fast-Canny operator on memristor arrays can reduce the processing time by half and save the area of buffer compared to the prior two-convolution Canny operation. Our work suggests that the memristive fast-Canny operator could be a promising and efficient hardware solution for edge detection at the network edge.

An Algorithm–Hardware Co-Optimized Framework for Accelerating N:M Sparse Transformers

The Transformer has been an indispensable staple in deep learning. However, for real-life applications, it is very challenging to deploy efficient Transformers due to the immense parameters and operations of models. To relieve this burden, exploiting sparsity is an effective approach to accelerate Transformers. Newly emerging Ampere graphics processing units (GPUs) leverage a 2:4 sparsity pattern to achieve model acceleration, while it can hardly meet the diverse algorithm and hardware constraints when deploying models. By contrast, we propose an algorithm–hardware co-optimized framework to flexibly and efficiently accelerate Transformers by utilizing general N:M sparsity patterns. First, from an algorithm perspective, we propose a sparsity inheritance mechanism along with inherited dynamic pruning (IDP) to obtain a series of N:M sparse candidate Transformers rapidly. A model compression scheme is further proposed to significantly reduce the storage requirement for deployment. Second, from a hardware perspective, we present a flexible and efficient hardware architecture, namely, STA, to achieve significant speedup when deploying N:M sparse Transformers. STA features not only a computing engine unifying both sparse–dense and dense–dense matrix multiplications with high computational efficiency but also a scalable softmax module eliminating the latency from intermediate off-chip data communication. Experimental results show that, compared to other methods, N:M sparse Transformers, generated using IDP, achieves an average of 6.7% improvement on accuracy with high training efficiency. Moreover, STA can achieve <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$14.47\times $ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$11.33\times $ </tex-math></inline-formula> speedups compared to Intel i9-9900X and NVIDIA RTX 2080 Ti, respectively, and perform <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.00 \,\,\sim 19.47 \times $ </tex-math></inline-formula> faster inference than the state-of-the-art field-programmable gate array (FPGA)-based accelerators for Transformers.

ESSA: Design of a Programmable Efficient Sparse Spiking Neural Network Accelerator

Spiking neural networks (SNNs) have been witnessing the developing trends to reduce the model size and improve the hardware efficiency for area- and energy-based applications, which are processed by model pruning and data compressions. However, it is challenging to exploit the unstructured sparsity of SNNs for the dense neuromorphic processors. In this article, we present an efficient sparse SNN accelerator (ESSA), which leverages both the temporal sparsity of spike events and the spatial sparsity of weights in SNN inference. It provides both the compressed weights for sparse SNNs and the uncompressed weights for compact SNNs. The self-adaptive spike compression is proposed for sparse spike scenarios, leading to the improvement of throughput by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3.2\times $ </tex-math></inline-formula> . ESSA executes a flexible fan-in–fan-out tradeoff by using combinable dendrites, which overcomes the fan-in limitation in neuromorphic systems. Furthermore, a low-latency intrachip spike multicast method is adopted to reduce the resource overhead. Implemented on the Xilinx Kintex Ultrascale field-programmable gate array (FPGA), ESSA achieves an equivalent performance of 253.1 GSOP/s and an energy efficiency of 32.1 GSOP/W for 75% weight sparsity at 140 MHz. The implementation of a four-layer fully connected SNN is expected to perform <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.6~\mu \text{s}$ </tex-math></inline-formula> per time step and the energy consumption is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$14.6~\mu \text{J}$ </tex-math></inline-formula> . Our results demonstrate that ESSA outperforms several state-of-the-art application-specific integrated circuit (ASIC) or FPGA neuromorphic processors.

EFA-Trans: An Efficient and Flexible Acceleration Architecture for Transformers

The topic of transformers is rapidly emerging as one of the most important key primitives in neural networks. Unfortunately, most hardware designs for transformers are deficient, either hardly considering the configurability of the design or failing to realize the complete inference process of transformers. Specifically, few studies have paid attention to the compatibility of different computing paradigms. Thus, this paper presents EFA-Trans, a highly efficient and flexible hardware accelerator architecture for transformers. To reach high performance, we propose a configurable matrix computing array and leverage on-chip memories optimizations. In addition, with the design of nonlinear modules and fine-grained scheduling, our architecture can perform complete transformer inference. EFA-Trans is also compatible with dense and sparse patterns, which further expands its application scenarios. Moreover, a performance analytic model is abstracted to guide the determination of architecture parameter sets. Finally, our designs are developed by RTL and evaluated on Xilinx ZCU102. Experimental results demonstrate that EFA-Trans provides 23.74× and 7.58× improvement in energy efficiency compared with CPU and GPU, respectively. It also shows DSP efficiency is between 3.59× and 21.07× higher than others, outperforming existing advanced works.

Efficient hardware implementations of lightweight Simeck Cipher for resource-constrained applications

Due to the vigorous and ever-evolving demands of the IoT field, resource-constrained devices are being deployed in such areas and several new challenges like sequestration and surveillance, have come into the picture. Multiple lightweight designs have been recommended to overcome the security issues for resource-constrained devices. In applications requiring data to be transmitted fast between various devices, loop unrolling and subsequent pipelining architectures are extremely efficient. In this paper, several efficient hardware implementations of Simeck cipher such as loop unrolling architecture and outer round pipelining technique have been proposed in order to achieve high throughput. This paper has also proposed a bit serialized architecture of the Simeck cipher that reduces the area footprint and used in less resource applications. Our Simeck Serial architecture is 29.5 times more efficient than LiCi cipher and occupies only 7% of the area occupied by LiCi cipher. Similarly, our proposed serial architecture occupies only 13% and 25% of total slices occupied by X192 and XTEA respectively while still performs 184% and 161% more efficiently. All three architectures are evaluated and compared on the basis of throughput, area utilization, and power consumption for their implementations in different FPGA platforms.

High-speed photonic neuromorphic computing using recurrent optical spectrum slicing neural networks

Neuromorphic computing using photonic hardware is a promising route towards ultrafast processing while maintaining low power consumption. Here we present and numerically evaluate a hardware concept for realizing photonic recurrent neural networks and reservoir computing architectures. Our method, called Recurrent Optical Spectrum Slicing Neural Networks (ROSS-NNs), uses simple optical filters placed in a loop, where each filter processes a specific spectral slice of the incoming optical signal. The synaptic weights in our scheme are equivalent to the filters’ central frequencies and bandwidths. Numerical application to high baud rate optical signal equalization (>100 Gbaud) reveals that ROSS-NN extends optical signal transmission reach to > 60 km, more than four times that of two state-of-the-art digital equalizers. Furthermore, ROSS-NN relaxes complexity, requiring less than 100 multiplications/bit in the digital domain, offering tenfold reduction in power consumption with respect to these digital counterparts. ROSS-NNs hold promise for efficient photonic hardware accelerators tailored for processing high-bandwidth (>100 GHz) optical signals in optical communication and high-speed imaging applications.

Artificial Tactile Recognition Enabled by Flexible Low-Voltage Organic Transistors and Low-Power Synaptic Electronics.

The advancement of self-powered intelligent strain systems for human-computer interaction is crucial toward wearable and energy-saving applications. Simultaneously, lowering operating voltage and thus reducing power consumption are of particular interests. A brain-like smart synaptic hardware system is considered as a promising candidate for low-power, parallel computing and learning processes. However, the combination of low-voltage organic transistors and energy efficient smart synapse hardware systems driven by a tactile signal has been hindered by the limited materials and technology. Here, by employing an elastomeric copolymer poly(vinylidene fluoride-co-hexafluoropropylene) (PVDF-HFP) with a high HFP content of 25 mol %, flexible, low-voltage transistors (|VG| ≤ 3 V) and a low energy consumption synapse ≤ 9.2 × 10-17 J are devised simultaneously, along with the lowest quality factor (R = Pw × VG, 2.76 × 10-16 J V). Furthermore, based on the low voltage and low power consumption characteristics, flexible artificial tactile recognition system and Morse code recognition are established without any computing supporting. Mechanical flexibility, cycling stability, image contrast enhancement functions, and simulated pattern recognition accuracy of the multilayer perceptron neural network are also simulated. This work recommends a route of exploiting low voltage, low power consumption synaptic systems and smart human-machine interfaces with low energy loss based on flexible organic synaptic transistors.

Efficient deep steering control method for self-driving cars through feature density metric

In this paper, a low cost method for input size reduction without sacrificing accuracy is proposed, which reduces required computation resources for both training and inference of deep convolutional neural network (DCNN) in the steering control of self-driving cars. Efficient processing of DCNNs is becoming prominent challenge due to its huge computation cost, number of parameters and also inadequate computation resources on power efficient hardware devices and the proposed method alleviates the problem comparing the state of the art. The proposed method introduces feature density metric (FDM) as criterion to mask and filter out regions of input image that do not contain adequate amount of features. This filtering method prevents DCNN from useless calculations belongs to feature-free regions. Compared to PilotNet, the proposed method accelerates overall training and inference phases of end-to-end (ETE) deep steering control of self-driving cars up to 1.3× and 2.0× respectively.

A CSMA/CA based MAC protocol for hybrid Power-line/Visible-light communication networks: Design and analysis

Hybrid Power-line/Visible-light Communication (HPVC) network has been one of the most promising Cooperative Communication (CC) technologies for constructing Smart Home due to its superior communication reliability and hardware efficiency. Current research on HPVC networks focuses on the performance analysis and optimization of the Physical (PHY) layer, where the Power Line Communication (PLC) component only serves as the backbone to provide power to light Emitting Diode (LED) devices. So designing a Media Access Control（MAC) protocol remains a great challenge because it allows both PLC and Visible Light Communication (VLC) components to operate data transmission, i.e., to achieve a true HPVC network CC. To solve this problem, we propose a new HPC network MAC protocol (HPVC MAC) based on Carrier Sense Multiple Access/Collision Avoidance (CSMA/CA) by combining IEEE 802.15.7 and IEEE 1901 standards. Firstly, we add an Additional Assistance (AA) layer to provide the channel selection strategies for sensor stations, so that they can complete data transmission on the selected channel via the specified CSMA/CA mechanism, respectively. Based on this, we give a detailed working principle of the HPVC MAC, followed by the construction of a joint analytical model for mathematical-mathematical validation of the HPVC MAC. In the modeling process, the impacts of PHY layer settings (including channel fading types and additive noise feature), CSMA/CA mechanisms of 802.15.7 and 1901, and practical configurations (such as traffic rate, transit buffer size) are comprehensively taken into consideration. Moreover, we prove the proposed analytical model has the solvability. Finally, through extensive simulations, we characterize the HPVC MAC performance under different system parameters and verify the correctness of the corresponding analytical model with an average error rate of 4.62% between the simulation and analytical results.