Hardware Design Language Research Articles

PEak: A Single Source of Truth for Hardware Design and Verification

Domain-specific languages for hardware can significantly enhance designer productivity, but sometimes at the cost of ease of verification. On the other hand, ISA specification languages are too static to be used during early stage design space exploration. We present PEak, an open-source hardware design and specification language, which aims to improve both design productivity and verification capability. PEak does this by providing a single source of truth for functional models, formal specifications, and RTL. PEak has been used in several academic projects, and PEak-generated RTL has been included in three fabricated hardware accelerators. In these projects, the formal capabilities of PEak were crucial for enabling both novel design space exploration techniques and automated compiler synthesis.

High-Throughput MPSoC Implementation of Sparse Bayesian Learning Algorithm

In the field of sparse signal reconstruction, sparse Bayesian learning (SBL) has excellent performance, which is accompanied by extremely high computational complexity. This paper presents an efficient SBL hardware and software (HW&SW) co-implementation method using the ZYNQ series MPSoC (multiprocessor system-on-chip). Firstly, considering the inherent challenges in parallelizing iterative algorithms like SBL, we propose an architecture based on the iterative calculations implemented on the PL side (FPGA) and the iteration control and input management handled by the PS side (ARM). By adopting this structure, we can take advantage of task-level pipelines on the FPGA side, effectively utilizing time and space resources. Secondly, we utilize LDL decomposition to perform the inversion of the Hermitian matrix, which not only exhibits the lowest computational complexity and requires fewer computational resources but also achieves a higher level in the parallel pipeline mechanism compared with other alternative methods. Furthermore, the algorithm conducts iterations sequentially, utilizing the parameters derived from the previous dataset as prior information for initializing the subsequent dataset’s initial values. This approach helps to reduce the number of iterations required. Finally, with the help of Vitis HLS 2022.2 and Vivado tools, we successfully accomplished the development of a hardware design language and its implementation on the ZYNQ UltraScale+ MPSoC ZCU102 platform. Meanwhile, we have solved a direction of arrival (DOA) estimation problem using horizontal line arrays to verify the practical feasibility of the method.

Hardware/software security co-verification and vulnerability detection: An information flow perspective

Security vulnerabilities provide attackers unauthorized access to critical resources and effective attack surfaces to compromise a system. Security verification is an emerging technique for detecting and locating such threats. However, existing security verification methods are typically restricted within the hardware or software boundary and incapable of meeting cross-layer verification requirements due to the differences in design semantics and the lack of a security model that fits both hardware and software. We attempt to address such a limitation from the perspective of information flow analysis and propose a hardware/software security co-verification method, which can check information flow security properties on fine-grained hardware information flow models. The proposed method can pinpoint security vulnerabilities by capturing information flow security property violations under clues of malicious information flows. Our information flow security model and properties are described using standard hardware design and verification languages, which allows our method to be seamlessly integrated with electronics design automation flows. Experimental results using RISC-V hardware/software designs show that the proposed method detects software, hardware and system-level security vulnerabilities, effectively.

Modular Hardware Design with Timeline Types

Modular design is a key challenge for enabling large-scale reuse of hardware modules. Unlike software, however, hardware designs correspond to physical circuits and inherit constraints from them. Timing constraints—which cycle a signal arrives, when an input is read—and structural constraints—how often a multiplier accepts new inputs—are fundamental to hardware interfaces. Existing hardware design languages do not provide a way to encode these constraints; a user must read documentation, build scripts, or in the worst case, a module’s implementation to understand how to use it. We present Filament, a language for modular hardware design that supports the specification and enforcement of timing and structural constraints for statically scheduled pipelines. Filament usestimeline types, which describe the intervals of clock-cycle time when a given signal is available or required. Filament enablessafe compositionof hardware modules, ensures that the resulting designs are correctly pipelined, and predictably lowers them to efficient hardware.

Radar Signal Processing Architecture for Early Detection of Automotive Obstacles

With the mass adoption of automotive vehicles, road accidents have become a common occurrence. One solution to this problem is to employ safety systems that can provide early warning for potential accidents. These systems alert drivers to brake or take active control of a vehicle in order to make braking safer and smoother, thereby protecting drivers and all other road traffic participants. Most such safety systems utilize millimeter-wave radar as primary sensors, and one of the main challenges is real-time data processing from multiple sensors integrated into a single passenger car. When an obstacle is too close to a vehicle, often there is insufficient time to run higher-order digital signal processing algorithms; hence, the decision to brake must be made based on low-level hardware processing only. For that purpose, a hardware generator for the early detection of automotive obstacles that does not impede the operation of higher-order signal processing algorithms is described. The proposed generator is captured in the Chisel hardware design language and a method for reducing the overall ranging latency is presented. The system constraints are calculated using an exemplary radar front-end and the proposed generator parameters. The obtained analytical results are experimentally confirmed with a prototype composed of a typical industrial radar front-end while the signal processing back-end instance of the described generator was implemented on an FPGA board. The measurements demonstrate that with the fast proximity alert, objects can be detected in less than a hundred microseconds, thus considerably reducing the system reaction delay and braking distance.

FPGA implementations of Grain v1, Mickey 2.0, Trivium, Lizard and Plantlet

In this paper, three eSTREAM Portfolio 2 ciphers: Grain v1, Mickey 2.0 and Trivium, and two Grain-like stream ciphers: Lizard and Plantlet are implemented in three versions aimed at different hardware application purposes. The hardware platform adopts Xilinx’s Spartan7 serial, and the simulations, syntheses and implementations are conducted in Vivado using the Verilog hardware design language. These implementations are compared with each other and those presented in existing literature in terms of performance metrics including: throughput, area consumption and throughput-area ratio. The basic version of Trivium achieves the highest frequency reaching a maximum of 416 Mbps and the serial version consumes the smallest area of 13 slices. In the parallel version, the maximum throughput-area ratio is 165.5 Mbps/Slice achieved by Trivium. At the same time, the basic version of the Mickey 2.0 algorithm achieved the second highest frequency of 384 Mbps, and the serial version of the Grain v1 algorithm achieved the second smallest area with 26 slices.

Comparison study of 8-PPM, 8-DPIM, and 8-RDH-PIM modulator FPGA hardware design in term of bandwidth efficiency and transmission rate

In this paper, a performance study of 8-Pulse-Position Modulation (PPM), 8-Digital Pulse Interval Modulation (DPIM), and 8-Reverse Dual Header-Pulse Interval Modulation (RDH-PIM) implementation in Verilog hardware design language is presented. The hardware design is chosen over software design since it could provide much more flexibility in term of transmission rate and reduce the workload of the processor in the complete system. Using 50 MHz clock as the reference data clock speeds, the transmission rate recorded are 11.11 Msymbol/second or 33.33 Mbps, 9.09 Msymbol/s or 27.27 Mbps, and 6.25 Msymbol/s or 18.75 Mbps for 8-RDH-PIM, 8-DPIM, and 8-PPM respectively. We conclude that 8-RDH-PIM modulator design provides better performance in term of bandwidth utilization and transmission rate as compared to 8-PPM and 8-DPIM.

Architecture design for a multi-sensor information fusion processor

This paper discusses the design of the architecture of an information fusion processor. This processor emulates the way of human thinking, namely by drawing conclusions from the obtained collection of information. Architecture design for this processor is based on Knowledge Growing System (KGS) algorithm. KGS is a novelty in Artificial Intelligence field. Compared to other AI methods, KGS focuses on the observation of the process of the knowledge growth within human brain based on information received from the surrounding environment. By using KGS algorithm, this processor works by receiving inputs from a set of sensors and possible hypotheses obtained after the processing of the information. The processor generates a value which is called as Degree of Certainty (DoC), which show the most possible hypothesis among all alternative ones. The Processor Elements which are used to perform KGS algorithm is designed based on systolic array architecture. The design of this processor is realized with VHSIC Hardware Design Language (VHDL) and synthesized by using FPGA Quartus II.13.1. The results show that the data path which has been design is able to perform the mechanism of KGS computation.

The research on edge detection algorithm of lane

In developed countries, the automation and intelligent development of vehicles has reached a relatively high level and has gradually developed in China. In recent years, algorithms for lane detection have emerged in an endless stream, but the advantages and disadvantages of comprehensive comparison of various algorithms have resulted in the following problems: First, the robustness of lane line detection is poor, mainly due to the surrounding environment of the road. The impact is greater, in traffic-intensive city streets, affected by natural factors such as trees or building shadows around the driveway; second, the real-time nature of the lane line detection is poor, affected by other marking lines on the driveway, or damaged in the lane. When the pollution is serious, the image of the lane line collected by the system is incomplete and of poor quality, which increases the difficulty of analyzing and processing data of the detection system. This article aims at the problems existing in the current lane line detection and determines the research focus of the article: (1) Improve the accuracy and real-time performance of the detection algorithm. Most of the factors affecting the detection of the lane line are generated before the image is acquired. This requires the strict pre-processing of the collected lane line image to remove a large amount of interference. After the information, not only can the detection result be more accurate but also the complexity of the algorithm be simplified, making the detection result accurate and effective. (2) Use the FPGA for verification. This paper simulates the detection algorithm from two aspects of MATLAB and FPGA, learns the working mode of the related chip and different interface protocols, optimizes the logic design through the hardware design language, and facilitates the hardware implementation of the algorithm. This method can effectively improve the image processing speed, save the logic resources, and better realize the lane recognition function. (3) Improve the existing lane line detection algorithm. There are many algorithms for lane detection, but each algorithm has its own advantages and disadvantages. Part of this article summarizes the advantages and disadvantages of these detection algorithms, analyzes their feasibility in actual detection, and improves the algorithm based on this.

FPGA-Based HD Camera System for the Micropositioning of Biomedical Micro-Objects Using a Contactless Micro-Conveyor

With recent advancements, micro-object contactless conveyers are becoming an essential part of the biomedical sector. They help avoid any infection and damage that can occur due to external contact. In this context, a smart micro-conveyor is devised. It is a Field Programmable Gate Array (FPGA)-based system that employs a smart surface for conveyance along with an OmniVision complementary metal-oxide-semiconductor (CMOS) HD camera for micro-object position detection and tracking. A specific FPGA-based hardware design and VHSIC (Very High Speed Integrated Circuit) Hardware Description Language (VHDL) implementation are realized. It is done without employing any Nios processor or System on a Programmable Chip (SOPC) builder based Central Processing Unit (CPU) core. It keeps the system efficient in terms of resource utilization and power consumption. The micro-object positioning status is captured with an embedded FPGA-based camera driver and it is communicated to the Image Processing, Decision Making and Command (IPDC) module. The IPDC is programmed in C++ and can run on a Personal Computer (PC) or on any appropriate embedded system. The IPDC decisions are sent back to the FPGA, which pilots the smart surface accordingly. In this way, an automated closed-loop system is employed to convey the micro-object towards a desired location. The devised system architecture and implementation principle is described. Its functionality is also verified. Results have confirmed the proper functionality of the developed system, along with its outperformance compared to other solutions.

Real Time Hardware Co - Simulation for Image Processing Algorithms Using Xilinx System Generator

The implementation of digital image processing required detailed knowledge of both hardware design and hardware description languages. This paper presents an efficient approach for the implementation of real time hardware digital image processing algorithms without requiring detailed knowledge of hardware design and hardware description languages. The purpose of this work is to achieve a real time hardware implementation with higher performance in both size and speed. It focuses on the implementation of an efficient architecture for image processing algorithms like segmentation (threshold) and contrast stretching by using the fewest possible system generator blocks for DSP tool, which integrates itself with the MATLAB based Simulink graphics environment and relieves the user of the textual HDL programming. While Past research has shown that the Image enhancement techniques on FPGA based on the Xilinx System Generator. This study connect between image histogram and Image enhancement techniques depending on the type of enhancement required. This paper describes also the methodology for implementing real-time DSP applications on FPGA and concept of hardware software co-simulation for digital image processing by using the Mathworks model-based design tool Simulink / Xilinx System Generator (XSG). Performances of efficient architectures are implemented on FPGA Virtex5 (XUPV5-LX110T).

A Hardware Design Language for Timing-Sensitive Information-Flow Security

Information security can be compromised by leakage via low-level hardware features. One recently prominent example is cache probing attacks, which rely on timing channels created by caches. We introduce a hardware design language, SecVerilog, which makes it possible to statically analyze information flow at the hardware level. With SecVerilog, systems can be built with verifiable control of timing channels and other information channels. SecVerilog is Verilog, extended with expressive type annotations that enable precise reasoning about information flow. It also comes with rigorous formal assurance: we prove that SecVerilog enforces timing-sensitive noninterference and thus ensures secure information flow. By building a secure MIPS processor and its caches, we demonstrate that SecVerilog makes it possible to build complex hardware designs with verified security, yet with low overhead in time, space, and HW designer effort.

A Hardware Design Language for Timing-Sensitive Information-Flow Security

Information security can be compromised by leakage via low-level hardware features. One recently prominent example is cache probing attacks, which rely on timing channels created by caches. We introduce a hardware design language, SecVerilog, which makes it possible to statically analyze information flow at the hardware level. With SecVerilog, systems can be built with verifiable control of timing channels and other information channels. SecVerilog is Verilog, extended with expressive type annotations that enable precise reasoning about information flow. It also comes with rigorous formal assurance: we prove that SecVerilog enforces timing-sensitive noninterference and thus ensures secure information flow. By building a secure MIPS processor and its caches, we demonstrate that SecVerilog makes it possible to build complex hardware designs with verified security, yet with low overhead in time, space, and HW designer effort.

ECG BASED HEART RATE MONITORING SYSTEM IMPLEMENTATION USING FPGA FOR LOW POWER DEVICES AND APPLICATIONS

This paper proposes a new design to monitor the Heart Rate from Electrocardiogram (ECG) signal. The proposed design is based on the concept of identifying the voltage level of the R-wave complex component of the ECG signal above a threshold level. A 100 Hertz sample rate is selected to sample the complex ECG signal. A dual-counter based calculation method is used to obtain the mathematical value of Heart Rate. The proposed FPGA based ECG Heart Rate monitoring system can operate with high performance with respect to the low-power and high speed. The system is designed using Verilog hardware design language and Xilinx XC3s500E FPGA.

Reconfigurable Operators: New Configuration Logic Blocks for Novel FPGA

For current FPGA architectures, the flne-grain programmable blocks are the most ∞exible ones. However, they bring in massive conflguration bits-stream and much performance loss. In this paper, we propose new conflguration logic blocks for the latest FPGA, a collection of Reconflgurable Operators (ReOps). A ReOp is a basic block which can process multiple bits data with a speciflc function set. Considering the ∞exibility and regularity, we divide ReOps into seven groups, which are arithmetic ReOps, shift ReOps, bitwise logic ReOps, Multiplier ReOps, Register ReOps, Multiplexer ReOps and Memory ReOps. The function set of ReOps is roundness for the arbitrary ASIC (Application Speciflc Integrated Circuit) design. To build the development environment for this novel FPGA, we employ a new hardware design language and hardware compiler. To compare the performance between our work and other current FPGAs, we use conflguration time and circuit delay as our evaluation measurements. And our experimental results show that our architecture achieves a great reduction on conflguration bits-stream and comparable delay compared with Virtex5 FPGA.

Investigation of Phase-Shifting and Frequency Conversion Sinusoidal Signal Generator Based on DDS and FPGA

The direct digital frequency synthesis (DDS) technology has high frequency resolution, fast frequency switching, low phase noise and higher frequency stability, so it is widely used in communications, aerospace, instrumentation and other fields. In this paper, the DDS system was designed based on Field Programmable Gate Array (FPGA) and hardware design language (VHDL). The experimental and simulation results show that the system has stable output frequency, high frequency accuracy, adjustable frequency and phase.

Automatic generation of hardware/software interfaces

Enabling new applications for mobile devices often requires the use of specialized hardware to reduce power consumption. Because of time-to-market pressure, current design methodologies for embedded applications require an early partitioning of the design, allowing the hardware and software to be developed simultaneously, each adhering to a rigid interface contract. This approach is problematic for two reasons: (1) a detailed hardware-software interface is difficult to specify until one is deep into the design process, and (2) it prevents the later migration of functionality across the interface motivated by efficiency concerns or the addition of features. We address this problem using the Bluespec Codesign Language~(BCL) which permits the designer to specify the hardware-software partition in the source code, allowing the compiler to synthesize efficient software and hardware along with transactors for communication between the partitions. The movement of functionality across the hardware-software boundary is accomplished by simply specifying a new partitioning, and since the compiler automatically generates the desired interface specifications, it eliminates yet another error-prone design task. In this paper we present BCL, an extension of a commercially available hardware design language (Bluespec SystemVerilog), a new software compiling scheme, and preliminary results generated using our compiler for various hardware-software decompositions of an Ogg Vorbis audio decoder, and a ray-tracing application.

Automatic generation of hardware/software interfaces

Enabling new applications for mobile devices often requires the use of specialized hardware to reduce power consumption. Because of time-to-market pressure, current design methodologies for embedded applications require an early partitioning of the design, allowing the hardware and software to be developed simultaneously, each adhering to a rigid interface contract. This approach is problematic for two reasons: (1) a detailed hardware-software interface is difficult to specify until one is deep into the design process, and (2) it prevents the later migration of functionality across the interface motivated by efficiency concerns or the addition of features. We address this problem using the Bluespec Codesign Language~(BCL) which permits the designer to specify the hardware-software partition in the source code, allowing the compiler to synthesize efficient software and hardware along with transactors for communication between the partitions. The movement of functionality across the hardware-software boundary is accomplished by simply specifying a new partitioning, and since the compiler automatically generates the desired interface specifications, it eliminates yet another error-prone design task. In this paper we present BCL, an extension of a commercially available hardware design language (Bluespec SystemVerilog), a new software compiling scheme, and preliminary results generated using our compiler for various hardware-software decompositions of an Ogg Vorbis audio decoder, and a ray-tracing application.

A platform for the automatic generation of attribute evaluation hardware systems

Attribute grammars (AG) allow the addition of context-sensitive properties into context free grammars, augmenting their expressional capabilities by using syntactic and semantic notations, making them in this way a really useful tool for a considerable number of applications. AGs have extensively been utilized in applications such as artificial intelligence, structural pattern recognition, compiler construction and even text editing. Obviously, the performance of an attribute evaluation system resides in the efficiency of the syntactic and semantic subsystems. In this paper, a hardware architecture for an attribute evaluation system is presented, which is based on an efficient combinatorial implementation of Earley's parallel parsing algorithm for the syntax part of the attribute grammar. The semantic part is managed by a special purpose module that traverses the parse tree and evaluates the attributes based on a proposed stack-based approach. The entire system is described in Verilog HDL (hardware design language), in a template form that given the specification of an arbitrary attribute grammar, the HDL synthesizable source code of the system is produced on the fly by a proposed automated tool. The generated code has been simulated for validation, synthesized and tested on an Xilinx FPGA (field programmable gate arrays) board for various AGs. Our method increases the performance up to three orders of magnitude compared to previous approaches, depending on the implementation, the size of the grammar and the input string length. This makes it particularly appealing for applications where attribute evaluation is a crucial aspect, like in real-time and embedded systems. Specifically, a natural language interface is presented, based on a question-answering application from the area of airline flights.

Automatic Constraint Based Test Generation for Behavioral HDL Models

With the emergence of complex high-performance microprocessors, functional test generation has become a crucial design step. Constraint-based test generation is a well-studied directed behavioral level functional test generation paradigm. The paradigm involves conversion of a given circuit model into a set of constraints and employing constraint solvers to generate tests for it. However, automatic extraction of constraints from a given behavioral hardware design language (HDL) model remained a challenging open problem. This paper proposes an approach for automatic extraction of word-level model constraints from the behavioral verilog HDL description. The scenarios to be tested are also expressed as constraints. The model and the scenario constraints are solved together using an integer solver to arrive at the necessary functional test. The effectiveness of the approach is demonstrated by automatically generating the constraint models for: 1) an exclusive-shared-invalid multiprocessor cache coherency model and 2) the 16-bit DLX-architecture, from their respective Verilog-based behavioral models. Experimental results that generate test vectors for high level scenarios like pipeline hazards, cache miss, etc., spanning over multiple time-frames are presented.